DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 8-12 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kim (US 2022/0005809).
[claim 1] A semiconductor device (fig. 11, 9B, 2, 4,7A) comprising: a substrate (LS, fig. 11, 9B); a plurality of semiconductor patterns (CH of ACT, fig. 9B, 11) spaced apart from each other in a first horizontal direction (D3, fig. 11) on the substrate, wherein each of the plurality of semiconductor patterns has first side surfaces opposing each other in the first horizontal direction and second side surfaces opposing each other in a second horizontal direction (D2, fig. 11), the first horizontal direction parallel to an upper surface of the substrate (fig. 11), the second horizontal direction parallel to the upper surface of the substrate and perpendicular to the first horizontal direction (fig. 11) ; source/drain regions (SD1, SD2 of ACT, fig. 9B, 11) on the second side surfaces of each of the plurality of semiconductor patterns; a plurality of gate patterns (EWL, SWL of WL, fig. 7A, see WL in fig. 9B, 11, [0063]) surrounding an upper surface of each of the plurality of semiconductor patterns (SWL of WL in fig. 7A wraps around the semiconductor pattern CH of ACT), a lower surface of each of the plurality of semiconductor patterns (SWL of WL in fig. 7A wraps around the semiconductor pattern CH of ACT), and the first side surfaces of each of the plurality of semiconductor patterns (SWL of WL in fig. 7A wraps around the semiconductor pattern CH of ACT); a plurality of conductive line patterns (E2 of EWL of WL in fig. 7A which is part of WL in fig. 11 ) connecting the plurality of gate patterns to each other (each semiconductor pattern CH of ACT has a wrap around gate structure SWL with interconnects EWL between the adjacent SWLs, fig. 7A, 11); and data storage structures (CAP, fig. 11, [0032]) in parallel to the plurality of semiconductor patterns in the second horizontal direction (fig. 11), wherein a thickness of each of the plurality of gate patterns surrounding a respective semiconductor pattern of the plurality of semiconductor patterns is substantially uniform (SWL in fig. 7A has constant thickness in D1 direction), , wherein the thickness of each of the plurality of conductive line patterns is defined in the second horizontal direction (D2 direction , fig. 7A), and wherein the thickness of each of the plurality of gate patterns is defined in a plane extending in the first horizontal direction (D3 direction, fig. 7A) and a vertical direction (D1 direction, fig. 7A), the vertical direction being perpendicular to the upper surface of the substrate (note that the plane of D1 and D3 has a thickness in the D1 direction, fig. 7A). As can be seen in fig. 9A and 11, the shape of the WL is square shaped and therefore the thickness of both E2 of EWL in the D2 direction and SWL in the D1 would be the same and thus a thickness of each of the plurality of conductive line patterns at a portion contacting a respective gate pattern (E2 of EWL in the D2 direction has the same thickness as SWL in the D1 direction , fig. 7A) of each of the plurality of gate patterns has a substantially same thickness as the thickness of each of the plurality of gate patterns (fig. 7A). As such the claims are anticipated.
Alternatively, assuming arguendo that Kim must be interpreted so narrowly as not to disclose a square shaped word line, the claims would not be anticipated. Nevertheless, it would have been obvious to have made the word line square shaped, since it has been held that a particular shape configuration (square shape) was a matter of choice which a person of ordinary skill in the art before the time of filing would have found obvious absent evidence that the particular configuration was critical. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
With this possible modification Kim discloses:
[claim 2] The semiconductor device of claim 1, wherein each of the plurality of conductive line patterns extends in the first horizontal direction between adjacent gate patterns of the plurality of gate patterns (fig. 11, 7A).
[claim 3] The semiconductor device of claim 2, wherein: an upper surface of each of the plurality of conductive line patterns is coplanar with an upper surface of each of the plurality of gate patterns (fig. 11), and a lower surface of each of the plurality of conductive line patterns is coplanar with a lower surface of each of the plurality of gate patterns (fig. 7A).
[claim 4] The semiconductor device of claim 1, wherein each of the plurality of conductive line patterns is integrally connected to each of the plurality of gate patterns (fig. 7A).
[claim 5] The semiconductor device of claim 1, wherein the plurality of conductive line patterns include a material that is a same material as a material of the plurality of gate patterns [0063].
[claim 8] The semiconductor device of claim 1,wherein: the source/drain regions include a first source/drain region (SD2, fig. 9B) on one side of the plurality of semiconductor patterns and a second source/drain region (SD1, fig. 9B) on an opposite side opposing the one side of the plurality of semiconductor patterns, and a first length of the first source/drain region in the second horizontal direction is different from a second length of the second source/drain region in the second horizontal direction (note that lengths are different in different parts of the source/drain regions, length of SD2 in D2 direction must be different than the length of SD1 in the D2 direction since lengths in D2 vary, fig. 9B).
[claim 9] The semiconductor device of claim 8, wherein: the first source/drain region is between the plurality of semiconductor patterns and the data storage structures, and the first length is greater than the second length (as can be seen in fig. 3B, SD2 in the center has a length while SD1 in the same center has no thickness since it is occupied by GM).
[claim 10] The semiconductor device of claim 8, wherein the first source/drain region includes a portion having a width in the first horizontal direction that increases in a direction from the data storage structures toward the plurality of semiconductor patterns ((as can be seen in fig. 3B, in the D3 direction SD2’s width increases beyond where GM is present toward the CAP structure since GM is no longer present in the center).
[claim 11] The semiconductor device of claim 1, further comprising: a plurality of vertical conductive patterns (Bl1, BL2, fig. 11) extending in a vertical direction (D1, fig. 11) perpendicular to the upper surface of the substrate and spaced apart from each other in the first horizontal direction on the substrate, wherein each semiconductor pattern of the plurality of semiconductor patterns include includes: first semiconductor patterns (CH of ACT on one side of BL1/BL2, fig. 11) on a first side of each of the plurality of vertical conductive patterns, and second semiconductor patterns (CH of ACT on the other side of BL1/BL2, fig. 11) on a second side opposing the first side of each of the plurality of vertical conductive patterns.
[claim 12] The semiconductor device of claim 1, wherein a length of each of the plurality of semiconductor patterns in a vertical direction (D1) is a substantially same length as a length of each of the source/drain regions in the vertical direction (fig. 2).
Claim(s) 13 and 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kim (US 2022/0005809).
[claim 13] A semiconductor device (fig. 11, 9B, 2, 7A), comprising: a substrate (LS, fig. 11, 9B); a plurality of horizontal structures (ACT, WL, fig. 11, 9B) and a plurality of interlayer insulating layers (GD, fig. 2) alternately stacked on the substrate; and a vertical conductive pattern (BL1, BL2, fig. 11) extending in a vertical direction perpendicular to an upper surface of the substrate on the substrate, wherein each of the plurality of horizontal structures includes: a first structure (ACT on one side of BL1/BL2, fig. 11) on a first side of the vertical conductive pattern, and a second structure (ACT on the other side of BL1/BL2, fig. 11) spaced apart from the first structure and on a second side of the vertical conductive pattern opposing the first side, wherein the vertical conductive pattern is electrically connected to the first structure and the second structure of each of the plurality of horizontal structures between the first structure and the second structure (fig. 11), and wherein each of the first structure and the second structure of each of the plurality of horizontal structures includes: a semiconductor pattern (CH of ACT, fig. 9B, 11) having first side surfaces opposing each other in a first horizontal direction (D3, fig. 11) and second side surfaces opposing each other in a second horizontal direction (D2, fig. 11), the first horizontal direction parallel to the upper surface of the substrate (fig. 11), the second horizontal direction parallel to the upper surface of the substrate and perpendicular to the first horizontal direction (fig. 11), source/drain regions including a first source/drain region (SD2, fig. 11) on one side of the second side surfaces of the semiconductor pattern, and a second source/drain region (SD1, fig. 1) on an opposite side opposing the one side of the second side surfaces of the semiconductor pattern and between the semiconductor pattern and the vertical conductive pattern, a gate pattern (WL, fig. 11, fig. 7A) surrounding an upper surface of the semiconductor pattern, a lower surface of the semiconductor pattern, and the first side surfaces of the semiconductor pattern, and a data storage structure (CAP, fig. 11, [0101]) on a side surface of the first source/drain region of the source/drain regions, wherein the first structure includes a plurality of first structures (multiple ACTs on one side of BL1/BL2, fig. 11) spaced apart from each other in the first horizontal direction, wherein the second structure includes a plurality of second structures (multiple ACTs on the other side of BL1/BL2, fig. 11) spaced apart from each other in the first horizontal direction, wherein each of the plurality of horizontal structures further includes first conductive line patterns (E2 of EWL of WL in fig. 7A which is part of WL in fig. 11 ) connecting first gate patterns (SWL of WL in fig. 7A wraps around the semiconductor pattern CH of ACT) of the plurality of first structures to each other, and second conductive line patterns (E2 of EWL of WL in fig. 7A which is part of WL in fig. 11 ) connecting second gate patterns (SWL of WL in fig. 7A wraps around the semiconductor pattern CH of ACT) of the plurality of second structures to each other, wherein a thickness of each of the first gate patterns of the plurality of first structures and a thickness of each of the second gate patterns of the plurality of second structures is substantially uniform surrounding a respective semiconductor pattern of each of the first structure and the second structure (fig. 7A), and wherein the thickness of each of the first conductive line patterns and the second conductive line patterns is defined in the second horizontal direction (fig. 7A), wherein the thickness of each of the first gate patterns of the plurality of first structures and the thickness of each of the second gate patterns of the plurality of second structures is defined in a plane extending in the first horizontal direction and the vertical direction (fig. 7A). As can be seen in fig. 9A and 11, the shape of the WL is square shaped and therefore the thickness of both E2 of EWL in the D2 direction and SWL in the D1 would be the same and thus a thickness of each of the first conductive line patterns at a portion contacting a respective one of the first gate patterns has a substantially same thickness as the thickness of each of the first gate patterns (E2 of EWL in the D2 direction has the same thickness as SWL in the D1 direction , fig. 7A), wherein a thickness of each of the second conductive line patterns at a portion contacting a respective one of the second gate patterns has a substantially same thickness as the thickness of each of the second gate patterns (E2 of EWL in the D2 direction has the same thickness as SWL in the D1 direction , fig. 7A). As such the claims are anticipated.
Alternatively, assuming arguendo that Kim must be interpreted so narrowly as not to disclose a square shaped word line, the claims would not be anticipated. Nevertheless, it would have been obvious to have made the word line square shaped, since it has been held that a particular shape configuration (square shape) was a matter of choice which a person of ordinary skill in the art before the time of filing would have found obvious absent evidence that the particular configuration was critical. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
With this possible modification Kim discloses:
[claim 15] The semiconductor device of claim 13, wherein: the vertical conductive pattern includes a plurality of vertical conductive patterns (BL1, BL2, fig. 11) spaced apart from each other in the first horizontal direction.
[claim 16] The semiconductor device of claim 15,wherein: each of the first conductive line patterns extends between adjacent first gate patterns of the first gate patterns in the first horizontal direction (fig. 11), each of the second conductive line patterns extends between adjacent second gate patterns of the second gate patterns in the first horizontal direction (fig. 11), and the first conductive line patterns are spaced apart from the second conductive line patterns (fig. 11).
[claim 17] The semiconductor device of claim 16,wherein: one side surface of each of the first conductive line patterns is coplanar with one side surface of each of the first gate patterns on a first plane (fig. 7A), and one side surface of each of the second conductive line patterns is coplanar with one side surface of each of the second gate patterns on a second plane (fig. 7A).
[claim 18] The semiconductor device of claim 13, wherein the first source/drain region has a recess portion in contact with the data storage structure and recessed by the data storage structure (SD2 is recessed relative to the CAP in fig. 9B).
Claim(s) 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kim (US 2022/0005809).
[claim 19] A semiconductor device (fig. 11, 9B, 2, 7A), comprising: a substrate (LS, fig. 11, 9B); a plurality of horizontal structures (ACT, WL, fig. 11, 9B) stacked and spaced apart from each other in a vertical direction (D1, fig. 11) perpendicular to an upper surface of the substrate; a plurality of interlayer insulating layers (GD, fig. 9B) alternately stacked with the plurality of horizontal structures; and a plurality of vertical conductive patterns (BL1, BL2, fig. 11) extending in the vertical direction based on penetrating through the plurality of horizontal structures and the plurality of interlayer insulating layers, and spaced apart from each other in a first horizontal direction (D3, fig. 11), the first horizontal direction parallel to the upper surface of the substrate (fig. 11), wherein each of the plurality of horizontal structures includes: first structures (ACT, SWL of WL on one side of BL1/BL2, fig. 11, 9B, 7A) spaced apart from each other in the first horizontal direction on a first side of the plurality of vertical conductive patterns ,first conductive line patterns (E2 of EWL of WL, fig. 7A) connecting the first structures to each other, second structures (ACT, SWL of WL on the other side of BL1/BL2, fig. 11, 9B, 7A) spaced apart from each other in the first horizontal direction on a second side of the plurality of vertical conductive patterns opposing the first side, and second conductive line patterns (E2 of EWL of WL, fig. 7A) connecting the second structures to each other, and wherein each of the first structures and the second structures includes: a semiconductor pattern (CH of ACT, fig. 9B, 11) having first side surfaces opposing each other in the first horizontal direction (D3, fig. 11) and second side surfaces opposing each other in a second horizontal direction (D2, fig. 11) parallel to the upper surface of the substrate and perpendicular to the first horizontal direction, source/drain regions (SD1, SD2 of ACT, fig. 9B, 11) on the second side surfaces of the semiconductor pattern, a gate pattern (SWL of WL , fig. 7A, 11) surrounding an upper surface of the semiconductor pattern (fig. 11), a lower surface of the semiconductor pattern (fig. 11), and the first side surfaces of the semiconductor pattern (fig. 11), and a data storage structure (CAP, fig. 11) in parallel to the semiconductor pattern in the second horizontal direction on one side of the source/drain regions wherein a thickness of each of the plurality of gate patterns surrounding a respective semiconductor pattern of the plurality of semiconductor patterns is substantially uniform (SWL in fig. 7A has constant thickness in D1 direction), , wherein the thickness of each of the plurality of conductive line patterns is defined in the second horizontal direction (D2 direction , fig. 7A), and wherein the thickness of each of the plurality of gate patterns is defined in a plane extending in the first horizontal direction (D3 direction, fig. 7A) and a vertical direction (D1 direction, fig. 7A), the vertical direction being perpendicular to the upper surface of the substrate (note that the plane of D1 and D3 has a thickness in the D1 direction, fig. 7A). As can be seen in fig. 9A and 11, the shape of the WL is square shaped and therefore the thickness of both E2 of EWL in the D2 direction and SWL in the D1 would be the same and thus a thickness of each of the plurality of conductive line patterns at a portion contacting a respective gate pattern (E2 of EWL in the D2 direction has the same thickness as SWL in the D1 direction , fig. 7A) of each of the plurality of gate patterns has a substantially same thickness as the thickness of each of the plurality of gate patterns (fig. 7A). As such the claims are anticipated.
Alternatively, assuming arguendo that Kim must be interpreted so narrowly as not to disclose a square shaped word line, the claims would not be anticipated. Nevertheless, it would have been obvious to have made the word line square shaped, since it has been held that a particular shape configuration (square shape) was a matter of choice which a person of ordinary skill in the art before the time of filing would have found obvious absent evidence that the particular configuration was critical. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
With this possible modification Kim discloses:
[claim 20] The semiconductor device of claim 19, wherein: the first conductive line patterns are integrally connected to each gate pattern of the first structures (fig. 7A), and the second conductive line patterns are integrally connected to each gate patterns of the second structures (fig. 7A).
[claim 21] The semiconductor device of claim 1, wherein each of the plurality of conductive line patterns has a substantially uniform thickness (E2 has a uniform thickness, fig. 7A).
Claim Rejections - 35 USC § 103
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0005809) in view of Ryu (US 2022/0013524).
Kim discloses the semiconductor device of claim 13, but does not explicitly provide for an interlayer insulating layer between each level of the memory cell.
Ryu discloses a semiconductor device wherein an interlayer insulating layer (LSPT, fig. 1C) is present between each level of the memory cell (MCA comprises levels MC2, MC4, fig. 1C).
It would have been obvious to one of ordinary skill in the art before the time of filing to have used Ryu’s interlayer insulating layer in Kim’s device in order to provide for horizontal structural support as we as insulation between each level of the memory cell (see [0040] of Ryu).
With this modification Kim discloses:
[claim 14] The semiconductor device of claim 13, wherein: each of the plurality of interlayer insulating layers (upon modification Kim would interlayer insulating layer LSPT from Ryu fig. 1C between level of the memory cell) includes: a first portion (portion of LSPT overlapping the gate WLL, fig. 1C Ryu) vertically overlapping the gate pattern of at least one of the first structure or the second structure of at least one horizontal structure, and a second portion (portion overlapping SD1, SD2, and CAP) vertically overlapping the source/drain regions and the data storage structure of the at least one of the first structure or the second structure of the at least one horizontal structure, and; and a thickness of the first portion in the vertical direction is smaller than a thickness of the second portion in the vertical direction (e.g. as can be seen the right edge of LSPT which overlaps SD2 and CAP is thicker than the portion of LSPT overlapped by WLL).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any interpretation applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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