DETAILED ACTION Claims 1-20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “circuitry configured to” in claims 1-6 and 8-10. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 8-10 and 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The following claim language is unclear: As per claim 8, lines 1-3 recite “respond to receipt of the interrupt from the virtual function by writing a sequential number to a memory location according to a request identifier of the virtual function” It is unclear what a sequential number means in the context of the claim. Sequential in relation to what number? Sequential to the request identifier? As per claim 9, lines 1-3 recite “wherein the virtual function is configured to submit one or more indirect buffers to a virtual ring buffer that is exposed to a single root input/output virtualization scheduler associated with the virtual function” it is unclear from the context of the claims as a whole how the virtual function submits indirect buffers to a ring buffer of an SR-IOV. According to the claim the vf is used to communicate with pf’s, and therefore it is unclear whether the request comprises buffers. As per claim 10, it recites a physical ring buffer. It is unclear how does this physical ring buffer relates to the virtual ring buffer of the claim on which it depends. Claims 16-17 recite similar limitations as claims 8-10 and therefore are rejected under the same rationale above. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3, 7, 11, 13, 18 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Haim et al. (US 11748285 B1). Regarding claim 1, Haim teaches a computing device ( Fig. 2, host configuration 200 ) comprising: host circuitry configured to provide a physical function (Col. 4, lines 52-53: physical function (PF) 220 on the PCIe endpoint device 212) ; and guest circuitry configured to provide a virtual function (Col. 4, lines 43-49: The virtual machines can be built upon, and bound by, a hypervisor layer in this example, and can each be in communication with a respective virtual function 214, 216, 218 on an external PCIe endpoint device 212. The virtual functions can perform specific tasks for the virtual machines, such as to transmit data for various data operations.) , wherein the host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis (Col. 5, lines 17-26: In the example of FIG. 2, each virtual function is assigned to a separate ordering domain, which can each be associated with a respective PCIe identifier (“PCI ID”). In this way, each virtual function can be treated as a separate virtual PCIe device even though they are all running on a single device in this example. Requests or transactions coming from different virtual functions will be associated with different PCI_ID values, such that it can be determined that the sources are unrelated and at least some of the ordering rules do not need to be enforced.) instead of a time-to-time basis that uses fixed value request identifiers in time slices. Regarding claim 3, Haim teaches wherein the host circuitry is configured to dynamically assign the request identifiers when performing direct memory access for guest circuitry (Col. 5, lines 17-26: Requests or transactions coming from different virtual functions will be associated with different PCI_ID values, such that it can be determined that the sources are unrelated and at least some of the ordering rules do not need to be enforced. For example, write requests associated with different PCI_ID values do not need to have ordering enforced, similar with completions with respect to write transactions.; Col. 10. line 13: a direct memory access (DMA)) . Regarding claim 7, Diaz-Cuellar teaches wherein the host circuitry is configured to dynamically assign a request identifier of the virtual function to an interrupt ([0031]). Regarding claim 11, it is a system type claim having similar limitations as claim 1 above. Therefore it is rejected under the same rationale above. Further, the additional limitations at least one physical processor; and physical memory comprising computer-executable instructions that, when executed by the at least one physical processor, cause the at least one physical processor to are taught by Haim in at least Claim 13 “A system, comprising: a processor; and memory including instructions that, when executed by the processor, cause the system to” Regarding claim 13, it is a system type claim having similar limitations as claim 3 above. Therefore it is rejected under the same rationale above. Regarding claim 18, it is a method type claim having similar limitations as claim 1 above. Therefore it is rejected under the same rationale above. Regarding claim 19, it is a method type claim having similar limitations as claim 3 above. Therefore it is rejected under the same rationale above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 4, 12, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Haim et al. (US 11748285 B1) in further view of Diaz-Cuellar et al. (US 2022/0276886 A1). Regarding claim 2, Haim teaches dynamically assign the request identifiers (Col. 5, lines 17-26: In the example of FIG. 2, each virtual function is assigned to a separate ordering domain, which can each be associated with a respective PCIe identifier (“PCI ID”). In this way, each virtual function can be treated as a separate virtual PCIe device even though they are all running on a single device in this example. Requests or transactions coming from different virtual functions will be associated with different PCI_ID values; Col. 13, lines 56-60: As mentioned, PCIe devices may be utilized in a shared resource environment, such as a data center or server farm. FIG. 10 illustrates an example network configuration 1000 that can be used to route communications between specific host machines or other such devices in such an environment.). Haim does not explicitly teach wherein the host circuitry is configured to dynamically assign the request identifiers in a manner that routes traffic transmitted by the guest circuitry directly to another virtual function . However, Diaz-Cuellar teaches wherein the host circuitry is configured to dynamically assign the request identifiers in a manner that routes traffic transmitted by the guest circuitry directly to another virtual function ([0031] One technique that can improve network latency in a virtualized network is input-output virtualization (IOV) Virtual Functions (VFs) or single root (SR) IOV. SR-IOV is an extension to the PCI Express (PCIe) specification that allows a device such as a network adaptor (e.g., NIC) to separate access to its resources among various PCIe hardware functions. The PCIe hardware functions include a PCIe Physical Function (PF) and one or more PCIe Virtual Functions (VFs). The PF is the primary function of the device and advertises the device's SR-IOV capabilities. The PF is associated with the Hyper-V parent partition in a virtualized environment. Each VF is associated with the PF. A VF shares one or more physical resources of the device, such as a memory (e.g., memory 116) and a network port, with the PF and other VFs on the device. Each VF is associated with a Hyper-V child partition in a virtualized environment. Each PF and VF is assigned a unique PCI Express Requester ID (RID) that allows an I/O memory management unit (IOMMU) to differentiate between different traffic streams and apply memory and interrupt translations between the PF and VFs. This allows traffic streams to be delivered directly to the appropriate Hyper-V parent or child partition. As a result, non-privileged data traffic flows from the PF to VF without affecting other VFs. SR-IOV enables network traffic to bypass the software switch layer of the Hyper-V virtualization stack. Because the VF is assigned to a child partition, the network traffic flows directly between the VF and child partition.) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Diaz-Cuellar with the teachings of Haim to use identifiers to route communication among different entities including partitions. The modification would have been motivated by the desire of combining known elements to yield predictable results. Regarding claim 4 , Haim teaches wherein the host circuitry is configured to dynamically assign the request identifiers (Col. 5, lines 17-26: In the example of FIG. 2, each virtual function is assigned to a separate ordering domain, which can each be associated with a respective PCIe identifier (“PCI ID”). In this way, each virtual function can be treated as a separate virtual PCIe device even though they are all running on a single device in this example. Requests or transactions coming from different virtual functions will be associated with different PCI_ID values). In addition, Diaz-Cuellar teaches when transmitting interrupts ([0031] One technique that can improve network latency in a virtualized network is input-output virtualization (IOV) Virtual Functions (VFs) or single root (SR) IOV. SR-IOV is an extension to the PCI Express (PCIe) specification that allows a device such as a network adaptor (e.g., NIC) to separate access to its resources among various PCIe hardware functions. The PCIe hardware functions include a PCIe Physical Function (PF) and one or more PCIe Virtual Functions (VFs). The PF is the primary function of the device and advertises the device's SR-IOV capabilities. The PF is associated with the Hyper-V parent partition in a virtualized environment. Each VF is associated with the PF. A VF shares one or more physical resources of the device, such as a memory (e.g., memory 116) and a network port, with the PF and other VFs on the device. Each VF is associated with a Hyper-V child partition in a virtualized environment. Each PF and VF is assigned a unique PCI Express Requester ID (RID) that allows an I/O memory management unit (IOMMU) to differentiate between different traffic streams and apply memory and interrupt translations between the PF and VFs. This allows traffic streams to be delivered directly to the appropriate Hyper-V parent or child partition. As a result, non-privileged data traffic flows from the PF to VF without affecting other VFs. SR-IOV enables network traffic to bypass the software switch layer of the Hyper-V virtualization stack. Because the VF is assigned to a child partition, the network traffic flows directly between the VF and child partition.) . Regarding claim 12, it is a system type claim having similar limitations as claim 2 above. Therefore it is rejected under the same rationale above. Regarding claim 14, it is a system type claim having similar limitations as claim 4 above. Therefore it is rejected under the same rationale above. Regarding claim 20, it is a method type claim having similar limitations as claim 4 above. Therefore it is rejected under the same rationale above. Claims 5-6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Haim et al. (US 11748285 B1) in further view of Ashkar et al. (US 2022/0091847 A1). Regarding claim 5 , Haim does not teach wherein: the host circuitry is configured to process a ring buffer providing an indication of an access location for a command in an indirect buffer and a context for the command; and the indication of the access location includes a request identifier of the virtual function. However, Ashkar teaches wherein: the host circuitry is configured to process a ring buffer providing an indication of an access location for a command in an indirect buffer and a context for the command ([0033] In response to identifying the indirect buffer prefetch packet 105 at the command packet ring buffer 106, the command processor 104 uses each of the entries 540, 541, and 542 to prefetch data from the corresponding indirect buffer. For example, in some embodiments the command processor prefetches data from the memory 110 at the memory address indicated by the addresses field 546. The command processor 104 maintains a table or other data structure for the indirect buffers, and stores both the value of the identifier field 545, and the value for the virtual memory identifier field 548 at the table or other data structure for subsequent use. The command processor 104 employs the indirect buffer size field 147 to identify an end or final entry of the corresponding indirect buffer, and stops prefetching data from the indirect buffer at identified final entry.) and the indication of the access location includes a request identifier of the virtual function ([0032] In particular, each of the entries 542, 543, 544 includes an identifier field 545, an addresses field 546, an indirect buffer size field 547, and a virtual memory identifier field 548. The identifier field 545 stores an identifier for the indirect buffer corresponding to the entry.). Regarding claim 6, Ashkar teaches wherein a derivative of the command in the indirect buffer is tagged with a request identifier of the virtual function ([0033]) . Regarding claim 15, it is a system type claim having similar limitations as claim 5 above. Therefore it is rejected under the same rationale above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JORGE A CHU JOY-DAVILA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0692 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 6:00am-5:00pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Aimee J Li can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-4169 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JORGE A CHU JOY-DAVILA/ Primary Examiner, Art Unit 2195