DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 11, 13, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Edirisooriya et al. (US 10,990,546 B1).
Regarding claim 1, Edirisooriya teaches a computing device (Fig. 1, host 102a and host 102b) comprising:
host circuitry configured to provide a physical function (Col. 2, lines 49-51: Each PCIe-enabled device may be associated with a physical function that specifies parameters to operate the device.); and
guest circuitry configured to provide a virtual function (Fig. 1, VM114A comprising a VF driver 116A; Col. 5, lines 6-9: For example, host 102A may include PCI interface device 106A that serve as the primary physical function 120A and support VMs 114A, 114B associated with virtual functions 122A.), wherein the host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis, wherein changing request identifiers on a command-to-command basis does not include using fixed value request identifiers in time slices (Col. 8, line 1 through Col. 9, lines 36: When processing a DMA descriptor at the top of working queue 216, DMA descriptor processing circuit 202 may inspect the DMA descriptor to determine the originating VM and target VM and to determine whether the originating VM has the appropriate access permission to the target VM. If the originating VM has the access permission, the extended logic (VMX) of processor may translate guest physical address to the host physical address using page tables. In one embodiment, the DMA descriptor may be a regular descriptor denoting a DMA access operation (write or read) between two VMs (e.g., from VFa to VFb) residing on a single host. The DMA descriptor may be in the work queue associated with VFa and the destination field of the DMA descriptor being set to VFb. The DMA descriptor processing circuit may first determine whether VFa has the access permission to write to or read from VFb based on the access control table and whether the destination data buffer associated with VFb is within the guest physical address (GPA) space of VFb shared with VFa. If the DMA descriptor processing circuit determines that VFa does not have the access permission or the destination data buffer is not within the GPA space of VFb shared with VFa, DMA descriptor processing circuit may report the error condition through the completion queue. Otherwise, for the write operation, the DMA descriptor processing circuit may generate PCIe read transactions with requester ID being set to VFa to read data from the VFa's GPA space, and write the data on PCIe bus with requester ID being set to VFb to write data to VFb's GPA space (to the region which is shared with VFa). For the read operation, the DMA descriptor processing circuit may generate PCIe read transactions with requester ID being set to VFb to read data from VFb's GPA space (from the region being shared with VFa), and write the data on PCIe bus with requester ID being set to VFa to write data to VFa's GPA space. The VMX logic circuit (e.g., VT-d logic) of the processor performs the translation from the guest physical addresses to corresponding host physical addresses using page tables. After processing the descriptor, the DMA descriptor processing circuit may write the completion of transmission status to the corresponding completion queue.)
While Edirisooriya teaches changing/setting requester ID in write transactions to VFa or VFb, which corresponds to accessing a VF of a different VM, depending on whether permission is allowed for the transaction. Edirisooriya does not explicitly teach accessing at least at least the host circuitry.
However, Edirisooriya does teach in at least Col , “Once the PCIe virtualization is enabled, each VF's configuration space may be associated with a PCI memory space of the PF, where the PCI memory space is used to map a register set. The VF device driver operates on the register set. The VF can function and appear as the PF using the register set mapped to the PCI memory space.”
As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to understand Edirisooriya’s teachings to encompass the claimed limitation because VFs and PFs are associated with an underlying memory space of the host circuitry. Therefore, an access (read or write) request that is allowed access, is dynamically changed to the VF of the other VM (i.e., VFb). Accordingly, Edirisooriya reasonably teaches the limitation as claimed.
Regarding claim 3, Edirisooriya teaches wherein the host circuitry is configured to dynamically assign the request identifiers when performing direct memory access for guest circuitry (Col. 8, line 1 through Col. 9, lines 36).
Regarding claim 11, it is a system type claim having similar limitations as claim 1 above. Therefore it is rejected under the same rationale above. Further, the additional limitations at least one physical processor; and physical memory comprising computer-executable instructions that, when executed by the at least one physical processor, cause the at least one physical processor to are taught by Edirisooriya in at least Col. 24 line 47-51 “The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element”
Regarding claim 13, it is a system type claim having similar limitations as claim 3 above. Therefore it is rejected under the same rationale above.
Regarding claim 18, it is a method type claim having similar limitations as claim 1 above. Therefore it is rejected under the same rationale above.
Regarding claim 19, it is a method type claim having similar limitations as claim 3 above. Therefore it is rejected under the same rationale above.
Claims 2, 4, 7-8, 12, 14, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Edirisooriya et al. (US 10,990,546 B1) in further view of Diaz-Cuellar et al. (US 2022/0276886 A1).
Regarding claim 2, Edirisooriya teaches wherein the host circuitry is configured to dynamically assign the request identifiers in a manner that routes [write requests] transmitted by the guest circuitry directly to another virtual function (Col. 8, line 1 through Col. 9, lines 36).
Edirisooriya does not explicitly teach wherein the host circuitry is configured to dynamically assign the request identifiers in a manner that routes traffic transmitted by the guest circuitry directly to another virtual function.
However, Diaz-Cuellar teaches wherein the host circuitry is configured to dynamically assign the request identifiers in a manner that routes traffic transmitted by the guest circuitry directly to another virtual function ([0031] One technique that can improve network latency in a virtualized network is input-output virtualization (IOV) Virtual Functions (VFs) or single root (SR) IOV. SR-IOV is an extension to the PCI Express (PCIe) specification that allows a device such as a network adaptor (e.g., NIC) to separate access to its resources among various PCIe hardware functions. The PCIe hardware functions include a PCIe Physical Function (PF) and one or more PCIe Virtual Functions (VFs). The PF is the primary function of the device and advertises the device's SR-IOV capabilities. The PF is associated with the Hyper-V parent partition in a virtualized environment. Each VF is associated with the PF. A VF shares one or more physical resources of the device, such as a memory (e.g., memory 116) and a network port, with the PF and other VFs on the device. Each VF is associated with a Hyper-V child partition in a virtualized environment. Each PF and VF is assigned a unique PCI Express Requester ID (RID) that allows an I/O memory management unit (IOMMU) to differentiate between different traffic streams and apply memory and interrupt translations between the PF and VFs. This allows traffic streams to be delivered directly to the appropriate Hyper-V parent or child partition. As a result, non-privileged data traffic flows from the PF to VF without affecting other VFs. SR-IOV enables network traffic to bypass the software switch layer of the Hyper-V virtualization stack. Because the VF is assigned to a child partition, the network traffic flows directly between the VF and child partition.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Diaz-Cuellar with the teachings of Edirisooriya to use identifiers to route communication among different entities including partitions. The modification would have been motivated by the desire of combining known elements to yield predictable results.
Regarding claim 4, Edirisooriya teaches wherein the host circuitry is configured to dynamically assign the request identifiers (Col. 8, line 1 through Col. 9, lines 36).
In addition, Diaz-Cuellar teaches when transmitting interrupts ([0031] One technique that can improve network latency in a virtualized network is input-output virtualization (IOV) Virtual Functions (VFs) or single root (SR) IOV. SR-IOV is an extension to the PCI Express (PCIe) specification that allows a device such as a network adaptor (e.g., NIC) to separate access to its resources among various PCIe hardware functions. The PCIe hardware functions include a PCIe Physical Function (PF) and one or more PCIe Virtual Functions (VFs). The PF is the primary function of the device and advertises the device's SR-IOV capabilities. The PF is associated with the Hyper-V parent partition in a virtualized environment. Each VF is associated with the PF. A VF shares one or more physical resources of the device, such as a memory (e.g., memory 116) and a network port, with the PF and other VFs on the device. Each VF is associated with a Hyper-V child partition in a virtualized environment. Each PF and VF is assigned a unique PCI Express Requester ID (RID) that allows an I/O memory management unit (IOMMU) to differentiate between different traffic streams and apply memory and interrupt translations between the PF and VFs. This allows traffic streams to be delivered directly to the appropriate Hyper-V parent or child partition. As a result, non-privileged data traffic flows from the PF to VF without affecting other VFs. SR-IOV enables network traffic to bypass the software switch layer of the Hyper-V virtualization stack. Because the VF is assigned to a child partition, the network traffic flows directly between the VF and child partition.).
Regarding claim 7, Diaz-Cuellar teaches wherein the host circuitry is configured to dynamically assign a request identifier of the virtual function to an interrupt ([0031]).
Regarding claim 8, Diaz-Cuellar teaches wherein the guest circuitry is configured to respond to receipt of the interrupt from the virtual function by writing a number to a memory location according to a request identifier of the virtual function ([0031] Each PF and VF is assigned a unique PCI Express Requester ID (RID) that allows an I/O memory management unit (IOMMU) to differentiate between different traffic streams and apply memory and interrupt translations between the PF and VFs).
Regarding claim 12, it is a system type claim having similar limitations as claim 2 above. Therefore it is rejected under the same rationale above.
Regarding claim 14, it is a system type claim having similar limitations as claim 4 above. Therefore it is rejected under the same rationale above.
Regarding claim 16, it is a system type claim having similar limitations as claim 8 above. Therefore it is rejected under the same rationale above.
Regarding claim 20, it is a method type claim having similar limitations as claim 4 above. Therefore it is rejected under the same rationale above.
Claims 5-6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Edirisooriya et al. (US 10,990,546 B1)in further view of Ashkar et al. (US 2022/0091847 A1).
Regarding claim 5, Edirisooriya does not teach wherein: the host circuitry is configured to process a ring buffer providing an indication of an access location for a command in an indirect buffer and a context for the command; and the indication of the access location includes a request identifier of the virtual function.
However, Ashkar teaches wherein: the host circuitry is configured to process a ring buffer providing an indication of an access location for a command in an indirect buffer and a context for the command ([0033] In response to identifying the indirect buffer prefetch packet 105 at the command packet ring buffer 106, the command processor 104 uses each of the entries 540, 541, and 542 to prefetch data from the corresponding indirect buffer. For example, in some embodiments the command processor prefetches data from the memory 110 at the memory address indicated by the addresses field 546. The command processor 104 maintains a table or other data structure for the indirect buffers, and stores both the value of the identifier field 545, and the value for the virtual memory identifier field 548 at the table or other data structure for subsequent use. The command processor 104 employs the indirect buffer size field 147 to identify an end or final entry of the corresponding indirect buffer, and stops prefetching data from the indirect buffer at identified final entry.) and the indication of the access location includes a request identifier of the virtual function ([0032] In particular, each of the entries 542, 543, 544 includes an identifier field 545, an addresses field 546, an indirect buffer size field 547, and a virtual memory identifier field 548. The identifier field 545 stores an identifier for the indirect buffer corresponding to the entry.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ashkar’s indirect buffer with the queue as taught by Edirisooriya. The modification would have been motivated by the desire of combining known techniques to yield predictable results.
Regarding claim 6, Ashkar teaches wherein a derivative of the command in the indirect buffer is tagged with a request identifier of the virtual function ([0033]).
Regarding claim 15, it is a system type claim having similar limitations as claim 5 above. Therefore it is rejected under the same rationale above.
Allowable Subject Matter
Claims 9-10 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE A CHU JOY-DAVILA whose telephone number is (571)270-0692. The examiner can normally be reached Monday-Friday, 6:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee J Li can be reached at (571)272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JORGE A CHU JOY-DAVILA/Primary Examiner, Art Unit 2195
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