DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/15/2026 has been entered.
Response to Arguments
Applicant's arguments filed06/15/2026 have been fully considered but they are not persuasive.
Applicants argue, see REMARKS page 10 and 11, that “Claim 1 [and similarly claim 13] is amended herein to recite "the power modulator to consume more power in a power state corresponding to presence of the idle data pattern than in a power state corresponding to absence of the idle data pattern." The cited references, whether considered individually or in the proposed combination, do not teach or suggest at least this limitation.”
The Office respectfully disagrees. Verbin fairly teaches (Para. [0004]-[0016]) that in Q-mode a “transmitter enters” an “idle period” where “the transmitter in Q-mode transmits two signals in alternation: a "stationary" signal [Para. [0060]: “the stationary idle signal”] with low PAR, and a "non-stationary" signal with low overall power, such as a pilot tone..”; “the stationary signal is chosen to have substantially the same statistical characteristics as normal transmission, rather than compromising the statistical characteristics of the Q-mode signal in favor of low PAR. The non-stationary signal is preferably a low-power, narrow-band signal, such as a pilot tone.” That is, more power is consumed/supplied by the Power Supply 36/Bias Current Control 37/the power modulator during the transmission of “the stationary idle signal” as compared to when it is not transmitted during the “idle period”). Hence it appears that the functionality of the “the stationary idle signal” equivalent to the claimed idle data pattern, hence Verbin fairly teaches "the power modulator to consume more power in a power state corresponding to presence of the idle data pattern than in a power state corresponding to absence of the idle data pattern" since less power is consumed/supplied by the Power Supply 36/Bias Current Control 37, i.e. the power modulator, during the transmission of “non-stationary idle signal” as compared to transmission of “the stationary idle signal” in the idle period.”
Applicants argue, see REMARKS page 10, that “Claim 1 is amended herein to recite "the power modulator to consume more power in a power state corresponding to presence of the idle data pattern than in a power state corresponding to absence of the idle data pattern." The cited references, whether considered individually or in the proposed combination, do not teach or suggest at least this limitation.”
Applicants argue, see REMARKS page 12, that “Claims 20 and 21 are believed to be allowable for at least the following additional reasons… Echavarri do not describe "determining presence of an idle data pattern at least partially responsive to determining the autocorrelation of the serialized data pattern exceeds a predetermined threshold," as recited in claim 20. Claim 21 depends from claim 20 and is believed to be allowable at least by virtue of its dependence.”
The Office respectfully disagrees. Echavarri fairly teaches ([0062], [0074]) the ideology of determining presence or absence of a data pattern such as a preamble, using auto-correlation where “peak is detected when an auto-correlation output exceeds a given threshold,” i.e. indicated presence of a data pattern/preamble. The office asserts that it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal generated by the idle data detector 18 in Verbin in view of ABE’s invention can be based on determining autocorrelation of a data pattern/preamble peak exceeding or not exceeding a threshold as taught by Echavarri et al. where doing so would (Echavarri et al., Para, [0004]) “provide an improved technique for preamble [data pattern] detection which gives more reliable results even under extreme radio channel signal conditions exhibiting noise, multi-path interference and clipping.”
Applicants argue, see REMARKS page 13, that “Bognanni thus describe signal transfer elements of a level shifter. They do not describe a current sink comprised by a power modulator that consumes more power in a power state corresponding to presence of the idle data pattern than in a power state corresponding to absence of the idle data pattern, as required by amended claim 1, from which claim 11 depends.”
The Office respectfully disagrees. As addressed above, Verbin fairly teaches by “a power modulator that consumes more power in a power state corresponding to presence of the idle data pattern than in a power state corresponding to absence of the idle data pattern” where Bognanni teaches the power modulator includes a current sink that controls level/voltage/power shifter by controlling “ON and OFF states by means of respective digital pulse signals Tp l and Tp2,” of the current sink/current sources 222a and 222b. Thus the combined teaches of Verbin in view of Bognanni fairly teaches the a current sink can be included in the power modulator/supply in Verbin’s invention for regulating the power supply from providing the more or less power dependency on the presence or absence of the idle data pattern.
Applicants argue, see REMARKS page 14, that “Kitamura do not describe multiple data pattern detectors that each set a respective data pattern status signal, and do not describe respective data pattern status signals of multiple data pattern detectors coupled to respective inputs of the multi-input AND gate, as recited in amended claim 10.”
The Office respectfully disagrees. Kitamura fairly teaches (Fig. 1, 3, 18, Para. [0062, [0087]) data pattern detector/“bit string detecting circuit 300” including a multi-input AND gate (Fig. 1, 3, Para. [0062], [0087]: “a multi-input AND gate F10”) and multiple data pattern detectors (Fig. 1, 3, Para. [0062], [0087]: “D latches 11 to 15”), each set a respective data pattern status signal (Fig. 18, Para. [0062]: the output of each D latch set respective data pattern status signal/logic “1” or “0” indicating the status of each corresponding bit in “the bit string”), respective data pattern status signal of the multiple data pattern detectors coupled to respective inputs of the multi-input AND gate (Fig. 1, 3, Para. [0062], [0087]: respective data pattern status signal/logic “1” or “0” of the “D latches 11 to 15” are coupled to the respective inputs of the “multi-input AND gate F10).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the idle data detector 18 in Verbin in view of ABE’s invention can be implemented to include a multi-input AND gate receiving a respective data pattern status signal from corresponding multiple data pattern detectors outputs as taught by Kitamura where doing so would (Kitamura, Para, [0001], [0146]) provide “a novel technique to be applied in the detection of a bit string having any desired pattern” and “not only can the number of components of the circuit be reduced, but also the costs can be saved.”
Applicant’s arguments (see REMARKS page 11 and 13) with respect to the any teachings by Ichiyoshi and BOGNANNI et al. teachings of claim 11 and 12 are moot because the new ground of rejection does not rely on Ichiyoshi as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of ABE (US 20120089757 A1).
Regarding Claim 1, Verbin discloses;
An apparatus (Fig. 1: “a data transmitter”), comprising:
a data pattern detector (Fig. 1: idle data detector 18) to:
determine a data pattern status of a serialized data pattern (Fig. 1, Para, [0038]: idle data detector 18 “determines when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern] generated by block 14 or 16 contain no meaningful information [i.e. idle status]”) to be received by a data-dependent power consumer (Fig. 1, Para. [0016], [0038], [0060]: “predefined idle mode symbols”/serialized data pattern symbols in the “the stationary idle signal” are then supplied to a Line Driver 34/a data-dependent power consumer)…, wherein data pattern statuses determinable by the data pattern detector include absence or presence of an idle data pattern (Para. [0004], [0015]: in Q-mode a “transmitter enters” an “idle period” where “the transmitter in Q-mode transmits…a "stationary" signal…” Para, [0038]: “An idle data detector 18 determines when the input data stream is idle…detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols ["stationary" idle signal]”. That is, the status of “the symbols [of the "stationary idle signal”/ serialized data pattern] generated by block 14 or 16” determinable the idle data detector 18 include at least a presence of an idle data pattern/idle symbols in the "stationary idle signal”); and
set a data pattern status signal (Fig. 1: output signal of idle data detector 18) to indicate the data pattern status of the serialized data pattern (Fig. 1. Para. [0038]: idle data detector 18 indicates [set a data pattern status signal - output of idle data detector 18 to encoder 22, power supply 36 and/or bias current controller 37] “when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern/"stationary" signal] generated by block 14 or 16 contain no meaningful information [i.e. idle data status]”) to be received by a data-dependent power consumer (Fig. 1, Para. [0038]: “detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols ["stationary idle signal”] which is then supplied to a Line Driver 34/a data-dependent power consumer); and
a power modulator (Fig. 1: Power Supply 36 and/or Bias Current Control 37) to set a power state of the power modulator at least partially based on the data pattern status signal (Fig. 1, Para. [0042]: Power Supply 36/Bias Current Control 37 output is set at a lower/reduced power state/level based at least on the idle data detector 18 output status signal), the power modulator to consume more power in a power state corresponding to presence of the idle data pattern than in a power state corresponding to absence of the idle data pattern (Para. [0016]: “the stationary signal is chosen to have substantially the same statistical characteristics as normal transmission, rather than compromising the statistical characteristics of the Q-mode signal in favor of low PAR. The non-stationary signal is preferably a low-power, narrow-band signal, such as a pilot tone.” That is, more power is consumed/supplied by the Power Supply 36/Bias Current Control 37/the power modulator during the transmission of “the stationary idle signal” as compared to when it is not transmitted during the “idle period”).
Verbin does not teach that outputs of the serialized data pattern comprising symbols, i.e. serialized data pattern symbols “generated by block 14 or 16” and received by idle data detector 18 is received:
“via a serial interface.”
On the other hand, in similar field of endeavor (Abstract: “a link controller that performs a process of a link layer, and a physical layer circuit that performs a process of a physical layer. The serial data transfer apparatus transmits and receives data with a destination apparatus via a serial bus. The link controller outputs idle data, which is received from the destination apparatus, to the physical layer circuit, and stops to operate of a unit responsible for generating data to transmit to the destination apparatus while outputting the idle data to the physical layer circuit”), ABE teaches that
“via a serial interface” (Fig. 1, 14, Para. [0042]: “serial data transfer apparatus 200 can be applied to any serial transfer interface that outputs idle data in an idle period”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal provided to the idle data detector 18 in Verbin’s invention can be done via a serial interface as taught by ABE where doing so would (ABE, Abstract, Para. [0026] ) “enables to output idle data conformed to the standard in an idle period of a serial data transfer apparatus and also reduce the power consumption.”
Regarding Claim 2, Verbin in view ABE of discloses all as applied to claim 1 above, where Verbin further teaches;
wherein the data pattern status determined by the data pattern detector includes presence of an idle data pattern (Para. [0038]: “idle data detector 18 determines when the input data stream is idle, i.e., when the symbols generated by block 14 or 16 contain no meaningful information’).
Regarding Claim 13, Verbin discloses;
A method, comprising:
determining a data pattern status of a serialized data pattern (Fig. 1, Para, [0038]: idle data detector 18 “determines when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern] generated by block 14 or 16 contain no meaningful information [i.e. idle status]”) to be received by a data-dependent power consumer (Fig. 1, Para. [0016], [0038], [0060]: “predefined idle mode symbols”/serialized data pattern symbols in the “the stationary idle signal” are then supplied to a Line Driver 34/a data-dependent power consumer)…, wherein data pattern statuses determinable by the data pattern detector include absence or presence of an idle data pattern (Para. [0004], [0015]: in Q-mode a “transmitter enters” an “idle period” where “the transmitter in Q-mode transmits…a "stationary" signal…” Para, [0038]: “An idle data detector 18 determines when the input data stream is idle…detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols ["stationary" idle signal]”. That is, the status of “the symbols [of the "stationary idle signal”/ serialized data pattern] generated by block 14 or 16” determinable the idle data detector 18 include at least a presence of an idle data pattern/idle symbols in the "stationary idle signal”); and
setting a data pattern status signal (Fig. 1: output signal of idle data detector 18) to indicate the data pattern status of the serialized data pattern (Fig. 1. Para. [0038]: idle data detector 18 indicates [set a data pattern status signal - output of idle data detector 18 to encoder 22, power supply 36 and/or bias current controller 37] “when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern/"stationary" signal] generated by block 14 or 16 contain no meaningful information [i.e. idle data status]”) to be received by a data-dependent power consumer (Fig. 1, Para. [0038]: “detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols ["stationary idle signal”] which is then supplied to a Line Driver 34/a data-dependent power consumer); and
modulating power consumption from a power source at least partially based on the set data pattern status signal (Fig. 1, Para. [0042]: a Power Supply 36/a power source outputs/modulates a lower/reduced power state/level based at least on the idle data detector 18 output status signal), the modulating comprising consuming more power from the power source in a power state corresponding to presence of the idle data pattern than in a power state corresponding to absence of the idle data pattern (Para. [0016]: “the stationary signal is chosen to have substantially the same statistical characteristics as normal transmission, rather than compromising the statistical characteristics of the Q-mode signal in favor of low PAR. The non-stationary signal is preferably a low-power, narrow-band signal, such as a pilot tone.” That is, more power is consumed/supplied by the Power Supply 36/Bias Current Control 37/the power modulator during the transmission of “the stationary idle signal” as compared to when it is not transmitted during the “idle period”).
Verbin does not teach that outputs of the serialized data pattern comprising symbols, i.e. serialized data pattern symbols “generated by block 14 or 16” and received by idle data detector 18 is received:
“via a serial interface.”
On the other hand, in similar field of endeavor (Abstract: “a link controller that performs a process of a link layer, and a physical layer circuit that performs a process of a physical layer. The serial data transfer apparatus transmits and receives data with a destination apparatus via a serial bus. The link controller outputs idle data, which is received from the destination apparatus, to the physical layer circuit, and stops to operate of a unit responsible for generating data to transmit to the destination apparatus while outputting the idle data to the physical layer circuit”), ABE teaches that
“via a serial interface” (Fig. 1, 14, Para. [0042]: “serial data transfer apparatus 200 can be applied to any serial transfer interface that outputs idle data in an idle period”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal provided to the idle data detector 18 in Verbin’s invention can be done via a serial interface as taught by ABE where doing so would (ABE, Abstract, Para. [0026] ) “enables to output idle data conformed to the standard in an idle period of a serial data transfer apparatus and also reduce the power consumption.”
Regarding Claim 14, Verbin in view of ABE discloses all as applied to claim 13 above, where Verbin further teaches the method comprising:
determining the data pattern status of the data pattern (Para. [0038]: “idle data detector 18 determines when the input data stream is idle, i.e., when the symbols generated by block 14 or 16 contain no meaningful information’); and
setting the data pattern status signal to indicate the determined data pattern status of the data pattern (Fig. 1, Para. [0038]: based on “the symbols generated by block 14 or 16 contain no meaningful information” idle data detector 18 generates/sets the status the output signal to indicated detections of idle symbols) .
Claims 3 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of ABE (US 20120089757 A1) further in view of Echavarri et al. (US 20030067999 A1 previously cited).
Regarding Claim 3, Verbin in view of ABE discloses all as applied to claim 1 above, where Verbin further teaches that the data pattern detector sets the data pattern status signal at least partially based on an output as addressed above, however, they do not teach the output is from;
“an autocorrelator” in the data pattern detector
On the other hand, Echavarri et al. discloses (Fig. 6) outputting a signal from;
“an autocorrelator” in the data pattern detector (Fig. 6, Para. [0043]: “The preamble detector 110 comprises an auto-correlation circuit 118 for auto-correlating the data samples received from the converter 104 and in response thereto generating various output values”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal generated by the idle data detector 18 in Verbin in view of ABE’s invention can be based on an autocorrelator as taught by Echavarri et al. where doing so would (Echavarri et al., Para, [0004]) “provide an improved technique for preamble detection which gives more reliable results even under extreme radio channel signal conditions exhibiting noise, multi-path interference and clipping.”
Regarding Claim 19, Verbin in view of ABE discloses all as applied to claim 14 above, where Verbin further teaches that the data pattern detector sets the data pattern status signal at least partially based on an output as addressed above, however, they do not teach the output is from;
“an autocorrelation of the data pattern”
On the other hand, Echavarri et al. discloses (Fig. 6) outputting a signal from;
“an autocorrelation of the data pattern” (Fig. 6, Para. [0043]: “The preamble detector 110 comprises an auto-correlation circuit 118 for auto-correlating the data samples received from the converter 104 and in response thereto generating various output values”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal generated by the idle data detector 18 in Verbin in view of ABE’s invention can be based on an autocorrelation as taught by Echavarri et al. where doing so would (Echavarri et al., Para, [0004]) “provide an improved technique for preamble detection which gives more reliable results even under extreme radio channel signal conditions exhibiting noise, multi-path interference and clipping.”
Regarding Claim 20, Verbin in view of ABE further in view of Echavarri et al. discloses all as applied to claim 19 above, where Echavarri et al. further teaches:
determining presence of an idle data pattern at least partially responsive to determining the autocorrelation of the data pattern exceeds a predetermined threshold (Para. [0062], [0074]: “an internal "previous maximum" variable PM is set equal to a predetermined threshold T… Unless certain conditions are met, the state machine then loops back to step 1010”; “A provisional peak is detected when an auto-correlation output exceeds a given threshold).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal generated by the idle data detector 18 in Verbin in view of ABE’s invention can be based on determining autocorrelation of a data pattern/preamble peak exceeding a threshold as taught by Echavarri et al. where doing so would (Echavarri et al., Para, [0004]) “provide an improved technique for preamble [data pattern] detection which gives more reliable results even under extreme radio channel signal conditions exhibiting noise, multi-path interference and clipping.”
Regarding Claim 21, Verbin in view of ABE further in view of Echavarri et al. discloses all as applied to claim 20 above, where Echavarri et al. further teaches:
determining absence of an idle pattern status at least partially responsive to determining the determined autocorrelation does not exceed the predetermined threshold (Para. [0062], [0074]: “an internal "previous maximum" variable PM is set equal to a predetermined threshold T… Unless certain conditions are met, the state machine then loops back to step 1010”; “A provisional peak is detected when an auto-correlation output exceeds a given threshold. That is, auto-correlation fails (i.e. pattern is absent/not detected) when an auto-correlation output does not exceed a given threshold).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal generated by the idle data detector 18 in Verbin in view of ABE’s invention can be based on determining autocorrelation of a data pattern/preamble peak not exceeding a threshold as taught by Echavarri et al. where doing so would (Echavarri et al., Para, [0004]) “provide an improved technique for preamble [data pattern] detection which gives more reliable results even under extreme radio channel signal conditions exhibiting noise, multi-path interference and clipping.”
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of ABE (US 20120089757 A1) further in view of BOGNANNI et al. (US 20210351686 A1 previously cited).
Regarding Claim 7, Verbin in view of ABE discloses all as applied to claim 1 above, where Verbin further teaches that the power modulator provides/outputs DC power (Para. [0040]) based on the power state of the power modulator as addressed above, however, they do not teach that power to the power modulator is provided by:
“a power source”.
On the other hand, BOGNANNI et al. discloses (Fig. 1, Para. [0002], [0031]) power supplies comprising;
“a power source” (Fig. 1, Para. [0042]: “a HV rail DC voltage source 11”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that DC power generated by at least the Power Supply 36 in Verbin in view of ABE’s invention can include a HV rail DC voltage source 11/power source as taught by BOGNANNI et al. in order (BOGNANNI et al., Para, [0038]) “to provide electrical power to the power devices.”
Regarding Claim 8, Verbin in view of ABE further in view of BOGNANNI et al. discloses all as applied to claim 7 above, where BOGNANNI et al. further teaches:
wherein the power source to provide power to the data-dependent power consumer (Fig. 1, Para. [0038]: HV rail DC voltage source 11 provides power to other power devices such as the data-dependent power consumer/Line Driver 34 in Verbin’s invention).
Regarding Claim 9, Verbin in view of ABE further in view of BOGNANNI et al. discloses all as applied to claim 8 above, where Verbin further teaches:
wherein the data-dependent power consumer comprises a data converter (Fig. 1, Para. [0038]: a Line Driver 34).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of ABE (US 20120089757 A1) further in view of BOGNANNI et al. (US 20210351686 A1 previously cited) still further in view of Afghahi et al. (US 6362666 B1).
Regarding Claim 11, Verbin in view of ABE further in view of BOGNANNI et al. discloses all as applied to claim 1 above, where Verbin further teaches that the power modulator provides/outputs DC power (Para. [0040]) based on the power state of the power modulator as addressed above, however, they do not teach that:
the power modulator comprises a current sink.
On the other hand, Afghahi et al. discloses (Fig. 3, 5, col. 4, line 21-56, claim 4) power supply/modulator comprising;
a current sink (Fig. 3, 5: power supplies/modulators 320, 322 and 318 each includes a current sink, i.e. transistors 369, 368, 315, 366, 357, 363; col. line : “the precharge circuit has two components 532 and 536 which allow it to both source and sink current… The component 510 has a CMOS inverter”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that DC power generated by at least the Power Supply 36 in Verbin in view of ABE further in view of BOGNANNI et al.’s invention can include a current sink as taught by Afghahi et al. where doing so would provide (Afghahi et al., Para, [0038]) “for reducing the recovery and settling time of the node voltage when the node is suddenly subjected to a large, capacitive load.”
Regarding Claim 12, Verbin in view of ABE further in view of BOGNANNI et al. still further in view of Afghahi et al. discloses all as applied to claim 11 above, where Afghahi et al. further teaches:
wherein the current sink comprises one or more CMOS inverters (Fig. 3, col. 4, line 21-56, claim 4: “a CMOS implementation in which the precharge circuit contains a single p-channel MOS field effect transistor (FET) 363 connected between a positive power supply Vs1 and the output node 120 of the amplifier 104… includes a number of CMOS inverters 320, 322, and 318 that are cascaded …”).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of ABE (US 20120089757 A1) in view of Kitamura (US 20020029233 A1 previously cited).
Regarding Claim 10, Verbin in view of ABE discloses all as applied to claim 1 as addressed above, however they do not teach wherein the data pattern detector comprises:
a multi-input AND gate; and
multiple data pattern detectors each to set a respective data pattern status signal, respective data pattern status signals of the multiple data pattern detectors coupled to respective inputs of the multi-input AND gate.
On the other hand, Kitamura (US 20020029233 A1) discloses (Fig. 3, 18) data pattern detector (Fig. 18: “bit string detecting circuit 300”) comprises;
a multi-input AND gate (Fig. 1, 3, 18, Para. [0062], [0087]: “a multi-input AND gate F10”/ “a multi-input AND gate F110”) and
multiple data pattern detectors (Fig. 1, 3, 18 Para. [0062], [0087]: “D latches 11 to 15”/ “D latches 111 to 115” and “D latches 311 to 315”), each set a respective data pattern status signal (Fig. 3, 18, Para. [0062]: the output of each D latch set respective data pattern status signal/logic “1” or “0” indicating the status of each corresponding bit in “the bit string”), respective data pattern status signal of the multiple data pattern detectors coupled to respective inputs of the multi-input AND gate (Fig. 1, 3, Para. [0062], [0087]: respective data pattern status signal/logic “1” or “0” of the “D latches 11 to 15” are coupled to the respective inputs of the “multi-input AND gate F10).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the idle data detector 18 in Verbin in view of ABE’s invention can be implemented to include a multi-input AND gate receiving a respective data pattern status signal from corresponding multiple data pattern detectors outputs as taught by Kitamura where doing so would (Kitamura, Para, [0001], [0146]) provide “a novel technique to be applied in the detection of a bit string having any desired pattern” and “not only can the number of components of the circuit be reduced, but also the costs can be saved.”
Allowable Subject Matter
Claim 4-6, 15-18 and 22 is allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior at of record, either alone or in combination fails to fairly teach ort suggest the following configuration:
“a data pattern detector to set a data pattern status signal to indicate a data pattern status of a data pattern to be received by a data-dependent power consumer, the data pattern detector
an XOR gate to continuously compare symbols presented at its inputs on every clock cycle, and generate an output to indicate a difference between the symbols; and
a filter to process the output of the XOR gate and set an output of the filter to indicate a frequency-stability of the output of the XOR gate; and
a power modulator to set a power state of the power modulator at least partially based on the data pattern status signal” as recited in claim 4;
“identifying relationships between symbols of the data pattern;
determining a data pattern status of the data pattern at least partially based on a frequency at which the identified relationships change; and
setting the data pattern status signal to indicate the determined data pattern status of the data pattern” as recited in claim 15;
“a serial interface including multiple lanes and multiple data-dependent power consumers;
a power source to provide power to the multiple data-dependent power consumers;
multiple data pattern detectors to set respective data pattern status signals to indicate data pattern status of data patterns received at respective ones of the multiple lanes of the serial interface; and
one or more power modulators to set power consumed from the power source by the one more power modulators at least partially based on the data pattern status signals” as recited in claim 22.
Claims 5-6 and 16-18 are allowable for at least its dependency on claim 4 and 15, respectively.
Conclusion
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633
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