DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/15/2024 was filed on 04/15/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claims 1-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of Ichiyoshi (US 20040255216 A1).
Regarding Claim 1, Verbin discloses;
An apparatus (Fig. 1: “a data transmitter”), comprising:
a data pattern detector (Fig. 1: idle data detector 18) to:
determine a data pattern status of a serialized data pattern (Fig. 1, Para, [0038]: idle data detector 18 “determines when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern] generated by block 14 or 16 contain no meaningful information [i.e. idle data status]”) to be received by a data-dependent power consumer (Fig. 1, Para. [0038]: “predefined idle mode symbols”/serialized data pattern symbols are then supplied to a Line Driver 34/a data-dependent power consumer)…, wherein data pattern statuses determinable by the data pattern detector include absence or presence of an idle data pattern (Para, [0038]: “An idle data detector 18 determines when the input data stream is idle…detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols”. That is, the status of “the symbols [serialized data pattern] generated by block 14 or 16” determinable the idle data detector 18 include at least a presence of an idle data pattern/idle symbols); and
set a data pattern status signal (Fig. 1: output signal of idle data detector 18) to indicate [[a]] the data pattern status of [[a]] the serialized data pattern (Fig. 1. Para. [0038]: idle data detector 18 indicates [set a data pattern status signal - output of idle data detector 18 to encoder 22, power supply 36 and/or bias current controller 37] “when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern] generated by block 14 or 16 contain no meaningful information [i.e. idle data status].”) to be received by a data-dependent power consumer (Fig. 1, Para. [0038]: “detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols” which is then supplied to a Line Driver 34/a data-dependent power consumer); and
a power modulator (Fig. 1: Power Supply 36 and/or Bias Current Control 37) to set a power state of the power modulator at least partially based on the data pattern status signal (Fig. 1, Para. [0042]: Power Supply 36/Bias Current Control 37 output is set at a lower/reduced power state/level based at least on the idle data detector 18 output status signal).
Verbin does not teach that outputs of the serialized data pattern comprising symbols, i.e. serialized data pattern symbols “generated by block 14 or 16” and received by idle data detector 18 is received:
“via a serial interface.”
On the other hand, in similar field of endeavor (Para. [0010]: “an IDLE packet generating section for providing an IDLE packet to fill an empty space in serial data transmitted”), Ichiyoshi teaches that
“via a serial interface (Fig. 4, 5, Para. [0047]: “the O/E decoders…are examples of the serial interface” the provides serialized data pattern symbol/“R_DATA” to the IDLE packet generating section 320B via the multiplexer).”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal provided to the idle data detector 18 in Verbin’s invention can be done via a serial interface as taught by Ichiyoshi where doing so would (Ichiyoshi, Para, [0013]) “provide an improved method for reducing power consumption of a transmitter during idle periods.”
Regarding Claim 2, Verbin in view of Ichiyoshi discloses all as applied to claim 1 above, where Verbin further teaches;
wherein the data pattern status determined by the data pattern detector includes presence of an idle data pattern (Para. [0038]: “idle data detector 18 determines when the input data stream is idle, i.e., when the symbols generated by block 14 or 16 contain no meaningful information’).
Regarding Claim 13, Verbin discloses;
A method, comprising:
determining a data pattern status of a serialized data pattern (Fig. 1, Para, [0038]: idle data detector 18 “determines when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern] generated by block 14 or 16 contain no meaningful information [i.e. idle data status]”) to be received by a data-dependent power consumer (Fig. 1, Para. [0038]: “predefined idle mode symbols”/serialized data pattern symbols are then supplied to a Line Driver 34/a data-dependent power consumer)…, wherein data pattern statuses determinable by the data pattern detector include absence or presence of an idle data pattern (Para, [0038]: “An idle data detector 18 determines when the input data stream is idle…detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols”. That is, the status of “the symbols [serialized data pattern] generated by block 14 or 16” determinable the idle data detector 18 include at least a presence of an idle data pattern/idle symbols); and
setting a data pattern status signal (Fig. 1: output signal of idle data detector 18) to indicate [[a]] the data pattern status of [[a]] the serialized data pattern (Fig. 1. Para. [0038]: idle data detector 18 indicates [set a data pattern status signal - output of idle data detector 18 to encoder 22, power supply 36 and/or bias current controller 37] “when the input data stream [serialized data pattern] is idle, i.e., when the symbols [serialized data pattern] generated by block 14 or 16 contain no meaningful information [i.e. idle data status].”) to be received by a data-dependent power consumer (Fig. 1, Para. [0038]: “detector 18 signals a data encoder 22 to replace the symbols from block 16 with predefined idle mode symbols” which is then supplied to a Line Driver 34/a data-dependent power consumer); and
modulating power consumption from a power source at least partially based on the set data pattern status signal (Fig. 1, Para. [0042]: a Power Supply 36/a power source outputs/modulates a lower/reduced power state/level based at least on the idle data detector 18 output status signal), wherein the power source provides power to the data-dependent power consumer (Fig. 1, Para. [0038]: Power Supply 36 “supplies power to a Line Driver 34/a data-dependent power consumer).
Verbin does not teach that outputs of the serialized data pattern comprising symbols, i.e. serialized data pattern symbols “generated by block 14 or 16” and received by idle data detector 18 is received:
“via a serial interface.”
On the other hand, in similar field of endeavor (Para. [0010]: “an IDLE packet generating section for providing an IDLE packet to fill an empty space in serial data transmitted”), Ichiyoshi teaches that
“via a serial interface (Fig. 4, 5, Para. [0047]: “the O/E decoders…are examples of the serial interface” the provides serialized data pattern symbol/“R_DATA” to the IDLE packet generating section 320B via the multiplexer).”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal provided to the idle data detector 18 in Verbin’s invention can be done via a serial interface as taught by Ichiyoshi where doing so would (Ichiyoshi, Para, [0013]) “provide an improved method for reducing power consumption of a transmitter during idle periods.”
Regarding Claim 14, Verbin in view of Ichiyoshi discloses all as applied to claim 13 above, where Verbin further teaches the method comprising:
determining the data pattern status of the data pattern (Para. [0038]: “idle data detector 18 determines when the input data stream is idle, i.e., when the symbols generated by block 14 or 16 contain no meaningful information’); and
setting the data pattern status signal to indicate the determined data pattern status of the data pattern (Fig. 1, Para. [0038]: based on “the symbols generated by block 14 or 16 contain no meaningful information” idle data detector 18 generates/sets the status the output signal to indicated detections of idle symbols) .
Claims 3 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of Ichiyoshi (US 20040255216 A1) further in view of Echavarri et al. (US 20030067999 A1 previously cited).
Regarding Claim 3, Verbin in view of Ichiyoshi discloses all as applied to claim 1 above, where Verbin further teaches that the data pattern detector sets the data pattern status signal at least partially based on an output as addressed above, however, they do not teach the output is from;
“an autocorrelator” in the data pattern detector
On the other hand, Echavarri et al. discloses (Fig. 6) outputting a signal from;
“an autocorrelator” in the data pattern detector (Fig. 6, Para. [0043]: “The preamble detector 110 comprises an auto-correlation circuit 118 for auto-correlating the data samples received from the converter 104 and in response thereto generating various output values”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal generated by the idle data detector 18 in Verbin in view of Ichiyoshi’s invention can be based on an autocorrelator as taught by Echavarri et al. where doing so would (Echavarri et al., Para, [0004]) “provide an improved technique for preamble detection which gives more reliable results even under extreme radio channel signal conditions exhibiting noise, multi-path interference and clipping.”
Regarding Claim 19, Verbin in view of Ichiyoshi discloses all as applied to claim 14 above, where Verbin further teaches that the data pattern detector sets the data pattern status signal at least partially based on an output as addressed above, however, they do not teach the output is from;
“an autocorrelation of the data pattern”
On the other hand, Echavarri et al. discloses (Fig. 6) outputting a signal from;
“an autocorrelation of the data pattern” (Fig. 6, Para. [0043]: “The preamble detector 110 comprises an auto-correlation circuit 118 for auto-correlating the data samples received from the converter 104 and in response thereto generating various output values”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the output/data pattern status signal generated by the idle data detector 18 in Verbin in view of Ichiyoshi’s invention can be based on an autocorrelation as taught by Echavarri et al. where doing so would (Echavarri et al., Para, [0004]) “provide an improved technique for preamble detection which gives more reliable results even under extreme radio channel signal conditions exhibiting noise, multi-path interference and clipping.”
Regarding Claim 20, Verbin in view of Ichiyoshi further in view of Echavarri et al. discloses all as applied to claim 19 above, where Echavarri et al. further teaches:
determining presence of an idle data pattern at least partially responsive to determining the autocorrelation of the data pattern exceeds a predetermined threshold (Para. [0062], [0074]: “an internal "previous maximum" variable PM is set equal to a predetermined threshold T… Unless certain conditions are met, the state machine then loops back to step 1010”; “A provisional peak is detected when an auto-correlation output exceeds a given threshold).
Regarding Claim 21, Verbin in view of Ichiyoshi further in view of Echavarri et al. discloses all as applied to claim 20 above, where Echavarri et al. further teaches:
determining absence of an idle pattern status at least partially responsive to determining the determined autocorrelation does not exceed the predetermined threshold (Para. [0062], [0074]: “an internal "previous maximum" variable PM is set equal to a predetermined threshold T… Unless certain conditions are met, the state machine then loops back to step 1010”; “A provisional peak is detected when an auto-correlation output exceeds a given threshold. That is, auto-correlation fails (i.e. pattern is absent/not detected) when an auto-correlation output does not exceed a given threshold).
Claims 7-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of Ichiyoshi (US 20040255216 A1) further in view of BOGNANNI et al. (US 20210351686 A1 previously cited).
Regarding Claim 7, Verbin in view of Ichiyoshi discloses all as applied to claim 1 above, where Verbin further teaches that the power modulator provides/outputs DC power (Para. [0040]) based on the power state of the power modulator as addressed above, however, they do not teach that power to the power modulator is provided by:
“a power source”.
On the other hand, BOGNANNI et al. discloses (Fig. 1, Para. [0002], [0031]) power supplies comprising;
“a power source” (Fig. 1, Para. [0042]: “a HV rail DC voltage source 11”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that DC power generated by at least the Power Supply 36 in Verbin in view of Ichiyoshi’s invention can include a HV rail DC voltage source 11/power source as taught by BOGNANNI et al. in order (BOGNANNI et al., Para, [0038]) “to provide electrical power to the power devices.”
Regarding Claim 8, Verbin in view of Ichiyoshi further in view of BOGNANNI et al. discloses all as applied to claim 7 above, where BOGNANNI et al. further teaches:
wherein the power source to provide power to the data-dependent power consumer (Fig. 1, Para. [0038]: HV rail DC voltage source 11 provides power to other power devices such as the data-dependent power consumer/Line Driver 34 in Verbin’s invention).
Regarding Claim 9, Verbin in view of Ichiyoshi further in view of BOGNANNI et al. discloses all as applied to claim 8 above, where Verbin further teaches:
wherein the data-dependent power consumer comprises a data converter (Fig. 1, Para. [0038]: a Line Driver 34).
Regarding Claim 11, Verbin in view of Ichiyoshi further in view of BOGNANNI et al. discloses all as applied to claim 7 above, where BOGNANNI et al. further teaches:
wherein the power modulator comprises a current sink (Fig. 1, 2, Para. [0060]: “a half-bridge switching circuit” implemented in a power supply includes a “current source or generator 222a, 222b”/current sink that “sinks current”).
Regarding Claim 12, Verbin in view of Ichiyoshi further in view of BOGNANNI et al. discloses all as applied to claim 11 above, where BOGNANNI et al. further teaches:
wherein the current sink comprises one or more CMOS inverters (Fig. 1, 2, Para. [0061]: “current source or generator 222a, 222b” may be implemented based on “Bipolar-CMOS-DMOS technology”).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Verbin (US 20030031269 A1 previously cited) in view of Ichiyoshi (US 20040255216 A1) in view of Kitamura (US 20020029233 A1 previously cited).
Regarding Claim 10, Verbin in view of Ichiyoshi discloses all as applied to claim 1 as addressed above, however they do not teach wherein the data pattern detector comprises:
a multi-input AND gate; and
multiple data pattern detectors, respective outputs of the multiple data pattern detectors coupled to respective inputs of the multi-input AND gate.
On the other hand, Kitamura (US 20020029233 A1) discloses (Fig. 18) data pattern detector (Fig. 18: “bit string detecting circuit 300”) comprises;
a multi-input AND gate (Fig. 1, 3, Para. [0062], [0087]: “a multi-input AND gate F10”); and
multiple data pattern detectors (Fig. 1, 3, Para. [0062], [0087]: “D latches 11 to 15”), respective outputs of the multiple data pattern detectors coupled to respective inputs of the multi-input AND gate (Fig. 1, 3, Para. [0062], [0087]: respective outputs of the “D latches 11 to 15” are coupled to the respective inputs of the “a multi-input AND gate F10”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the idle data detector 18 in Verbin in view of Ichiyoshi’s invention can be implemented to include a multi-input AND gate receiving output of multiple data pattern detectors outputs as taught by Kitamura where doing so would (Kitamura, Para, [0001], [0146]) provide “a novel technique to be applied in the detection of a bit string having any desired pattern” and “not only can the number of components of the circuit be reduced, but also the costs can be saved.”
Allowable Subject Matter
Claim 4-6, 15-18 and 22 is allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior at of record, either alone or in combination fails to fairly teach ort suggest the following configuration:
“a data pattern detector to set a data pattern status signal to indicate a data pattern status of a data pattern to be received by a data-dependent power consumer; comprising:
an XOR gate to continuously compare symbols presented at its inputs on every clock cycle, and generate an output to indicate a difference between the symbols; and
a filter to process the output of the XOR gate and set an output of the filter to indicate a frequency-stability of the output of the XOR ate; and
a power modulator to set a power state of the power modulator at least partially based on the data pattern status signal” as recited in claim 4;
“identifying relationships between symbols of the data pattern;
determining a data pattern status of the data pattern at least partially based on a frequency at which the identified relationshipschange; and
setting the data pattern status signal to indicate the determined data pattern status of the data pattern” as recited in claim 15;
“a serial interface including multiple lanes and multiple data-dependent power consumers;
a power source to provide power to the multiple data-dependent power consumers;
multiple data pattern detectors to set respective data pattern status signals to indicate data pattern status of data patterns received at respective ones of the multiple lanes of the serial interface; and
one or more power modulators to set power consumed from the power source by the one more power modulators at least partially based on the data pattern status signals” as recited in claim 22.
Claims 5-6 and 16-18 are allowable for at least its dependency on claim 4 and 15, respectively.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMNEET SINGH whose telephone number is (571)272-2414. The examiner can normally be reached 9:30am to 5:30pm.
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633