Prosecution Insights
Last updated: October 27, 2026
Application No. 18/473,289

HIGH-FREQUENCY MODULE

Final Rejection §102§112
Filed
Sep 25, 2023
Priority
Mar 31, 2021 — JP 2021-060426 +1 more
Examiner
SASSERATH, ELISA MARIE
Art Unit
2841
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
37 granted / 41 resolved
+22.2% vs TC avg
Moderate +11% lift
Without
With
+11.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§103
60.7%
+20.7% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 41 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, filed 5/5/2026, with respect to the rejection(s) of claims 1-20 under 102 and 103have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of amendments made to independent claims 1 and 11. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 7, 9-10, 17, and 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claims 7, 9-10, 17, and 19-20 introduce a “fifth electronic component.” This item is not disclosed in the specification filed 9/25/2023 and therefore would be considered new matter. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, 8 and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Matsumoto (WO 2020022180 A1) Regarding claim 1, Matsumoto teaches a high-frequency module, comprising: a first module substrate (41 first module substrate) including a first major surface (411 main surface) opposite to a second major surface (412 main surface, Fig 3 pg 31); a second module substrate (42 second module substrate) including a third major surface (421 main surface) opposite to a fourth major surface (422 main surface), the third major surface being disposed facing the second major surface (fig 3 pg 31); a plurality of electronic components disposed between the second major surface and the third major surface (Fig 3), on the first major surface (Fig 3), and on the fourth major surface (Fig 3); and a plurality of external connection terminals disposed on the fourth major surface (86 columnar electrodes and 91 mounting electrode, Fig 3), wherein the plurality of electronic components include a first electronic component (Combination of 11 13 and 12) including a first filter (12 transmission filter) coupled to a first power amplifier (11 power amplification element) and a first low-noise amplifier via a first switch (13 transmission matching element), a second electronic component (31 antenna switch) including a second filter coupled to a second low-noise amplifier (pg 6 ¶5), and a third electronic component including: a second switch (22 reception filter) coupled between the first filter and an antenna connection terminal (Fig 3) and between the second filter and the antenna connection terminal (Fig 3); and a switch controller controlling the second switch (21 low noise amplifier, pg 7 ¶7), the first electronic component is disposed one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface (Fig 3), the second electronic component is disposed in another one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface (Fig 3), and the third electronic component is disposed in another one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface (Fig 3) Regarding claim 2, Matsumoto teaches the high-frequency module according to claim 1, wherein the first electronic component (Combination of 11 13 and 12) is disposed on the first major surface (411 main surface Fig 3). Regarding claim 3, Matsumoto teaches the high-frequency module according to claim 1, wherein the second electronic component (31 antenna switch) is disposed between the second major surface (412 main surface) and the third major surface (421 main surface Fig 3). Regarding claim 4, Matsumoto teaches the high-frequency module according to claim 1, wherein the third electronic component (22 reception filter) is disposed on the fourth major surface (422 main surface Fig 3). Regarding claim 5, Matsumoto teaches the high-frequency module according to claim 1, further comprising: a first ground electrode pattern (61 pattern conductors) within the first module substrate (41 first module substate, Fig 3), wherein the first ground electrode pattern is disposed between the first electronic component and the second electronic component (Fig 3). Regarding claim 6, Matsumoto teaches the high-frequency module according to claim 1, further comprising: a second ground electrode pattern (62 pattern conductor) within the second module substrate (42 second module substrate, Fig 3), wherein the second ground electrode pattern is disposed between the second electronic component and the third electronic component (Fig 3). Regarding claim 8, Matsumoto teaches the high-frequency module according to claim 1, wherein the first low-noise amplifier and the second low-noise amplifier are a single same low-noise amplifier (pg 7 ¶9, 21 low noise amplifier). Regarding claim 11, Matsumoto teaches a high-frequency module, comprising: a module substrate (43 module substrate) including a first major surface (431 main surface) opposite to a second major surface (432 main surface, Fig 4 pg 31); a plurality of electronic components disposed on the first major surface (Fig 4), on the second major surface (Fig 4), and within the module substrate (Fig 4); and a plurality of external connection terminals disposed on the second major surface (86 columnar electrodes and 91 mounting electrode, Fig 4), wherein the plurality of electronic components include a first electronic component (Combination of 11 13 and 12) including a first filter (12 transmission filter) coupled to a first power amplifier (11 power amplification element) and a first low-noise amplifier via a first switch (21 low noise amplifier), a second electronic component (31 antenna switch) including a second filter coupled to a second low-noise amplifier (pg 6 ¶5), and a third electronic component including: a second switch (22 reception filter) coupled between the first filter and an antenna connection terminal (Fig 4) and between the second filter and the antenna connection terminal (Fig 4); and a switch controller controlling the second switch (13 transmission matching element, pg 7 ¶7), the first electronic component is disposed one of on the first major surface, on the second major surface, and within the module substrate (Fig 4), the second electronic component is disposed another one of on the first major surface, on the second major surface, and within the module substrate (Fig 4), and the third electronic component is disposed other one of on the first major surface, on the second major surface, and within the module substrate (Fig 4) ,wherein the plurality of electronic components further includes a fourth electronic component that is disposed between the second major surface (412 main surface, Fig 3 pg 31) and the third major surface (421 main surface, Fig 3), on the first major surface (411 main surface), or on the fourth major surface where the third electronic component is disposed and that includes a fourth switch (13 transmission matching element) connected between the first switch and the first low-noise amplifier (Pg 8 ¶4, pg 7 ¶9, 21 low noise amplifier). Regarding claim 12, Matsumoto teaches the high-frequency module according to claim 11, wherein the first electronic component (Combination of 11 13 and 12) is disposed on the first major surface (431 main surface Fig 3). Regarding claim 13, Matsumoto teaches the high-frequency module according to claim 11, wherein the second electronic component (31 antenna switch) is disposed within the module substrate (Fig 4). Regarding claim 14, Matsumoto teaches the high-frequency module according to claim 11, wherein the third electronic component (22 reception filter) is disposed on the second major surface (432 main surface Fig 4). Regarding claim 15, Matsumoto teaches the high-frequency module according to claim 11, further comprising: a first ground electrode pattern (63 pattern conductor) within the module substrate (43 module substrate), wherein the first ground electrode pattern is disposed between the first electronic component and the second electronic component (Fig 4). Regarding claim 16, Matsumoto teaches the high-frequency module according to claim 11, further comprising: a second ground electrode pattern (62 pattern conductor) within the module substrate (43 second module substrate, Fig 4), wherein the second ground electrode pattern is disposed between the second electronic component and the third electronic component (Fig 4). Regarding claim 18, Matsumoto teaches the high-frequency module according to claim 11, wherein the first low-noise amplifier and the second low-noise amplifier are a single same low-noise amplifier (pg 9 ¶5, 21 low noise amplifier). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELISA SASSERATH whose telephone number is (703)756-5847. The examiner can normally be reached Monday - Friday 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen Parker can be reached at (303) 297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.S./Examiner, Art Unit 2841 /HUNG S. BUI/Acting Patent Examiner, 2841/2800
Read full office action

Prosecution Timeline

Sep 25, 2023
Application Filed
Feb 24, 2026
Non-Final Rejection mailed — §102, §112
May 05, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+11.4%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 41 resolved cases by this examiner. Grant probability derived from career allowance rate.

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