Prosecution Insights
Last updated: April 19, 2026
Application No. 18/473,289

HIGH-FREQUENCY MODULE

Non-Final OA §102§103
Filed
Sep 25, 2023
Examiner
SASSERATH, ELISA MARIE
Art Unit
2841
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
29 granted / 32 resolved
+22.6% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
14 currently pending
Career history
46
Total Applications
across all art units

Statute-Specific Performance

§103
59.9%
+19.9% vs TC avg
§102
27.1%
-12.9% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 32 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-9 and 11-19 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Matsumoto (WO 2020022180 A1) Regarding claim 1, Matsumoto teaches a high-frequency module, comprising: a first module substrate (41 first module substrate) including a first major surface (411 main surface) opposite to a second major surface (412 main surface, Fig 3 pg 31); a second module substrate (42 second module substrate) including a third major surface (421 main surface) opposite to a fourth major surface (422 main surface), the third major surface being disposed facing the second major surface (fig 3 pg 31); a plurality of electronic components disposed between the second major surface and the third major surface (Fig 3), on the first major surface (Fig 3), and on the fourth major surface (Fig 3); and a plurality of external connection terminals disposed on the fourth major surface (86 columnar electrodes and 91 mounting electrode, Fig 3), wherein the plurality of electronic components include a first electronic component (Combination of 11 13 and 12) including a first filter (12 transmission filter) coupled to a first power amplifier (11 power amplification element) and a first low-noise amplifier via a first switch (13 transmission matching element), a second electronic component (31 antenna switch) including a second filter coupled to a second low-noise amplifier (pg 6 ¶5), and a third electronic component including: a second switch (22 reception filter) coupled between the first filter and an antenna connection terminal (Fig 3) and between the second filter and the antenna connection terminal (Fig 3); and a switch controller controlling the second switch (21 low noise amplifier, pg 7 ¶7), the first electronic component is disposed one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface (Fig 3), the second electronic component is disposed in another one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface (Fig 3), and the third electronic component is disposed in another one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface (Fig 3). Regarding claim 2, Matsumoto teaches the high-frequency module according to claim 1, wherein the first electronic component (Combination of 11 13 and 12) is disposed on the first major surface (411 main surface Fig 3). Regarding claim 3, Matsumoto teaches the high-frequency module according to claim 1, wherein the second electronic component (31 antenna switch) is disposed between the second major surface (412 main surface) and the third major surface (421 main surface Fig 3). Regarding claim 4, Matsumoto teaches the high-frequency module according to claim 1, wherein the third electronic component (22 reception filter) is disposed on the fourth major surface (422 main surface Fig 3). Regarding claim 5, Matsumoto teaches the high-frequency module according to claim 1, further comprising: a first ground electrode pattern (61 pattern conductors) within the first module substrate (41 first module substate, Fig 3), wherein the first ground electrode pattern is disposed between the first electronic component and the second electronic component (Fig 3). Regarding claim 6, Matsumoto teaches the high-frequency module according to claim 1, further comprising: a second ground electrode pattern (62 pattern conductor) within the second module substrate (42 second module substrate, Fig 3), wherein the second ground electrode pattern is disposed between the second electronic component and the third electronic component (Fig 3). Regarding claim 7, Matsumoto teaches the high-frequency module according to claim 1, wherein the plurality of electronic components include a fourth electronic component including the first switch (13 transmission matching element) and a switch controller (31 antenna switch) controlling the first switch (pg 8 ¶4), and the fourth electronic component is disposed between the second major surface and the third major surface, on the first major surface, or on the fourth major surface where the third electronic component is disposed (Fig 3). Regarding claim 8, Matsumoto teaches the high-frequency module according to claim 1, wherein the first low-noise amplifier and the second low-noise amplifier are a single same low-noise amplifier (pg 7 ¶9, 21 low noise amplifier). Regarding claim 9, Matsumoto teaches the high-frequency module according to claim 1, wherein the plurality of electronic components include a fourth electronic component that is disposed between the second major surface (412 main surface) and the third major surface (421 main surface), on the first major surface (411 main surface), or on the fourth major surface (422 main surface) where the second electronic component is disposed and that includes a third filter (12 transmission filter) coupled to a second power amplifier (11 power amplification element) and a third low-noise amplifier via a third switch (31 antenna switch, pg 7 ¶7). Regarding claim 11, Matsumoto teaches a high-frequency module, comprising: a module substrate (43 module substrate) including a first major surface (431 main surface) opposite to a second major surface (432 main surface, Fig 4 pg 31); a plurality of electronic components disposed on the first major surface (Fig 4), on the second major surface (Fig 4), and within the module substrate (Fig 4); and a plurality of external connection terminals disposed on the second major surface (86 columnar electrodes and 91 mounting electrode, Fig 4), wherein the plurality of electronic components include a first electronic component (Combination of 11 13 and 12) including a first filter (12 transmission filter) coupled to a first power amplifier (11 power amplification element) and a first low-noise amplifier via a first switch (21 low noise amplifier), a second electronic component (31 antenna switch) including a second filter coupled to a second low-noise amplifier (pg 6 ¶5), and a third electronic component including: a second switch (22 reception filter) coupled between the first filter and an antenna connection terminal (Fig 4) and between the second filter and the antenna connection terminal (Fig 4); and a switch controller controlling the second switch (13 transmission matching element, pg 7 ¶7), the first electronic component is disposed one of on the first major surface, on the second major surface, and within the module substrate (Fig 4), the second electronic component is disposed another one of on the first major surface, on the second major surface, and within the module substrate (Fig 4), and the third electronic component is disposed other one of on the first major surface, on the second major surface, and within the module substrate (Fig 4). Regarding claim 12, Matsumoto teaches the high-frequency module according to claim 11, wherein the first electronic component (Combination of 11 13 and 12) is disposed on the first major surface (431 main surface Fig 3). Regarding claim 13, Matsumoto teaches the high-frequency module according to claim 11, wherein the second electronic component (31 antenna switch) is disposed within the module substrate (Fig 4). Regarding claim 14, Matsumoto teaches the high-frequency module according to claim 11, wherein the third electronic component (22 reception filter) is disposed on the second major surface (432 main surface Fig 4). Regarding claim 15, Matsumoto teaches the high-frequency module according to claim 11, further comprising: a first ground electrode pattern (63 pattern conductor) within the module substrate (43 module substrate), wherein the first ground electrode pattern is disposed between the first electronic component and the second electronic component (Fig 4). Regarding claim 16, Matsumoto teaches the high-frequency module according to claim 11, further comprising: a second ground electrode pattern (62 pattern conductor) within the module substrate (43 second module substrate, Fig 4), wherein the second ground electrode pattern is disposed between the second electronic component and the third electronic component (Fig 4). Regarding claim 17, Matsumoto teaches the high-frequency module according to claim 11, wherein the plurality of electronic components include a fourth electronic component including the first switch (31 antenna switch), and the fourth electronic component is disposed on the first major surface, on the second major surface, or within the module substrate where the third electronic component is disposed (Fig 4). Regarding claim 18, Matsumoto teaches the high-frequency module according to claim 11, wherein the first low-noise amplifier and the second low-noise amplifier are a single same low-noise amplifier (pg 9 ¶5, 21 low noise amplifier). Regarding claim 19, Matsumoto teaches the high-frequency module according to claim 11, wherein the plurality of electronic components include a fourth electronic component that is disposed on the first major surface (431 main surface), on the second major surface (432 main surface), or within the module substrate (43 module substrate) where the second electronic component is disposed and that includes a third filter (12 transmission filter) coupled to a second power amplifier (11 power amplification element) and a third low-noise amplifier via a third switch (31 antenna switch, pg 9 ¶5). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Shinozaki et. al (US 20210091807 A1) hereafter referred to as Shinozaki. Regarding claim 10, Matsumoto teaches the high-frequency module according to claim 9, wherein the first electronic component (11 power amplification element) is disposed on the first major surface (411 main surface), and the fourth electronic component (31 antenna switch) is disposed between the second major surface (412 main surface) and the third major surface (421 main surface). Matsumoto fails to teach the first power amplifier supports a first power class, the second power amplifier supports a second power class whose maximum output power is lower than a maximum output power of the first power class, the first electronic component is disposed on the first major surface, and the fourth electronic component is disposed between the second major surface and the third major surface. However, Shinozaki teaches the first power amplifier (11 transmission power amplifier) supports a first power class (¶37), the second power amplifier (12 transmission power amplifier) supports a second power class (¶37) whose maximum output power is lower than a maximum output power of the first power class (¶37). Matsumoto and Shinozaki are both in the industry of frequency module communication devices, therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Matsumoto to include the power amplifier structure from Shinozaki in order to allow for precise control of the power class available to the communication device. (Shinozaki ¶31) Regarding claim 20, Matsumoto teaches the high-frequency module according to claim 19, wherein the first electronic component (11 power amplification element) is disposed on the first major surface (431 main surface), and the fourth electronic component is disposed within the module substrate (43 module substrate). Matsumoto fails to teach the first power amplifier supports a first power class, the second power amplifier supports a second power class whose maximum output power is lower than a maximum output power of the first power class. However, Shinozaki teaches the first power amplifier (11 transmission power amplifier) supports a first power class (¶37), the second power amplifier (12 transmission power amplifier) supports a second power class (¶7) whose maximum output power is lower than a maximum output power of the first power class (¶37). Matsumoto and Shinozaki are both in the industry of frequency module communication devices, therefore it would have been obvious to a person having ordinary skill in the art to modify the teachings of Matsumoto to include the power amplifier structure from Shinozaki in order to allow for precise control of the power class available to the communication device. (Shinozaki ¶31). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamaguchi (WO 2021039068 A1), Mototsugu (JP 2020126921 A), and Furuya (WO 2018110397 A1) teach a high frequency module with a module substrate and a plurality of electronic components mounted on the substrate. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELISA SASSERATH whose telephone number is (703)756-5847. The examiner can normally be reached Monday - Friday 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Allen Parker can be reached at (303) 297-4722. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.S./Examiner, Art Unit 2841 /HUNG S. BUI/Acting Patent Examiner, 2841/2800
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Prosecution Timeline

Sep 25, 2023
Application Filed
Feb 20, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+11.1%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 32 resolved cases by this examiner. Grant probability derived from career allow rate.

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