Prosecution Insights
Last updated: July 17, 2026
Application No. 18/473,336

RADIO-FREQUENCY MODULE AND COMMUNICATION DEVICE

Non-Final OA §112
Filed
Sep 25, 2023
Priority
Mar 31, 2021 — JP 2021-060081 +1 more
Examiner
CRUM, JACOB R
Art Unit
2835
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
474 granted / 640 resolved
+6.1% vs TC avg
Strong +28% interview lift
Without
With
+28.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
23 currently pending
Career history
669
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
85.4%
+45.4% vs TC avg
§102
6.4%
-33.6% vs TC avg
§112
6.9%
-33.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1 recites: “the first electronic component is disposed one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface, the second electronic component is disposed another one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface, and the third electronic component is disposed other one of between the second major surface and the third major surface, on the first major surface, and on the fourth major surface”, which renders the claims indefinite because it is unclear exactly what the relationship is between the components. For the purposes of examination below, Examiner has interpreted claim 1 as reading: “the first electronic component is disposed at one of: between the second major surface and the third major surface, on the first major surface, or on the fourth major surface, the second electronic component is disposed at another one of: between the second major surface and the third major surface, on the first major surface, or on the fourth major surface, and the third electronic component is disposed at a remaining one of: between the second major surface and the third major surface, on the first major surface, or on the fourth major surface”. Claim 8 recites: “the first electronic component is disposed one of on the first major surface, on the second major surface, and within the module substrate, the second electronic component is disposed another one of on the first major surface, on the second major surface, and within the module substrate, and the third electronic component is disposed other one of on the first major surface, on the second major surface, and within the module substrate”, which renders the claims indefinite because it is unclear exactly what the relationship is between the components. For the purposes of examination below, Examiner has interpreted claim 8 as reading: “the first electronic component is disposed at one of: on the first major surface, on the second major surface, or within the module substrate, the second electronic component is disposed at another one of: on the first major surface, on the second major surface, or within the module substrate, and the third electronic component is disposed at a remaining one of: on the first major surface, on the second major surface, or within the module substrate”. Allowable Subject Matter Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: As to claims 1-20, the allowability resides in the overall structure and functionality of the apparatus as recited in independent claims 1 and 8, and at least in part, because they recite the following limitations: “a first switch that switches connection and disconnection between a first filter and the power amplifier, and a third electronic component including a PA controller to control the power amplifier or a switch controller to control the first switch, the first electronic component is disposed at one of: between the second major surface and the third major surface, on the first major surface, or on the fourth major surface, the second electronic component is disposed at another one of: between the second major surface and the third major surface, on the first major surface, or on the fourth major surface, and the third electronic component is disposed at a remaining one of: between the second major surface and the third major surface, on the first major surface, or on the fourth major surface” - claim 1; “a first switch that switches connection and disconnection between a first filter and the power amplifier, and a third electronic component including a PA controller to control the power amplifier or a switch controller to control the first switch, the first electronic component is disposed at one of: on the first major surface, on the second major surface, or within the module substrate, the second electronic component is disposed at another one of: on the first major surface, on the second major surface, or within the module substrate, and the third electronic component is disposed at a remaining one of: on the first major surface, on the second major surface, or within the module substrate” - claim 8. Matsumoto (WO 2020022180 A1; cited in IDS), Ichitsubo (US 20060290421 A1), Hoang (US 20100291736 A1), and Asami (US 20090002967 A1) disclose conventional power amplifier, radio frequency, and semiconductor modules, but do not suggest the positional limitations of the first, second, and third electronic components and the switch that switches between the filter and the power amplifier. None of the prior art, either alone or in combination, can be reasonably construed as adequately teaching the above limitations in combination with the remaining claim elements. Further, Examiner has not identified any double patenting issues. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R CRUM whose telephone number is (571)270-7665. The examiner can normally be reached on Monday - Friday 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached on (571) 272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACOB R CRUM/Primary Examiner, Art Unit 2835
Read full office action

Prosecution Timeline

Sep 25, 2023
Application Filed
Apr 28, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+28.5%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allowance rate.

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