DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-10, 12-16, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. US 2019/0393702 (hereinafter Su) in view of Wei et al. US 2014/0032953 (hereinafter Wei).
Regarding claims 1 and 8, Su discloses a method for operating a battery charger, the method comprising:
operating a battery charger under a charging mode to use an adapter (fig. 2, element 226; power adapter) power to support a system power (¶¶ 0025-0026, 0028; The system is viewed by the circuit 200 as a load of the circuit 200 such that the circuit provides VSYS to the node 230 for at least partially powering the system) at an output of the battery charger;
detecting the adapter power reaches a maximum value (¶ 0037; when IIN (input current) is greater than IinDPM for a predefined period of time (e.g., such as for 500 microsecond or longer));
detecting the system voltage is less than a battery voltage of the battery by a predefined voltage offset (¶¶ 0043, 0050, 0069 and fig. 7; When VBUS is not greater in value than VBAT); and
in response to detecting the system voltage is greater than the battery voltage by the predefined voltage offset (see fig. 3, step 315 and ¶¶ 0034-0035, 0049; When VSYS is approximately equal in value to VBUS [e.g., when VSYS is within about 10% of VBUS]), transitioning the battery charger from the discharging mode to a pass-through mode (PTM) (¶ 0021; when entering the pass-through mode from the buck-boost mode the charger controller controls the one or more of the other components to progressively over-regulate the signal provided to the load about a specified voltage level) that continues to discharge the battery (fig. 3, element 320; operating in pass-through mode of operation), wherein the PTM causes the battery charger to discharge the battery without performing switching (¶¶ 0030-0033, 0042-0045, 0056-0059 and fig. 2, 4; the circuit enters the pass-through mode and ceases performing power conversion).
Su fails to disclose the method includes in response to the adapter power reaching the maximum value, transitioning the battery charger from the charging mode to a discharging mode to decrease a battery charging current in the battery charger to support the system power, wherein a system voltage at the output of the battery charger starts to decrease in response to the decreased battery charging current; and in response to detecting the system voltage is less than the battery voltage by the predefined voltage offset, transitioning the battery charger from the discharging mode to a pass-through mode (PTM).
However, Wei further discloses the method includes in response to the adapter power reaching the maximum value (¶ 0045; when the battery 217 is present, switch 615 is closed and switch 617 is opened so that the modulator 613 regulates VSYS to a maximum level indicated by VSYS_MAX as VREF), transitioning the battery charger from the charging mode to a discharging mode to decrease a battery charging current in the battery charger to support the system power (¶¶ 0011, 0022, 0038; When the battery 217 is discharging, PMON=VADP·IADP+VBAT·IDIS which is the adapter power plus the battery discharging power. In this manner, PMON generally indicates the total power level provided via VSYS),
wherein a system voltage at the output of the battery charger starts to decrease in response to the decreased battery charging current (¶¶ 0024, 0026, 0029-0030, 0034; in NVDC operation, Vsys is dynamically adjusted downward when charging current decreases and load shifts to battery support); and
in response to detecting the system voltage is less than the battery voltage by the predefined voltage offset (¶¶ 0023-0024; When VBAT<VSYS_MIN indicating
a deeply discharged battery having a voltage level below the minimum voltage level allowed for VSYS),
transitioning the battery charger from the discharging mode to a pass-through mode (PTM) (¶¶ 0024-0028, 0031; then the controller 205 drives BFET to operate in a linear region).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Su to incorporate with the teaching of Wei by supporting system power while the battery voltage is greater than the system voltage, because it would be advantageous to enhance the basic pass-through mode implementation with NVDC power path control techniques to handle various adapter power limits without excessive heat losses.
Regarding claims 2, 9 and 16, Su discloses a method for operating a battery charger, the method comprising: wherein the battery charger comprises a first high side switching element (210), a second high side switching element (218), a first low side switching element (212) and a second low side switching element (216), and transitioning the battery charger from the charging mode to the PTM comprises turning on the first high side switching element and the second high side switching element and turning off the first low side switching element and the second low side switching element (¶ 0031; When the charger controller 202 controls the transistor 210 and the transistor 218 to tum on, with a remainder of transistors shown in the circuit 200 to be off, a critical path is formed from the power adapter 226, passing through the resistor 206, transistor 210, inductor 214, and transistor 218 to the node 230; When operating in the pass-through mode, the transistor 210 and the transistor 218 are each held on (e.g., maintained in a saturation region of operation)).
Regarding claims 3 and 10, Su in view of Wei discloses the method further comprising:
in response to the adapter power reaching the maximum value (¶ 0037; in at least some implementations a first comparator (such as a Vin dynamic power management (VinDPM) comparator) monitors a value of VBUS with respect to a
threshold VinDPM and a second comparator (such as an IIN dynamic power management (IinDPM) comparator) monitors a value of IIN with respect to another threshold IinDPM), reducing an input voltage to the battery charger until the input voltage reaches a predefined input voltage (¶ 0036; controlled to not provide power
conversion (e.g., switching) until the node 230 has discharged, causing VSYS to decrease to approximately the regulation point); and
regulating the input voltage at the predefined input voltage until a start of the PTM (¶¶ 0037, 0049, 0059).
Regarding claims 5, 12, and 19, Su in view of Wei discloses the method further comprising maintaining an input voltage to the battery charger at a voltage level greater than the system voltage (Wei, ¶ 0025; when VBAT > VSYS_MIN, then the controller 205 turns BFET on so that the battery 217 discharges to provide power to the system.).
Regarding claims 6 and 13, Su discloses wherein an input voltage to the battery charger and the system voltage are shorted (turning ON 210 and 218) under the PTM (see fig. 2-4, 7 and ¶¶ 0032-0033).
Regarding claims 7, 14 and 20, Su discloses wherein the charging mode is a narrow voltage direct charging (NVDC) mode and the discharging mode is an NVDC discharging mode (¶¶ 0015-0017, 0040, 0047).
Regarding claim 15, Su discloses an apparatus comprising:
a power delivery circuit (can be a transformer) configured to convert an input voltage (from a power source) into an adapter voltage (¶ 0023; the adapter 105 is, a physical port or terminal at which the system 100 is configured to receive power, such as from a mains power supply, a transformer, a battery);
a switch converter (buck-boost converter) configured to switch the adapter voltage into a midpoint voltage (¶ 0026; In the buck-boost mode, the charger 110 operates as a traditional buck-boost power converter, performing power conversion
along the critical path between the power adapter 105 and the load 120 to increase (e.g., boost) or decrease (e.g., buck) VBUS [a midpoint voltage] to generate VSYS);
a battery charger (including/comprising elements 210, 212, 216, 218); and
a battery (fig. 2, element 228 and ¶¶ 0028-0030);
the battery charger is configured to:
operate under a charging mode to use an adapter power provided by the midpoint voltage (Vbus) to support a system power (¶ 0026; Vsys) at an output of the battery charger (output of the switch 218; ¶¶ 0025-0026, 0028);
detect the adapter power reaches a maximum value (¶ 0037; when IIN (input current) is greater than IinDPM for a predefined period of time (e.g., such as for 500 microsecond or longer));
detect the system voltage is less than a battery voltage of the battery by a predefined voltage offset (¶¶ 0043, 0050, 0069 and fig. 7; When VBUS is not greater in value than VBAT); and
in response to detection that the system voltage is greaterthan the battery voltage by the predefined voltage offset (see fig. 3, step 315 and ¶¶ 0034-0035, 0049; When VSYS is approximately equal in value to VBUS [e.g., when VSYS is within about 10% of VBUS]), transition the battery charger from the charging mode to a pass-through mode (PTM) (¶ 0021; when entering the pass-through mode from the buck-boost mode the charger controller controls the one or more of the other components to progressively over-regulate the signal provided to the load about a specified voltage level) that continues to discharge the battery (fig. 3, element 320; operating in pass-through mode of operation), wherein the PTM causes the battery charger to discharge the battery without performing switching (¶¶ 0030-0033, 0042-0045, 0056-0059 and fig. 2, 4; the circuit enters the pass-through mode and ceases performing power conversion).
Su fails to disclose the method includes in response to the adapter power reaching the maximum value, transitioning the battery charger from the charging mode to a discharging mode to decrease a battery charging current in the battery charger to support the system power, wherein a system voltage at the output of the battery charger starts to decrease in response to the decreased battery charging current; and in response to detecting the system voltage is less than the battery voltage by the predefined voltage offset, transitioning the battery charger from the discharging mode to a pass-through mode (PTM).
However, Wei further discloses the method includes in response to the adapter power reaching the maximum value (¶ 0045; when the battery 217 is present, switch 615 is closed and switch 617 is opened so that the modulator 613 regulates VSYS to a maximum level indicated by VSYS_MAX as VREF), transitioning the battery charger from the charging mode to a discharging mode to decrease a battery charging current in the battery charger to support the system power (¶¶ 0011, 0022, 0038; When the battery 217 is discharging, PMON=VADP·IADP+VBAT·IDIS which is the adapter power plus the battery discharging power. In this manner, PMON generally indicates the total power level provided via VSYS),
wherein a system voltage at the output of the battery charger starts to decrease in response to the decreased battery charging current (¶¶ 0024, 0026, 0029-0030, 0034; in NVDC operation, Vsys is dynamically adjusted downward when charging current decreases and load shifts to battery support); and
in response to detecting the system voltage is less than the battery voltage by the predefined voltage offset (¶¶ 0023-0024; When VBAT<VSYS_MIN indicating
a deeply discharged battery having a voltage level below the minimum voltage level allowed for VSYS),
transitioning the battery charger from the discharging mode to a pass-through mode (PTM) (¶¶ 0024-0028, 0031; then the controller 205 drives BFET to operate in a linear region).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Su to incorporate with the teaching of Wei by supporting system power while the battery voltage is greater than the system voltage, because it would be advantageous to enhance the basic pass-through mode implementation with NVDC power path control techniques to handle various adapter power limits without excessive heat losses.
Allowable Subject Matter
Claims 4, 11, 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4, 11 and 17, the method further comprising: in response to the adapter power reaching the maximum value: operating a first stage of the battery charger under an input current limit loop; decreasing a midpoint voltage being provided from the first stage to a second stage of the battery charger; in response to the midpoint voltage being decreased: operating the second stage under an input voltage loop to maintain the midpoint voltage at an input voltage limit; decreasing the system voltage; and in response to the system voltage being decreased, decreasing the battery charging current.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZIXUAN ZHOU whose telephone number is (571)272-6739. The examiner can normally be reached 9:00 am to 5:00 pm.
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/ZIXUAN ZHOU/Primary Examiner, Art Unit 2859 05/30/2026
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