DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Examiner acknowledges the receipt of the Applicant’s amendment filed on 04/20/2026. Claims 8, 12, 18, and 20 have been amended. Claims 1-20 are currently pending in the present application.
Response to Arguments
Applicant’s arguments, see Applicant Arguments/Remarks, filed 04/20/2026 with respect to the rejections of claims 1-20 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Keskin eta al. (US 2024/0106395 A1 herein Keskin), and further in view of Weissman et al. (US 2018/0019759 A1 herein Weissman).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Keskin eta al. (US 2024/0106395 A1 herein Keskin), and further in view of Weissman et al. (US 2018/0019759 A1 herein Weissman).
Regarding claim 1, Keskin teaches an electronic device (read as wireless device 110, 200) (Keskin – Figure 1, Figure 2, [0047], [0054]) comprising:
a memory device (read as memory 298) (Keskin – Figure 2, [0054]) configured to store operating state information (read as operating conditions; state tracking data) (Keskin – [0063]-[0064], [0074]) of a radio frequency front end (RFFE) (read as RFFE power amplifier 450; machine learning circuity 496 can accept the state tracking data from the monitoring circuitry 495, an envelope tracking signal from the DAC 404, and any other data from system operation in order to track performance quality and responsiveness under different operating conditions) (Keskin – Figure 4C, [0075]) and a damage prevention condition of the RFFE (read as operating conditions can include control signal conditions, such as certain settings for amplification circuity 424 operations and switcher 440 operation, communication signal conditions, such as certain frequencies, amplitudes, or bit patterns in a wireless communication signal, and envelope signal conditions, such as patters, frequencies, and amplitudes in the voltage level provided to the power amplifier 450 by envelope tracking systems) (Keskin – [0076]), the RFFE providing a signal path for delivering a first transmission (TX) signal to an antenna (read as transmit RF signal is routed through a duplexer or switch 246 and transmitted via an antennas 248; actual power provided at the antenna as part of a transmission can vary widely based on operating conditions and the particular application) (Keskin – Figure 2, [0057], [0063]); and
generate a TX signal control signal in response to determining that the operating state information does not satisfy the damage prevention condition, the TX signal control signal causing the first TX signal to be blocked or a magnitude of the first TX signal to be reduced (read as machine learning circuitry 496 can track power consumption and error rates under different operating conditions; the machine learning circuitry 496 can then match the real-time operating conditions to preferred power and signal performance results to dynamically generate improvements in real-time performance of a wireless communication apparatus; processing circuitry can provide a control signal indicating conditions for setting the second amplifier 526 in an on or off state based on characteristics of the analog envelope signal) (Keskin – [0076], [0079]).
However, Keskin fails to teach a TX signal controller.
In the related art, Weissman teaches a TX signal controller (read as data processor/controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; data processor/controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Weissman into the teachings of Keskin for the purpose of providing a controller that controls the opening or closing of switches to configure or reconfigure the transceiver or other units within the transceiver.
Regarding claim 2 as applied to claim 1, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]), the TX signal control signal causing the TX signal generator to blocks the generation of the digital TX signal (read as timing alignment 359 between the envelope signal 356 and the RF input 360 prevents the envelope signal 356 from being out of alignment with the signal 310, which would result in signal clipping and errors at the RF output 398; additional state tracking data from the coupler 630 can further improve real-time performance tracking of the envelope signal, and management of the control input to prevent the amplification circuity of the envelope tracking power supply from wasting power with excess current into the power amplifier 450 or causing error rates by failing to provide an adequate voltage to the power amplifier 450) (Keskin – [0069], [0092]).
Regarding claim 3 as applied to claim 1, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]); and a TX control circuit configured to, receive the digital TX signal, and reduce a magnitude of the digital TX signal in response to the TX signal control signal (read as phase locked loop (PLL) 292 receives timing information from data processor 210 and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator 290) (Keskin – [0059]).
Regarding claim 4 as applied to claim 1, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]); a clock signal generator configured to generate a clock signal (read as clock signal may be generated by a voltage-controlled oscillator (VCO) or some other types of oscillator; clock signal may also be referred to as VCO signal, an oscillator signal, etc.) (Weissman – Figure 2, [0035], [0037]); and a digital-to-analog converter configured to convert the digital TX signal into an analog TX signal in response to the clock signal, the analog TX signal corresponding to the first TX signal (read as RFFE-Tx 216 in the data processor/controller 210 processes data to be transmitted and provides a digital data to the DAC 292; the DAC 292 converts the digital data to a baseband analog output signal and provides the converted analog output signal to the transmitter 230, which generates a transmit RF signal) (Weissman – [0038]), the TX signal control signal causing at least one of the TX signal generator, the clock signal generator or the digital-to-analog converter to become disabled or off in response to the TX signal control signal (read as switches S9 are open which is read as disabled or off; timing controller 910 controls the second stage sampling switches 922 using multiple clock lines (n) 914 to control the plurality of second stage sampling switches 922, wherein each switch controls the time interlacing of each of the plurality of SAR ADCs) (Weissman – Figure 6A, Figure 6B, Figure 9, [0047]-[0048], [0056]).
Regarding claim 5 as applied to claim 1, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]); and a processor configured to control the TX signal generator to become disabled or off in response to receiving the TX signal control signal (read as data processor/controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; data processor/controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Regarding claim 6 as applied to claim 1, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal corresponding to the first TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]); a TX control circuit configured to receive the digital TX signal (read as phase locked loop (PLL) 292 receives timing information from data processor 210 and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator 290) (Keskin – [0059]); and a processor configured to control the TX control circuit to reduce a magnitude of the digital TX signal in response to receiving the TX signal control signal (read as data processor/controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; data processor/controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Regarding claim 7 as applied to claim 1, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]); a clock signal generator configured to generate a clock signal (read as clock signal may be generated by a voltage-controlled oscillator (VCO) or some other types of oscillator; clock signal may also be referred to as VCO signal, an oscillator signal, etc.) (Weissman – Figure 2, [0035], [0037]); a digital-to-analog converter configured to convert the digital TX signal into an analog TX signal in response to the clock signal, the analog TX signal corresponding to the first TX signal (read as DAC 292 converts the digital data generated in the data processor/controller 210 to an analog output signal and provides the converted analog output signal to the transmitter 230) (Weissman – Figure 2, [0032]); and a processor configured to control at least one of the TX signal generator, the clock signal generator or the digital-to-analog converter to become disabled or off in response to receiving the TX signal control signal (read as data processor/controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; data processor/controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Regarding claim 8, Keskin teaches an electronic device (read as wireless device 110, 200) (Keskin – Figure 1, Figure 2, [0047], [0054]) comprising:
a memory device (read as memory 298) (Keskin – Figure 2, [0054]) configured to store operating state information (read as operating conditions; state tracking data) (Keskin – [0063]-[0064], [0074]) of an RFFE (read as RFFE power amplifier 450; machine learning circuity 496 can accept the state tracking data from the monitoring circuitry 495, an envelope tracking signal from the DAC 404, and any other data from system operation in order to track performance quality and responsiveness under different operating conditions) (Keskin – Figure 4C, [0075]) and a damage prevention condition of the RFFE (read as operating conditions can include control signal conditions, such as certain settings for amplification circuity 424 operations and switcher 440 operation, communication signal conditions, such as certain frequencies, amplitudes, or bit patterns in a wireless communication signal, and envelope signal conditions, such as patters, frequencies, and amplitudes in the voltage level provided to the power amplifier 450 by envelope tracking systems) (Keskin – [0076]), the RFFE providing a signal path for delivering a first transmission (TX) signal to an antenna (read as transmit RF signal is routed through a duplexer or switch 246 and transmitted via an antennas 248; actual power provided at the antenna as part of a transmission can vary widely based on operating conditions and the particular application) (Keskin – Figure 2, [0057], [0063]);
a processor (read as data processor 210) (Keskin – [0054]) configured to,
receive the operating state information and the damage prevention condition (read as operating conditions; state tracking data) (Keskin – [0063]-[0064], [0074]), and
write the operating state information and the damage prevention condition in the memory device (read as memory 298 may be configured to store data and program codes, and may generally comprise analog and/or digital processing components; can include memory for storing the state tracking data) (Keskin – [0054], [0107], [0123]); and
generate a TX signal control signal in response to determining that the operating state information does not satisfy the damage prevention condition, the TX signal control signal causing the first TX signal to be blocked or a magnitude of the first TX signal to be reduced (read as machine learning circuitry 496 can track power consumption and error rates under different operating conditions; the machine learning circuitry 496 can then match the real-time operating conditions to preferred power and signal performance results to dynamically generate improvements in real-time performance of a wireless communication apparatus; processing circuitry can provide a control signal indicating conditions for setting the second amplifier 526 in an on or off state based on characteristics of the analog envelope signal) (Keskin – [0076], [0079]).
However, Keskin fails to teach a TX signal controller.
In the related art, Weissman teaches a TX signal controller (read as controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Weissman into the teachings of Keskin for the purpose of providing a controller that controls the opening or closing of switches to configure or reconfigure the transceiver or other units within the transceiver.
Regarding claim 9 as applied to claim 8, Keskin as modified by Weissman further teaches further comprising: a TX control circuit configured to, receive a digital TX signal transmitted, and reduce a magnitude of the digital TX signal in response to the TX signal control signal (read as data processor/controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; data processor/controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]); and a digital-to-analog converter configured to convert the digital TX signal having the reduced magnitude into an analog TX signal, the analog TX signal corresponding to the first TX signal (read as RFFE-Tx 216 in the data processor/controller 210 processes data to be transmitted and provides a digital data to the DAC 292; the DAC 292 converts the digital data to a baseband analog output signal and provides the converted analog output signal to the transmitter 230, which generates a transmit RF signal) (Weissman – [0038]).
Regarding claim 10 as applied to claim 8, Keskin as modified by Weissman further teaches further comprising: a digital-to-analog converter configured to convert a digital TX signal into an analog TX signal corresponding to the first TX signal (read as RFFE-Tx 216 in the data processor/controller 210 processes data to be transmitted and provides a digital data to the DAC 292; the DAC 292 converts the digital data to a baseband analog output signal and provides the converted analog output signal to the transmitter 230, which generates a transmit RF signal) (Weissman – [0038]), the TX signal control signal causing the digital-to-analog converter to become disabled or off (read as data processor/controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; data processor/controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Regarding claim 11 as applied to claim 8, Keskin as modified by Weissman further teaches further comprising: a digital-to-analog converter configured to, receive a digital TX signal, and convert the digital TX signal into an analog TX signal (read as RFFE-Tx 216 in the data processor/controller 210 processes data to be transmitted and provides a digital data to the DAC 292; the DAC 292 converts the digital data to a baseband analog output signal and provides the converted analog output signal to the transmitter 230, which generates a transmit RF signal) (Weissman – [0038]) in response to a clock signal, the analog TX signal corresponding to the first TX signal; and a clock signal generator configured to generate the clock signal (read as clock signal may be generated by a voltage-controlled oscillator (VCO) or some other types of oscillator; clock signal may also be referred to as VCO signal, an oscillator signal, etc.) (Weissman – Figure 2, [0035], [0037]), the TX signal control signal causing at least one of the digital-to-analog converter or the clock signal generator to become disabled or off (read as switches S9 are open which is read as disabled or off; timing controller 910 controls the second stage sampling switches 922 using multiple clock lines (n) 914 to control the plurality of second stage sampling switches 922, wherein each switch controls the time interlacing of each of the plurality of SAR ADCs) (Weissman – Figure 6A, Figure 6B, Figure 9, [0047]-[0048], [0056]).
Regarding claim 12 as applied to claim 8, Keskin as modified by Weissman further teaches further comprising: an amplifier configured to, receive the first TX signal transmitted, and reduce the magnitude of the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as RF amplifier 700 can be configured as a low-power PA, mid-power PA, or high-power PA by appropriately configuring the switches S15 to S19 and can be configured to be used as an LNA or three different power levels of the PA) (Weissman – Figure 7, [0049]).
Regarding claim 13 as applied to claim 8, Keskin as modified by Weissman further teaches further comprising: a switch circuit configured to block the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as switches S9 are open which is read as disabled or off; timing controller 910 controls the second stage sampling switches 922 using multiple clock lines (n) 914 to control the plurality of second stage sampling switches 922, wherein each switch controls the time interlacing of each of the plurality of SAR ADCs) (Weissman – Figure 6A, Figure 6B, Figure 9, [0047]-[0048], [0056]).
Regarding claim 14, Keskin teaches an electronic system (read as wireless device 110, 200 communicating with a wireless communication system 120) (Keskin – Figure 1, Figure 2, [0047], [0054]) comprising:
an RFFE (read as RFFE power amplifier 450; machine learning circuity 496 can accept the state tracking data from the monitoring circuitry 495, an envelope tracking signal from the DAC 404, and any other data from system operation in order to track performance quality and responsiveness under different operating conditions) (Keskin – Figure 4C, [0075]) configured to provide a signal path for delivering a first transmission (TX) signal to an antenna (read as transmit RF signal is routed through a duplexer or switch 246 and transmitted via an antennas 248; actual power provided at the antenna as part of a transmission can vary widely based on operating conditions and the particular application) (Keskin – Figure 2, [0057], [0063]);
a memory device (read as memory 298) (Keskin – Figure 2, [0054]) configured to store operating state information (read as operating conditions; state tracking data) (Keskin – [0063]-[0064], [0074]) of the RFFE and a damage prevention condition of the RFFE (read as operating conditions can include control signal conditions, such as certain settings for amplification circuity 424 operations and switcher 440 operation, communication signal conditions, such as certain frequencies, amplitudes, or bit patterns in a wireless communication signal, and envelope signal conditions, such as patters, frequencies, and amplitudes in the voltage level provided to the power amplifier 450 by envelope tracking systems) (Keskin – [0076]); and
generate a TX signal control signal in response to determining the operating state information does not satisfy the damage prevention condition, the TX signal control signal causing the first TX signal to be blocked or a magnitude of the first TX signal to be reduced (read as machine learning circuitry 496 can track power consumption and error rates under different operating conditions; the machine learning circuitry 496 can then match the real-time operating conditions to preferred power and signal performance results to dynamically generate improvements in real-time performance of a wireless communication apparatus; processing circuitry can provide a control signal indicating conditions for setting the second amplifier 526 in an on or off state based on characteristics of the analog envelope signal) (Keskin – [0076], [0079]).
However, Keskin fails to teach a TX signal controller.
In the related art, Weissman teaches a TX signal controller (read as controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Weissman into the teachings of Keskin for the purpose of providing a controller that controls the opening or closing of switches to configure or reconfigure the transceiver or other units within the transceiver.
Regarding claim 15 as applied to claim 14, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]), the TX signal control signal causing the TX signal generator to become disabled or off (read as data processor/controller 210 may perform processing for data being received via the receiver 250 and data being transmitted via the transmitter 230 and may also control the operation of various circuits within the transceiver 220; data processor/controller 210 also includes a digital baseband receiver radio frequency front-end processor (RFFE-Rx) 214 and a digital baseband transmitter RF front-end processor (RFFE-Tx) 216; RFFE-Rx 214 processes the digital baseband signal received from the ADC 290, while the RFFE-Tx 216 processes the digital baseband signal transmitted to the DAC 292) (Weissman – [0033]-[0034]).
Regarding claim 16 as applied to claim 14, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]); and a TX control circuit configured to, receive the digital TX signal, and reduce a magnitude of the digital TX signal in response to the TX signal control signal (read as phase locked loop (PLL) 292 receives timing information from data processor 210 and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from LO signal generator 290) (Keskin – [0059]).
Regarding claim 17 as applied to claim 14, Keskin as modified by Weissman further teaches further comprising: a TX signal generator configured to generate a digital TX signal (read as TX LO signal generator 290 generates the I and Q TX LO signals used for frequency upconverstion) (Keskin – [0057], [0059]); a clock signal generator configured to generate a clock signal (read as clock signal may be generated by a voltage-controlled oscillator (VCO) or some other types of oscillator; clock signal may also be referred to as VCO signal, an oscillator signal, etc.) (Weissman – Figure 2, [0035], [0037]); and a digital-to-analog converter configured to convert the digital TX signal into an analog TX signal in response to the clock signal, the analog TX signal corresponding to the first TX signal (read as RFFE-Tx 216 in the data processor/controller 210 processes data to be transmitted and provides a digital data to the DAC 292; the DAC 292 converts the digital data to a baseband analog output signal and provides the converted analog output signal to the transmitter 230, which generates a transmit RF signal) (Weissman – [0038]), and the TX signal control signal causing at least one of the TX signal generator, the clock signal generator or the digital-to-analog converter to become disabled or off (read as switches S9 are open which is read as disabled or off; timing controller 910 controls the second stage sampling switches 922 using multiple clock lines (n) 914 to control the plurality of second stage sampling switches 922, wherein each switch controls the time interlacing of each of the plurality of SAR ADCs) (Weissman – Figure 6A, Figure 6B, Figure 9, [0047]-[0048], [0056]).
Regarding claim 18 as applied to claim 14, Keskin as modified by Weissman further teaches further comprising: an amplifier configured to reduce the magnitude of the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as RF amplifier 700 can be configured as a low-power PA, mid-power PA, or high-power PA by appropriately configuring the switches S15 to S19 and can be configured to be used as an LNA or three different power levels of the PA) (Weissman – Figure 7, [0049]).
Regarding claim 19 as applied to claim 14, Keskin as modified by Weissman further teaches further comprising: a switch circuit configured to block the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as switches S9 are open which is read as disabled or off; timing controller 910 controls the second stage sampling switches 922 using multiple clock lines (n) 914 to control the plurality of second stage sampling switches 922, wherein each switch controls the time interlacing of each of the plurality of SAR ADCs) (Weissman – Figure 6A, Figure 6B, Figure 9, [0047]-[0048], [0056]).
Regarding claim 20 as applied to claim 14, Keskin as modified by Weissman further teaches further comprising: a TX control circuit configured to block the first TX signal to be transmitted to the RFFE or to reduce the magnitude of the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as machine learning circuitry 496 can track power consumption and error rates under different operating conditions; the machine learning circuitry 496 can then match the real-time operating conditions to preferred power and signal performance results to dynamically generate improvements in real-time performance of a wireless communication apparatus; processing circuitry can provide a control signal indicating conditions for setting the second amplifier 526 in an on or off state based on characteristics of the analog envelope signal) (Keskin – [0076], [0079]), the memory device and the TX signal controller being in a modem (read as wireless modem) (Weissman – [0030]), and the TX control circuit being in a radio frequency integrated circuit (RFIC) (read as implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs))(Keskin – [0054]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to APRIL GUZMAN GONZALES whose telephone number is (571)270-1101. The examiner can normally be reached Monday - Friday 8:00 am to 4:00 pm EST. The examiner’s email address is april.guzman@uspto.gov.
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/APRIL G GONZALES/ Primary Examiner, Art Unit 2648
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