DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for domestic priority under 35 U.S.C. 119(e) is acknowledged.
Information Disclosure Statement
The information disclosure statements submitted on 09/25/2023 and 05/01/2024 have been considered by the Examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Babcock et al. (US 2018/0226367 A1 herein Babcock).
Regarding claim 1, Babcock teaches an electronic device (read as wireless communication device 650) (Babcock – Figure 39A, [0634]) comprising:
a memory device (read as memory 654, 806 can be used for storing data and/or instructions to facilitate the operation of the wireless communication device 800 and/or to provide storage of user information) (Babcock – [0638], [0649]) configured to store operating state information (read as selectively enable overload protection/signal limiter functionality based on a state of a digital control signals received) (Babcock – [0017], [0025], [0715]) of a radio frequency front end (RFFE) (read as front-end system 803) (Babcock – [0538], [0638], [0641]) and a damage prevention condition of the RFFE, the RFFE providing a signal path for delivering a first transmission (TX) signal (read as overload protection circuit detects an overload condition, the overload protection circuit provides feedback to the analog control input of the switch to increase the impedance of the switch and reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0693], [0710]) to an antenna (read as integrated antenna) (Babcock – Figure 1B, [0528], [0553]); and
a TX signal controller configured to generate a TX signal control signal in response to determining that the operating state information does not satisfy the damage prevention condition (read as overload protection circuit can include a detector and an error amplifier, in which the detector configured to generate a detection signal based on detecting the signal level) (Babcock – [0077], [0532]), the TX signal control signal causing the first TX signal to be blocked (read as DC blocking capacitors 351-353 serve to provide DC blocking to provide enhanced flexibility in controlling internal DC biasing of the front end system 345) (Babcock – [0615], [0682]) or a magnitude of the first TX signal to be reduced (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 2 as applied to claim 1, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (Babcock – [0648]), the TX signal control signal causing the TX signal generator to blocks the generation of the digital TX signal (read as DC blocking capacitors 351-353 serve to provide DC blocking to provide enhanced flexibility in controlling internal DC biasing of the front end system 345) (Babcock – [0615], [0682]).
Regarding claim 3 as applied to claim 1, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (Babcock – [0648]); and a TX control circuit configured to, receive the digital TX signal, and reduce a magnitude of the digital TX signal in response to the TX signal control signal (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 4 as applied to claim 1, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal (Babcock – [0648]); a clock signal generator configured to generate a clock signal (read as clock signal; crystal 4108 supplies clock information for the SoC 4102) (Babcock – Figure 107, [1086], [1148]); and a digital-to-analog converter (read as digital-to-analog converters (DACs) (Babcock – [0772], [0820], [1153]) configured to convert the digital TX signal into an analog TX signal in response to the clock signal, the analog TX signal corresponding to the first TX signal, the TX signal control signal causing at least one of the TX signal generator, the clock signal generator or the digital-to-analog converter to become disabled or off in response to the TX signal control signal (read as limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – [0701]).
Regarding claim 5 as applied to claim 1, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (Babcock – [0648]); and a processor configured to control the TX signal generator to become disabled or off in response to receiving the TX signal control signal (read as limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – [0701]).
Regarding claim 6 as applied to claim 1, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal corresponding to the first TX signal (Babcock – [0648]); a TX control circuit configured to receive the digital TX signal (read as control and biasing circuit 7 can receive control signals) (Babcock – [0536]); and a processor (read as processor 653) (Babcock – Figure 39A, [0634]) configured to control the TX control circuit to reduce a magnitude of the digital TX signal in response to receiving the TX signal control signal (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 7 as applied to claim 1, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal (Babcock – [0648]); a clock signal generator configured to generate a clock signal (read as clock signal; crystal 4108 supplies clock information for the SoC 4102) (Babcock – Figure 107, [1086], [1148]); a digital-to-analog converter configured to convert the digital TX signal into an analog TX signal in response to the clock signal, the analog TX signal corresponding to the first TX signal (read as digital-to-analog converters (DACs) (Babcock – [0772], [0820], [1153]); and a processor configured to control at least one of the TX signal generator, the clock signal generator or the digital-to-analog converter to become disabled or off in response to receiving the TX signal control signal (read as limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – [0701]).
Regarding claim 8, Babcock teaches an electronic device (read as wireless communication device 650) (Babcock – Figure 39A, [0634]) comprising:
a memory device (read as memory 654, 806 can be used for storing data and/or instructions to facilitate the operation of the wireless communication device 800 and/or to provide storage of user information) (Babcock – [0638], [0649]) configured to store operating state information (read as selectively enable overload protection/signal limiter functionality based on a state of a digital control signals received) (Babcock – [0017], [0025], [0715]) of an RFFE (read as front-end system 803) (Babcock – [0638], [0641]) and a damage prevention condition of the RFFE, the RFFE providing a signal path for delivering a first transmission (TX) signal (read as overload protection circuit detects an overload condition, the overload protection circuit provides feedback to the analog control input of the switch to increase the impedance of the switch and reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0693], [0710]) to an antenna (read as integrated antenna) (Babcock – Figure 1B, [0528], [0553]);
a processor (read as processor 1321, 1434) (Babcock – [0771], [0822]) configured to,
receive the operating state information and the damage prevention condition (read as overload protection circuit is included to provide feedback to the switch’s analog control input based on detecting a signal level of the LNA 6; the overload protection circuit detects whether or not the LNA 6 is overloaded and when the overload protection circuit detects an overload condition, the overload protection circuit provides feedback to the analog control input of the switch) (Babcock – [0532]), and
write the operating state information and the damage prevention condition in the memory device (read as memory 806 can be used for storing data and/or instructions to facilitate the operation of the wireless communication device 800 and/or to provide storage of user information) (Babcock – [0649]); and
a TX signal controller configured to generate a TX signal control signal in response to determining that the operating state information does not satisfy the damage prevention (read as overload protection circuit can include a detector and an error amplifier, in which the detector configured to generate a detection signal based on detecting the signal level) (Babcock – [0077], [0532]), the TX signal control signal causing the first TX signal to be blocked (read as DC blocking capacitors 351-353 serve to provide DC blocking to provide enhanced flexibility in controlling internal DC biasing of the front end system 345) (Babcock – [0615], [0682]) or a magnitude of the first TX signal to be reduced (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 9 as applied to claim 8, Babcock further teaches further comprising: a TX control circuit (read as processor 1321, 1434) (Babcock – [0771], [0822]) configured to, receive a digital TX signal transmitted, and reduce a magnitude of the digital TX signal in response to the TX signal control signal (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]); and a digital-to-analog converter (read as digital-to-analog converters (DACs) (Babcock – [0772], [0820], [1153]) configured to convert the digital TX signal having the reduced magnitude into an analog TX signal (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]), the analog TX signal corresponding to the first TX signal.
Regarding claim 10 as applied to claim 8, Babcock further teaches further comprising: a digital-to-analog converter (read as digital-to-analog converters (DACs) (Babcock – [0772], [0820], [1153]) configured to convert a digital TX signal into an analog TX signal corresponding to the first TX signal, the TX signal control signal causing the digital-to-analog converter to become disabled or off (read as limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – [0701]).
Regarding claim 11 as applied to claim 8, Babcock further teaches further comprising: a digital-to-analog converter (read as digital-to-analog converters (DACs) (Babcock – [0772], [0820], [1153]) configured to, receive a digital TX signal, and convert the digital TX signal into an analog TX signal in response to a clock signal, the analog TX signal corresponding to the first TX signal; and a clock signal generator (read as clock signal; crystal 4108 supplies clock information for the SoC 4102) (Babcock – Figure 107, [1086], [1148]) configured to generate the clock signal, the TX signal control signal causing at least one of the digital-to-analog converter or the clock signal generator to become disabled or off (read as limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – [0701]).
Regarding claim 12 as applied to claim 8, Babcock further teaches further comprising: an amplifier (read as LNA 6 can be used to amplify a received signal from the antenna) (Babcock – [0530]) configured to, receive the first TX signal transmitted, and reduce a magnitude of the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 13 as applied to claim 8, Babcock further teaches further comprising: a switch circuit configured to block the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as transceiver-side switch 3; limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – Figure 1A, [0527], [0701]).
Regarding claim 14, Babcock teaches an electronic system (read as front end system 10) (Babcock – Figure 1A, [0522]) comprising:
an RFFE (read as front end system can be implemented as a radio frequency module that is partially shielded) (Babcock – [0538]) configured to provide a signal path for delivering a first transmission (TX) signal to an antenna (read as antenna-side switch 2 can be used to connect a particular one of the transmit signal path, the receive signal path, or the bypass signal to an antenna) (Babcock – [0527]);
a memory device configured to store operating state information of the RFFE and a damage prevention condition of the RFFE (read as memory 654, 806 can be used such as storing data and/or instructions to facilitate the operation of the wireless communication device 800 and/or to provide storage of information) (Babcock – Figure 39A, [0634]); and
a TX signal controller configured to generate a TX signal control signal in response to determining the operating state information does not satisfy the damage prevention condition (read as overload protection circuit can include a detector and an error amplifier, in which the detector configured to generate a detection signal based on detecting the signal level) (Babcock – [0077], [0532]), the TX signal control signal causing the first TX signal to be blocked (read as DC blocking capacitors 351-353 serve to provide DC blocking to provide enhanced flexibility in controlling internal DC biasing of the front end system 345) (Babcock – [0615], [0682]) or a magnitude of the first TX signal to be reduced (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 15 as applied to claim 14, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (Babcock – [0648]), the TX signal control signal causing the TX signal generator to become disabled or off (read as limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – [0701]).
Regarding claim 16 as applied to claim 14, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal associated with the first TX signal (Babcock – [0648]); and a TX control circuit (read as processor 1321, 1434) (Babcock – [0771], [0822]) configured to, receive the digital TX signal, and reduce a magnitude of the digital TX signal in response to the TX signal control signal (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 17 as applied to claim 14, Babcock further teaches further comprising: a TX signal generator configured to generate a digital TX signal (Babcock – [0648]); a clock signal generator configured to generate a clock signal (read as clock signal; crystal 4108 supplies clock information for the SoC 4102) (Babcock – Figure 107, [1086], [1148]); and a digital-to-analog converter (read as digital-to-analog converters (DACs) (Babcock – [0772], [0820], [1153]) configured to convert the digital TX signal into an analog TX signal in response to the clock signal, the analog TX signal corresponding to the first TX signal, and the TX signal control signal causing at least one of the TX signal generator, the clock signal generator or the digital-to-analog converter to become disabled or off (read as limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – [0701]).
Regarding claim 18 as applied to claim 14, Babcock further teaches further comprising: an amplifier (read as LNA 6 can be used to amplify a received signal from the antenna) (Babcock – [0530]) configured to reduce a magnitude of the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as reduce the magnitude of the RF input signal received by the LNA) (Babcock – [0532], [0693], [0696]).
Regarding claim 19 as applied to claim 14, Babcock further teaches further comprising: a switch circuit configured to block the first TX signal to be transmitted to the RFFE in response to the TX signal control signal (read as transceiver-side switch 3; limiter enable circuit can be used to disconnect the overload protection circuit from the analog control input when the input switch is in an off state and/or when overload protection is disabled) (Babcock – Figure 1A, [0527], [0701]).
Regarding claim 20 as applied to claim 14, Babcock further teaches further comprising: a TX control circuit configured to block the first TX signal to be transmitted to the RFFE (read as DC blocking capacitors 351-353 serve to provide DC blocking to provide enhanced flexibility in controlling internal DC biasing of the front end system 345) (Babcock – [0615], [0682]) or to reduce a magnitude of the first TX signal to be transmitted to the RFFE in response to the TX signal control signal, the memory device and the TX signal controller being in a modem (read as modem) (Babcock – [0597], [1163]), and the TX control circuit being in a radio frequency integrated circuit (RFIC) (read as integrated circuit) (Babcock – [0524], [0540], [0548]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to APRIL GUZMAN GONZALES whose telephone number is (571)270-1101. The examiner can normally be reached Monday - Friday 8:00 am to 4:00 pm EST. The examiner’s email address is April.guzman@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley L. Kim can be reached at (571) 272-7867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/APRIL G GONZALES/Primary Examiner, Art Unit 2648