DETAILED ACTION
This Office Action is in response to the Amendments filed 08 July 2026. Claims 1-29 are pending in this application. Claims 12, 15 remains withdrawn.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 19 allowable. Claims 25, 28, previously withdrawn from consideration as a result of a restriction requirement, include all the limitations of an allowable claim. Pursuant to the procedures set forth in MPEP § 821.04(a), claims 25, 28 hereby rejoined and fully examined for patentability under 37 CFR 1.104.
However, the restriction remains in effect since Claims are still rejected, and there remain Claims withdrawn which depend on the rejected claims and do not contain all the limitations of an allowed claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,4, 6-9, 13, 17 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Park et. al (US 2020/0185400 A1) (of record).
Regarding Claim 1, Park discloses (as shown in Figs. 1, 3) A memory device ([0015] Semiconductor devices according to example embodiments of the inventive concepts may include a non-volatile memory device such as a VNAND memory or a three-dimensional flash memory.) comprising:
a gate stack structure ([0017] stacked structure 40) including a plurality of insulating layers ([0017] insulating layers 41) alternately stacked with a plurality of conductive layers ([0017] electrode layers 45) in a stacked direction; ([0017] The stacked structure 40 may include a plurality of insulating layers 41 and a plurality of electrode layers 45 which are alternately and repeatedly stacked)
a plurality of support structures ([0016] a plurality of dummy channel structures 59D) extending in the stacked direction; ([0036] The plurality of dummy channel structures 59D which penetrate through the interlayer insulating layer 46, the stacked structure 40, the support plate 38A, and the source mold layer 37 into the fourth lower insulating layer 34)
a plurality of contact holes ([0016] a plurality of contact holes 71) formed through at least one layer of the plurality of conductive layers (45) and the plurality of insulating layers (41), ([0070] Referring to FIGS. 3 and 24, a plurality of contact holes 71 which pass through the second upper insulating layer 67, the first upper insulating layer 62, and the interlayer insulating layer 46 to expose portions of the plurality of electrode layers 45 may be formed) (See Fig. 1)
the plurality of contact holes (71) extending in the stacked direction and formed having different lengths through which the plurality of conductive layers (45) are exposed at different levels; ([0070] Referring to FIGS. 3 and 24, a plurality of contact holes 71 which pass through the second upper insulating layer 67, the first upper insulating layer 62, and the interlayer insulating layer 46 to expose portions of the plurality of electrode layers 45 may be formed) (See Fig. 1)
and a plurality of contacts ([0016] a plurality of contact structures 75), each disposed in a corresponding one of the plurality of contact holes and individually connected to a corresponding one of the plurality of conductive layers (45); ([0037] Each of the plurality of contact structures 75 may be in contact (e.g., direct contact) with a selected/respective one of the plurality of electrode layers 45.)
wherein the plurality of contact holes (71) includes a first contact hole (See An. Fig. 3 below, FCH) through which a sidewall of a first support structure (See An. Fig. 3 below, FSS) closest to the first contact hole (See AN. Fig. 3, FCH) among the plurality of support structures (59D) is exposed
and a second contact hole (See AN. Fig. 3, FSH) spaced apart from a second support structure (See An. Fig. 3 below, SSS) closest to the second contact hole (See AN. Fig. 3, SCH) among the plurality of support structures (59D), the second support structure (See An. Fig. 3 below, SSS) closer to the second contact hole (See AN. Fig. 3, SCH) than to the first contact hole (See AN. Fig. 3, FCH).
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Regarding Claim 4, Park further discloses (as shown in Fig. 4) wherein each of the plurality of support structure ([0016] a plurality of dummy channel structures 59D) includes:
a first support structure layer ([0063] dummy blocking layer 54D);
and a second support structure layer ([0063] dummy charge storage layer 53D) extending along an inner wall of the first support structure layer (54D), (See Fig. 8)
the second support structure layer (53D) including a material that is different from a material of the first support structure layer (54D). ([0065] The blocking layer 54 and the dummy blocking layer 54D may include a material different from that of the charge storage layer 53 and the dummy charge storage layer 53D.)
Regarding Claim 6, Park further discloses (as shown in Fig. 4) wherein the second support structure layer (53D) is exposed through the first contact hole ([0016] a plurality of contact holes 71). ([0022] Referring to FIG. 4, a contact hole 71 may partially overlap four dummy channel holes 51D.) (See Fig. 4)
Regarding Claim 7, Park further discloses (as shown in Fig. 4) wherein each of the plurality of support structures further includes a third support structure layer ([0063] dummy channel pattern 56D) surrounded by the second support structure layer (53D). ([0023] A dummy channel pattern 56D may surround an outer side of a dummy core pattern 57D. A dummy information storage pattern 55D may surround an outer side of the dummy channel pattern 56D. The dummy information storage pattern 55D may include a dummy tunnel insulation layer 52D which surrounds the outer side of the dummy channel pattern 56D, a dummy charge storage layer 53D which surrounds an outer side of the dummy tunnel insulation layer 52D)
Regarding Claim 8, Park further discloses (as shown in Fig. 4) wherein the first to third support structure layers include different materials. ([0065] the dummy blocking layer 54D may include an insulating layer such as silicon oxide, metal oxide, or a combination thereof.) [0065] the dummy charge storage layer 53D may include an insulating layer such as silicon nitride) ([0064] The channel pattern 56 and the dummy channel pattern 56D may include a semiconductor layer such as polysilicon. The channel pattern 56 and the dummy channel pattern 56D may include P-type impurities)
Regarding Claim 9, Park further discloses (as shown in Fig. 4) wherein the third support structure (56D) layer includes a conductive material. ([0064] The channel pattern 56 and the dummy channel pattern 56D may include a semiconductor layer such as polysilicon. The channel pattern 56 and the dummy channel pattern 56D may include P-type impurities)
Regarding Claim 13, Park further discloses (as shown in Fig. 2, 3) slits ([0016] isolation trench 63T) along sidewalls of the gate stack structure (40) extending through the plurality of insulating layers (41) and the plurality of conductive layers (45), (See Fig. 2)
wherein the slits (63T) extend in a first direction and are spaced apart in a second direction that is perpendicular to the first direction. (See Fig. 3)
Regarding Claim 17, Park further discloses (as shown in Fig. 2, 3) a linear auxiliary slit ([0021] selection line isolation pattern 64) extending through the gate stack structure (40), the linear auxiliary slit extending in the first direction, (See Fig. 3)
wherein the gate stack structure (40) includes a first contact region and a second contact region at each side of the linear auxiliary slit (64). (See Fig. 3, showing contacts 75 on either side of the selection isolation pattern 64)
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Noh (US 2022/0059561 A1) (of record).
Regarding Claim 14, Park fails to disclose wherein the plurality of support structures (59D) include a first linear support structure and a second linear support structure, which are spaced apart from each other with the first contact hole (FCH) interposed therebetween.
Noh discloses (as shown in Fig. 1A) wherein the plurality of support structures ([0025] A plurality of supporters 131 and 132 that penetrate the upper structure 130 may be formed) include a first linear support structure ([0025] line-type supporters 132 (top)) and a second linear support structure ([0025] line-type supporters 132 (bottom)), which are spaced apart from each other with the first contact hole ([0027] A second contact plug 123) interposed therebetween. (See Fig. 1A, showing 2 line-type supporters 132 with the second contact plug 123 between them)
Noh teaches that bridges between the source level contact layer and the first contact plug can be prevented by the line-type supporters. ([0032] As described above, bridges between the source level contact layer 112 and the first contact plug 114 may be prevented by the line-type supporters 132.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to include the line-type supporters 132 of Noh in addition to the pillar-type supporters of Park in order to prevent bridging.
Alternately, Claim 14 can be rejected over Park as applied to claim 1 above, and further in view of Luo et. al (Us 2021/0126009 A1) (of record) and Shimomura et. al (US 20220352196 A1) (of record)
Claim(s) 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Luo et. al (Us 2021/0126009 A1) (of record) and Shimomura et. al (US 20220352196 A1) (of record)
Regarding Claim 14, Park fails to disclose wherein the plurality of support structures (59D) include a first linear support structure and a second linear support structure, which are spaced apart from each other with the first contact hole (FCH) interposed therebetween.
Luo discloses (as shown in Fig. 2A) wherein the plurality of support structures include a first linear support structure and a second linear support structure ([0049] With returned reference to FIG. 2A, the support structures 224), which are spaced apart from each other with the first contact hole ([0046] The contact structures 214) interposed therebetween. (See Fig. 2A, showing the support structures 224 on both sides of the contact structures 214)
Luo teaches that the shape of the support structures (224) are selected based on the shape of the shape and location of other components of the memory device. ([0040] As described in further detail below, the geometric configurations, horizontal positions, and horizontal spacing of the support structures 124 may be selected at least partially based on the geometric configurations, horizontal positions, and horizontal spacing of other components (e.g., the steps 112 of the staircase structure 110, the contact structures 114) of the microelectronic device structure 100.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to optimize the shape of the support structures (224) based on the configuration of other parts of the device.
Furthermore, Shimomura teaches that elongated support structures can reduce bowing. ([0232] The second-type support pillar structures (20, 20B, 20C) may also have a larger horizontal cross sectional size than the first-type support pillar structures 22 to reduce backside trench bowing or tilting) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have linear support structures in order to decrease bowing.
Regarding Claim 16, Luo further teaches (as shown in Fig. 2A) wherein the first linear support structure and the second linear support structure (224) extend in the second direction and are spaced apart from each other in the first direction. (See Fig. 2A, showing the support structures 224 extending in a direction parallel to the slots 230 and arranged in the direction of extension of the slots 230)
Allowable Subject Matter
Claim 19-29 allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 19, Shoji discloses (as shown in Figs. 6, 8, 15) A memory device ([0026] FIG. 1 is a diagram showing a configuration example of a semiconductor memory device 1) comprising:
a gate stack structure ([0051] The memory cell array MCA1 includes a stacked body S1) including a plurality of insulating layers ([0051] insulating films 34) alternatively stacked with a plurality of conductive layers ([001] electrode films 23); ([0051] The stacked body S1 is configured by alternately stacking a plurality of electrode films 23 and a plurality of insulating films 34 in a Z direction.)
a plurality of support structures ([0068] support portions HR) extending through the plurality of insulating layers (34) and the plurality of conductive layers (23); ([0071] The support portion HR is provided as a columnar body that extends the stacked body S1 in the Z direction and penetrates the stacked body S1)
a first contact conductive layer ([0080] a conductor 44) contacting a conductive layer ([0080] The conductor 44 extends in the Z direction in the stacked body S1, is provided to correspond to the word line WL3, and is connected to the word line WL3. ) among the plurality of conductive layers;
and a first contact insulating layer ([0082] insulating film 41) surrounding a sidewall of the first contact conductive layer (44); ([0080] The stacked film 40 is a spacer film that is provided up to immediately above the word line WL3 and covers the outer periphery of the conductor 44…The stacked film 40 includes the insulating films 41 to 43)
wherein the plurality of support structures (HR) include a first support structure contacting the first contact insulating layer (43). (See Fig. 8, showing support pillars HR in contact with the insulating film 41)
Shoji fails to disclose a first support structure layer extending along an inner wall of a hole penetrating the plurality of insulating layers (34) and the plurality of conductive layers (23); a second support structure layer disposed in the hole, the second support structure layer extending along an inner wall of the first support structure layer; and a third support structure layer disposed in the hole, the third support structure layer extending along an inner wall of the second support structure layer, and wherein the first contact insulating layer is in contact with the second support structure layer of the first support structure.
Park discloses (as shown in Fig. 4) wherein each of the plurality of support structure ([0016] a plurality of dummy channel structures 59D) includes:
a first support structure layer ([0063] dummy blocking layer 54D) extending along an inner wall of a hole penetrating the plurality of insulating layers (34) and the plurality of conductive layers (23); ([0036] The plurality of dummy channel structures 59D which penetrate through the interlayer insulating layer 46, the stacked structure 40, the support plate 38A, and the source mold layer 37 into the fourth lower insulating layer 34) ([0063] Each of the plurality of dummy channel structures 59D may include a dummy information storage pattern 55D … The dummy information storage pattern 55D may include … a dummy blocking layer 54D, as shown in FIG. 4.)
a second support structure layer ([0063] dummy charge storage layer 53D) disposed in the hole, the second support structure layer (53D) extending along an inner wall of the first support structure layer (54D); ([0023] a dummy blocking layer 54D which surrounds an outer side of the dummy charge storage layer 53D.)
and a third support structure layer ([0063] dummy tunnel insulation layer 52D) disposed in the hole, the third support structure layer (52D) extending along an inner wall of the second support structure layer (53D), ([0023] a dummy charge storage layer 53D which surrounds an outer side of the dummy tunnel insulation layer 52D)
However, Park fails to disclose wherein the second support structure layer (53D) includes a material having an etch selectivity with respect to a silicon oxide layer and a silicon nitride layer.
Park instead discloses that the charge storage layer 53D may include silicon nitride. ([0065] the dummy charge storage layer 53D may include an insulating layer such as silicon nitride.)
Other layers of the dummy channel pattern (56D) cannot be chosen due to limitations in the claim. Dummy blocking layer 54D must be the first support structure layer because it must fulfill “a first support structure layer extending along an inner wall of a hole penetrating the plurality of insulating layers and the plurality of conductive layers”. Only dummy blocking layer 54D extends along the inner wall of the hole. Similarly, the second support structure layer requires “the second support structure layer extending along an inner wall of the first support structure layer”. Since the first support structure must be 54D, only dummy charge storage layer 53D extends along the inner wall of the dummy blocking layer 54D.
Because the prior art does not contain this limitation, Claim 19 is allowed.
Regarding Claims 20-29, Claims 20-29 depend from Claim 19 and are allowed for the same reasons.
Claim 2-3, 5, 10-11, 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claims 2-3, 5, 10, 18; Claims 2-3, 5, 10, 18 were previously indicated as containing allowable subject matter. They still contain allowable subject matter for the same reasons.
Regarding Claim 11, Park further discloses (as shown in Figs. 1, 3) wherein each of the first contact hole (An. Fig. 3, FCH) and the second contact hole (An. Fig. 3, SCH) includes a lower region (See An. Fig. 1 below, lower region LR) and an upper region (See An. Fig. 1 below, upper region UR) extending in the stacked direction; (See An. Fig. 1)
wherein a width of the upper region (UR) is greater than a width of the lower region (LR) in each of the first contact hole (FCH) and the second contact hole (SCH); (See An. Fig. 1, showing the lower regions LR are narrower than the upper regions UR)
wherein the sidewall of at least one of the plurality of support structures (59D) is exposed through the upper region (UR) of the first contact hole (FCH); (See An. Fig. 1)
and wherein the lower region (LR) of each of the first contact hole (FCH) and the second contact hole (SCH) is disposed spaced apart from the plurality of support structures (59D). (See An Fig. 1)
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However, Park fails to disclose wherein the upper region (UR) of the second contact hole (SCH) is disposed spaced apart from the plurality of support structures (59D).
While the second contact hole (SCH) is separated from the second support structure (SSS), they are not separated from all of the plurality of support structures.
Other relevant prior art includes Iguchi (US 2024/0099001 A1) (of record). Iguchi discloses (as shown in Fig. 21) wherein the second contact hole (Fig. 20, CH7) is disposed to be spaced apart from the plurality of support structures ([0075] The support pillars HR), ([0071] The contact plugs CC and the support pillars HR may be in contact with or separated from each other) (See Fig. 20, showing the contact hole CH7 separated from the support pillars HR1, HR2).
However, Iguchi does not provide a rationale for combining this configuration with the configuration in Park. Iguchi teaches that existence of the support pillars prevent deformation ([0103] The support pillars HR are provided to prevent the stacked body Sla from being depressed or deflected at this time.). However, Iguchi does not teach a rationale for removing some of the support pillars (59D) from Park.
Since the Claim contains limitations not found in the prior art, Claim 11 contains allowable subject matter.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON JAMES GREAVING/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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