DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 11 March 2026. Claims 1-11, 13--24, 26-27, 29 are pending in this application. Claims 12, 25, 28 are withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 11, 13, 17 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Iguchi (US 2024/0099001 A1)
Regarding Claim 1, Iguchi discloses (as shown in Fig. 15-21) A memory device ([0018] FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device 100) comprising:
a gate stack structure ([0053] stacked body S1) including a plurality of insulating layers ([0053] insulators 34) and a plurality of conductive layers ([0053] conductors 23), which are alternately stacked; ([0053] A stacked body S1 is obtained by alternately stacking the plurality of insulators 34 and the plurality of conductors 23 along the z-axis direction.)
a plurality of support structures ([0075] The support pillars HR) extending in a stacked direction , the stacked direction being a direction in which the plurality of insulating layers (34) and the plurality of conductive layers (23) are stacked; ([0075] The support pillars HR extend out from the stacked body S1 along the z-axis direction)
a plurality of contact holes ([0090] Next, contact holes CH1 to CH8 ) penetrating at least one layer of the plurality of conductive layers (23) and the plurality of insulating layers (34), ([0090] As described with reference to FIG. 7, the plurality of contact plugs CC are formed at a depth corresponding to the positions of the conductors 23 with which the contact plugs CC are in contact.)
the plurality of contact holes (CH1-8), extending in the stacked direction, being formed to have different lengths to individually expose the plurality of conductive layers (23) disposed at different levels; ([0090] As described with reference to FIG. 7, the plurality of contact plugs CC are formed at a depth corresponding to the positions of the conductors 23 with which the contact plugs CC are in contact. That is, bottom surfaces of the plurality of contact plugs CC are formed in a stepped shape to be located at different heights. Accordingly, the contact plugs CC are electrically connected to the corresponding conductor 23 (word line WL))
and a plurality of contacts ([0068] contact plugs CC) disposed in the plurality of contact holes (CH1-8) to be individually connected to the plurality of conductive layers (23), ([0106] the contact holes CH are filled with the conductor to form the contact plugs CC) ([0090] That is, bottom surfaces of the plurality of contact plugs CC are formed in a stepped shape to be located at different heights. Accordingly, the contact plugs CC are electrically connected to the corresponding conductor 23 (word line WL))
wherein the plurality of contact holes (CH1-8) include a first contact hole (See Fig. 20, showing contact hole CH5) exposing a sidewall of at least one of the plurality of support structures (HR) ([0071] The contact plugs CC and the support pillars HR may be in contact with or separated from each other) (See Fig. 20, showing the contact hole CH5 in contact with the sidewalls of the support pillars HR1, HR2)
and a second contact hole (See Fig. 20, showing contact hole CH7) that is spaced apart from the plurality of support structures (HR). ([0071] The contact plugs CC and the support pillars HR may be in contact with or separated from each other) (See Fig. 20, showing the contact hole CH7 separated from the support pillars HR1, HR2)
Regarding Claim 11, Iguchi further discloses (as shown in Fig. 7, 20) wherein each of the first contact hole (See Fig. 7, CC2, Fig. 20, CH5) and the second contact hole (See Fig. 2, CH7) includes a lower region (See An. Fig. 7 lower region LR) and an upper region (See An. Fig. 7 upper region UR) extending in the stacked direction, (See An. Fig. 7, showing an upper region and lower region of different widths for the contact plugs CC)
wherein a width of the upper region (UR) is greater than a width of the lower region (LR) in each of the first contact hole (See Fig. 7, CC2, Fig. 20, CH5) and the second contact hole (Fig. 20, CH7), (See An. Fig. 7, showing the upper region is wider than the lower region)
wherein the upper region (UR) of the first contact hole (See Fig. 7, CC2, Fig. 20, CH5) exposes the sidewall of at least one of the plurality of support structures (HR), (See An. Fig. 7, showing the upper region of CC2 between the support pillars HR contact the support pillars HR )
wherein the upper region (UR) of the second contact hole (Fig. 20, CH7) is disposed to be spaced apart from the plurality of support structures (HR), ([0071] The contact plugs CC and the support pillars HR may be in contact with or separated from each other) (See Fig. 20, showing the contact hole CH7 separated from the support pillars HR1, HR2)
and wherein the lower region (LR) of each of the first contact hole (See Fig. 7, CC2, Fig. 20, CH5) and the second contact hole (Fig. 20, CH7) is disposed to be spaced apart from the plurality of support structures (HR). (See An. Fig. 7, showing that the lower region of CC2 is separated from the support pillars HR) ([0071] The contact plugs CC and the support pillars HR may be in contact with or separated from each other) (See Fig. 20, showing the contact hole CH7 separated from the support pillars HR1, HR2)
PNG
media_image1.png
690
525
media_image1.png
Greyscale
Regarding Claim 13, Iguchi further discloses (as shown in Fig. 4, 5) slits ([0062] The slit SLT) defined along both sidewalls of the gate stack structure (S1) while penetrating the plurality of insulating layers (34) and the plurality of conductive layers (23), (See Fig. 5, showing the slit SLT penetrates the insulators 34 and the conductors 23)
wherein the slits (SLT) extend in a first direction (See Fig. 5, showing the slit SLT extends in the x direction) and are spaced apart from each other in a second direction that is perpendicular to the first direction. (See Fig. 4, showing the slits SLT separated in the y direction)
Regarding Claim 17, Iguchi further discloses (as shown in Fig. 4, 5) a linear auxiliary slit penetrating the gate stack structure ([0039] The slits SHE extend along the x-axis and are arranged apart from each other along the y-axis. Each slit SHE is located between two otherwise adjacent slits SLT.), the linear auxiliary slit (SHE) extending in the first direction ([0039] The slits SHE extend along the x-axis), wherein the gate stack structure (S1) includes a first contact region and a second contact region at both sides of the linear auxiliary slit (SHE). (See fig. 4, showing the slits SHE separate the stacked body into into multiple regions) ([0040] FIG. 4 shows one block BLK, that is, a region including the string units SU0 to SU4, and the two slits SLT sandwiching the block BLK.)
Claim(s) 19, 26-27 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Shoji et. al (US 2024/0292626 A1)
Regarding Claim 19, Shoji discloses (as shown in Figs. 6, 8, 15) A memory device ([0026] FIG. 1 is a diagram showing a configuration example of a semiconductor memory device 1) comprising:
a gate stack structure ([0051] The memory cell array MCA1 includes a stacked body S1) including a plurality of insulating layers ([0051] insulating films 34) and a plurality of conductive layers ([001] electrode films 23), which are alternately stacked; ([0051] The stacked body S1 is configured by alternately stacking a plurality of electrode films 23 and a plurality of insulating films 34 in a Z direction.)
a plurality of support structures ([0068] support portions HR) penetrating the plurality of insulating layers (34) and the plurality of conductive layers (23); ([0071] The support portion HR is provided as a columnar body that extends the stacked body S1 in the Z direction and penetrates the stacked body S1)
a first contact conductive layer ([0080] a conductor 44) in contact with a conductive layer ([0080] The conductor 44 extends in the Z direction in the stacked body S1, is provided to correspond to the word line WL3, and is connected to the word line WL3. ), among the plurality of conductive layers;
and a first contact insulating layer ([0082] insulating film 41) surrounding a sidewall of the first contact conductive layer (44), ([0080] The stacked film 40 is a spacer film that is provided up to immediately above the word line WL3 and covers the outer periphery of the conductor 44…The stacked film 40 includes the insulating films 41 to 43)
wherein the plurality of support structures (HR) include a first support structure in contact with the first contact insulating layer (43). (See Fig. 8, showing support pillars HR in contact with the insulating film 41)
Regarding Claim 26, Shoji further discloses (as shown in Fig. 7) a slit ([0055] Furthermore, a plurality of slits ST are provided in the stacked body S1) partitioning the gate stack structure (S1) (See Fig. 7 showing the slits ST partitioning the stacked body S1)
while penetrating the plurality of insulating layers (34) and the plurality of conductive layers (23), ([0055] The slits ST extend in the X direction and penetrate the stacked body S1 in the stacking direction (Z direction) of the stacked body S1)
wherein the slit (ST) is formed in a line shape extending in a first direction. ([0055] The slits ST extend in the X direction) (See Fig. 7, showing the slits ST are a line in the X direction)
Regarding Claim 27, Shoji further discloses (as shown in Fig. 6, 8, 15) a second support structure facing the first support structure (See Fig. 8, showing a first (left) and second (right) support portions HR)),
wherein a first contact ([0070] word line contact CC3) including the first contact conductive layer (44) and the first contact insulating layer (41) is disposed between the first support structure (HR) and the second support structure (HR). (See Fig. 8, showing the word line contact CC3 between the left and right support portions HR)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iguchi as applied to claim 1 above, and further in view of Park et. al (US 2020/0185400 A1).
Regarding Claim 4, Iguchi fails to disclose wherein each of the plurality of support structure (HR) includes: a first support structure layer; and a second support structure layer extending along an inner wall of the first support structure layer, the second support structure layer including a material that is different from a material of the first support structure layer.
Park discloses (as shown in Fig. 4) wherein each of the plurality of support structure ([0016] a plurality of dummy channel structures 59D) includes:
a first support structure layer ([0063] dummy blocking layer 54D);
and a second support structure layer ([0063] dummy charge storage layer 53D) extending along an inner wall of the first support structure layer (54D), (See Fig. 8)
the second support structure layer (53D) including a material that is different from a material of the first support structure layer (54D). ([0065] The blocking layer 54 and the dummy blocking layer 54D may include a material different from that of the charge storage layer 53 and the dummy charge storage layer 53D.)
In Park, the dummy channel structures (59D) are made of the same materials as the cell channel structures (59). This simplifies manufacturing as the dummy channel structures can be formed in the same step as the cell channel structures, instead of requiring separate processing steps. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to make the support structures of Iguchi be dummy channel structures, like in Park, with the same structure as the cell channel structures in order to simplify manufacturing.
Regarding Claim 6, Park further discloses (as shown in Fig. 4) wherein the second support structure layer (53D) is exposed by the first contact hole ([0016] a plurality of contact holes 71). ([0022] Referring to FIG. 4, a contact hole 71 may partially overlap four dummy channel holes 51D.) (See Fig. 4)
Regarding Claim 7, Park further discloses (as shown in Fig. 4) wherein each of the plurality of support structures further includes a third support structure layer ([0063] dummy channel pattern 56D) surrounded by the second support structure layer (53D). ([0023] A dummy channel pattern 56D may surround an outer side of a dummy core pattern 57D. A dummy information storage pattern 55D may surround an outer side of the dummy channel pattern 56D. The dummy information storage pattern 55D may include a dummy tunnel insulation layer 52D which surrounds the outer side of the dummy channel pattern 56D, a dummy charge storage layer 53D which surrounds an outer side of the dummy tunnel insulation layer 52D)
Regarding Claim 8, Park further discloses (as shown in Fig. 4) wherein the first to third support structure layers include different materials. ([0065] the dummy blocking layer 54D may include an insulating layer such as silicon oxide, metal oxide, or a combination thereof.) [0065] the dummy charge storage layer 53D may include an insulating layer such as silicon nitride) ([0064] The channel pattern 56 and the dummy channel pattern 56D may include a semiconductor layer such as polysilicon. The channel pattern 56 and the dummy channel pattern 56D may include P-type impurities)
Regarding Claim 9, Park further discloses (as shown in Fig. 4) wherein the third support structure (56D) layer includes a conductive material. ([0064] The channel pattern 56 and the dummy channel pattern 56D may include a semiconductor layer such as polysilicon. The channel pattern 56 and the dummy channel pattern 56D may include P-type impurities)
Claim(s) 14-15is/are rejected under 35 U.S.C. 103 as being unpatentable over Iguchi as applied to claim 1 above, and further in view of Noh (US 2022/0059561 A1).
Regarding Claim 14, Iguchi fails to disclose wherein the plurality of support structures (HR) include a first linear support structure and a second linear support structure, which are spaced apart from each other with the first contact hole (CH5) interposed therebetween.
Noh discloses (as shown in Fig. 1A) wherein the plurality of support structures ([0025] A plurality of supporters 131 and 132 that penetrate the upper structure 130 may be formed) include a first linear support structure ([0025] line-type supporters 132 (top)) and a second linear support structure ([0025] line-type supporters 132 (bottom)), which are spaced apart from each other with the first contact hole ([0027] A second contact plug 123) interposed therebetween. (See Fig. 1A, showing 2 line-type supporters 132 with the second contact plug 123 between them)
Noh teaches that bridges between the source level contact layer and the first contact plug can be prevented by the line-type supporters. ([0032] As described above, bridges between the source level contact layer 112 and the first contact plug 114 may be prevented by the line-type supporters 132.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to include the line-type supporters 132 of Noh in addition to the pillar-type supporters of Iguchi in order to prevent bridging.
Regarding Claim 15, Noh further discloses (as shown in Fig. 1A) wherein the first linear support structure (132) and the second linear support structure (132) extend in the first direction and are spaced apart from each other in the second direction. (See Fig. 1A, showing the line-type supporters 132 extend in the left-right direction and are spaced apart in the up-down direction.)
Alternately, Claim 14 can be rejected over Iguchi as applied to claim 1 above, and further in view of Luo et. al (Us 2021/0126009 A1) and Shimomura et. al (US 20220352196 A1)
Claim(s) 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iguchi as applied to claim 1 above, and further in view of Luo et. al (Us 2021/0126009 A1) and Shimomura et. al (US 20220352196 A1)
Regarding Claim 14, Iguchi fails to disclose wherein the plurality of support structures (HR) include a first linear support structure and a second linear support structure, which are spaced apart from each other with the first contact hole (CH5) interposed therebetween.
Luo discloses (as shown in Fig. 2A) wherein the plurality of support structures include a first linear support structure and a second linear support structure ([0049] With returned reference to FIG. 2A, the support structures 224), which are spaced apart from each other with the first contact hole ([0046] The contact structures 214) interposed therebetween. (See Fig. 2A, showing the support structures 224 on both sides of the contact structures 214)
Luo teaches that the shape of the support structures (224) are selected based on the shape of the shape and location of other components of the memory device. ([0040] As described in further detail below, the geometric configurations, horizontal positions, and horizontal spacing of the support structures 124 may be selected at least partially based on the geometric configurations, horizontal positions, and horizontal spacing of other components (e.g., the steps 112 of the staircase structure 110, the contact structures 114) of the microelectronic device structure 100.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to optimize the shape of the support structures (224) based on the configuration of other parts of the device.
Furthermore, Shimomura teaches that elongated support structures can reduce bowing. ([0232] The second-type support pillar structures (20, 20B, 20C) may also have a larger horizontal cross sectional size than the first-type support pillar structures 22 to reduce backside trench bowing or tilting) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have linear support structures in order to decrease bowing.
Regarding Claim 16, Luo further teaches (as shown in Fig. 2A) wherein the first linear support structure and the second linear support structure (224) extend in the second direction and are spaced apart from each other in the first direction. (See Fig. 2A, showing the support structures 224 extending in a direction parallel to the slots 230 and arranged in the direction of extension of the slots 230)
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shoji as applied to claim 19 above, and further in view of Park et. al (US 2020/0185400 A1).
Regarding Claim 20, Shoji fails to disclose a first support structure layer extending along an inner wall of a hole penetrating the plurality of insulating layers (34) and the plurality of conductive layers (23); a second support structure layer disposed in the hole, the second support structure layer extending along an inner wall of the first support structure layer; and a third support structure layer disposed in the hole, the third support structure layer extending along an inner wall of the second support structure layer, and wherein the first contact insulating layer is in contact with the second support structure layer of the first support structure.
Park discloses (as shown in Fig. 4) wherein each of the plurality of support structure ([0016] a plurality of dummy channel structures 59D) includes:
a first support structure layer ([0063] dummy blocking layer 54D) extending along an inner wall of a hole penetrating the plurality of insulating layers (34) and the plurality of conductive layers (23); ([0036] The plurality of dummy channel structures 59D which penetrate through the interlayer insulating layer 46, the stacked structure 40, the support plate 38A, and the source mold layer 37 into the fourth lower insulating layer 34) ([0063] Each of the plurality of dummy channel structures 59D may include a dummy information storage pattern 55D … The dummy information storage pattern 55D may include … a dummy blocking layer 54D, as shown in FIG. 4.)
a second support structure layer ([0063] dummy charge storage layer 53D) disposed in the hole, the second support structure layer (53D) extending along an inner wall of the first support structure layer (54D); ([0023] a dummy blocking layer 54D which surrounds an outer side of the dummy charge storage layer 53D.)
and a third support structure layer ([0063] dummy tunnel insulation layer 52D) disposed in the hole, the third support structure layer (52D) extending along an inner wall of the second support structure layer (53D), ([0023] a dummy charge storage layer 53D which surrounds an outer side of the dummy tunnel insulation layer 52D)
and wherein the first contact insulating layer ([0018] contact spacer 73) is in contact with the second support structure layer (53D) of the first support structure (59D). (See Fig. 4, showing the contact spacer 73 in contact with the dummy charge storage layer 53D)
Claim(s) 23-24, 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shoji as applied to claim 19 above, and further in view of Luo et. al (Us 2021/0126009 A1) and Shimomura et. al (US 20220352196 A1)
Regarding Claim 23, Shoji fails to disclose wherein the plurality of support structures (HR) include a second support structure, wherein the first support structure and the second support structure are formed in line shapes extending in parallel to each other, and wherein the first contact conductive layer and the first contact insulating layer are disposed between the first support structure and the second support structure.
Luo discloses (as shown in Fig. 2A) wherein the plurality of support structures ([0049] With returned reference to FIG. 2A, the support structures 224) include a second support structure (See Fig. 2A, showing multiple support structures 224),
wherein the first support structure (224) and the second support structure (224) are formed in line shapes extending in parallel to each other, (See Fig. 2A)
and wherein the contact structures ([0046] The contact structures 214) are disposed between the first support structure (224) and the second support structure (224). (See Fig. 2A, showing the contact structures 214 between two support structures 224)
Shoji teaches that the contact structure ([0080] word line contact) comprises a first contact conductive layer (44) and a first contact insulating layer (41) ([0080] The word line contact CC3 includes the stacked film 40 including a plurality of insulating films 41 to 43 stacked on the inner wall of the contact hole CH, and a conductor 44 buried in the stacked film 40 in the contact hole CH). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the first contact conductive layer (44) and the first contact insulating layer (41) between the first support structure (224) and the second support structure (224), since Luo teaches the contact structures (214) is between the first support structure (224) and the second support structure (224).
Luo teaches that the shape of the support structures (224) are selected based on the shape of the shape and location of other components of the memory device. ([0040] As described in further detail below, the geometric configurations, horizontal positions, and horizontal spacing of the support structures 124 may be selected at least partially based on the geometric configurations, horizontal positions, and horizontal spacing of other components (e.g., the steps 112 of the staircase structure 110, the contact structures 114) of the microelectronic device structure 100.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to optimize the shape of the support structures (224) based on the configuration of other parts of the device.
Furthermore, Shimomura teaches that elongated support structures can reduce bowing. ([0232] The second-type support pillar structures (20, 20B, 20C) may also have a larger horizontal cross sectional size than the first-type support pillar structures 22 to reduce backside trench bowing or tilting) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have linear support structures in order to decrease bowing.
Regarding Claim 24, Shoji further discloses (as shown in Fig. 6, 8, 15) the first contact insulating layer (41) is in contact with the plurality of support structures (HR).
Therefore, it would have been obvious for the first contact insulating layer (41) to be in contact with the linear support structures (224) of Luo in the combination of Shoji and Luo.
Regarding Claim 29, Luo further discloses (as shown in fig. 2A) wherein each of the first support structure (224) and the second support structure (224) is formed in a line shape extending a second direction that is perpendicular to the first direction. (See Fig. 2A, showing the support structures 224 extending in a direction parallel to the slots 230 and arranged in the direction of extension of the slots 230)
Allowable Subject Matter
Claims 2-3, 5, 10, 18, 21-22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, Iguchi further discloses wherein each of the plurality of contact holes (CH1-8) is disposed between corresponding support structures (HR) that are adjacent to each other, among the plurality of support structures (HR) ([0071] Each contact plug CC is provided between adjacent support pillars HR.)
However, Iguchi fails to disclose wherein the plurality of contact holes have a larger width as the length in the stacked direction is longer.
Because the prior art does not contain this limitation, Claim 2 contains allowable subject matter.
Regarding Claim 3, Claim 3 depends from Claim 2 and contains allowable subject matter for the same reasons.
Regarding Claim 5, Park further discloses (as shown in Fig. 4) wherein the first support structure layer (54D) includes an insulating material ([0065] the dummy blocking layer 54D may include an insulating layer such as silicon oxide, metal oxide, or a combination thereof.),
However, Park fails to disclose wherein the second support structure layer (53D) includes a metal nitride layer ([0065] the dummy charge storage layer 53D may include an insulating layer such as silicon nitride)
Because the prior art does not contain this limitation, Claim 5 contains allowable subject matter.
Regarding Claim 10, Park fails to disclose wherein each of the plurality of contact holes (71) is disposed to be spaced apart from the third support structure layer (56D) with the second support structure layer (53D) interposed therebetween.
Because the prior art does not contain this limitation, Claim 10 contains allowable subject matter.
Regarding Claim 18, Iguchi fails to disclose wherein the plurality of contacts (CC) include: a first group disposed in the first contact region; and a second group disposed in the second contact region, the second group having a maximum width that is different from a maximum width of the first group.
Iguchi fails to show the linear auxiliary slits (SHE) extend into the contact region.
Other relevant Prior Art includes Sakamoto et. al (US 2020/0295033 A1). Sakamoto discloses (as shown in Fig. 7) the linear auxiliary slits ([0069] slits … SLT3) extend into the contact region, such that wherein the plurality of contacts ([0106] The contacts CC) include: a first group disposed in the first contact region (See Fig. 7, showing contacts CC in a region above slit SLT3); and a second group disposed in the second contact region (See Fig. 7, showing contacts CC in a region below slit SLT3)
Sakamoto that the Slits divide the interconnect layers ([0072] Specifically, each of slits SLT1, SLT2, and SLT3 divides a plurality of interconnect layers corresponding respectively to word lines WL0 to WL11, select gate lines SGDa, SGDb and SGDc, and select gate line SGS.). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the auxiliary linear slit extend into contact region to have a first group disposed in the first contact region; and a second group disposed in the second contact region.
However, Sakamoto still fails to disclose the second group having a maximum width that is different from a maximum width of the first group.
Because the prior art does not contain this limitation, Claim 18 contains allowable subject matter.
Regarding Claim 21, Park further discloses (as shown in Fig. 4) wherein the first support structure layer (54D) includes an insulating material, ([0065] the dummy blocking layer 54D may include an insulating layer such as silicon oxide, metal oxide, or a combination thereof.)
However, Park fails to disclose wherein the second support structure layer (53D) includes a material having an etch selectivity with respect to a silicon oxide layer and a silicon nitride layer.
Park instead discloses that the charge storage layer 53D may include silicon nitride. ([0065] the dummy charge storage layer 53D may include an insulating layer such as silicon nitride.)
Because the prior art does not contain this limitation, Claim 21 contains allowable subject matter.
Regarding Claim 22, Park further discloses (as shown in Fig. 4) wherein the first support structure layer (54D) includes an oxide layer, ([0065] the dummy blocking layer 54D may include an insulating layer such as silicon oxide, metal oxide, or a combination thereof.)
wherein the second support structure layer (53D) includes a metal nitride layer, ([0065] the dummy charge storage layer 53D may include an insulating layer such as silicon nitride.)
However, Park fails to disclose wherein the third support structure layer includes a metal layer.
Because the prior art does not contain this limitation, Claim 22 contains allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights