DETAILED ACTION
This Office Action is in response to Applicant’s Remarks filed on 07/08/2026.
Currently, claims 1-4, 6-8, and 18-30 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's arguments with respect to claim(s) 1-4, 6-8, and 18-30 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, and 18-30 are rejected under 35 U.S.C. 103 as being obvious over HANAFI et al. (US Pub. No. 2003/0211681) in view of MISTRY et al. (US Pub. No. 2001/0033000) and further in view of DORIS et al. (US Pub. No. 2006/0001095).
Regarding independent claim 1, Hanafi teaches a device (Fig. 12), comprising: a silicon-on-insulator (SOI) substrate (Fig. 12, 14 + 12 + 10, ¶ [0025]) including:
first (Fig. 12, 14, ¶ [0025]) and second (Fig. 12, 10, ¶ [0025]) silicon layers, the first silicon layer having a first surface (Fig. 12, top of 14);
a first insulating layer (Fig. 12, 12, ¶ [0025]) between the first silicon layer and the second silicon layer; and
a recess (Figs. 8 & 12, opening in 14 vertically under topmost surface of 14, see Fig. 8) in the first surface of the first silicon layer;
a second insulating layer (Fig. 12, 36, ¶ [0040]) in the recess; and
a first gate (Fig. 12, 38, ¶ [0041]) on the second insulating layer, the first gate having a first gate portion (Fig.12, portion of 38 recessed in 14) in the recess and a second gate portion (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) on the first gate portion, the second gate portion being a different dimension than the first gate portion in a first direction (Figs. 8 & 12, top and bottom portions of 38 have different maximum widths).
However, Hanafi does not explicitly teach that the recess is curved from a first side to an opposite second side (the Examiner notes that the portion of Hanafi’s recess between the left and right portions are not curved), wherein the second insulating layer is a continuous layer entirely covering the first gate portion in the recess and extending onto sidewalls of the second gate portion.
However, Mistry is a pertinent art that teaches that the recess (Figs. 18-20, 712, ¶ [0070]) is curved from a first side to an opposite second side (Mistry’s recess 712 is curved from the left side to the right side).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bottom surface of Hanafi’s recess to be curved according to the teaching of Mistry (Figs. 18-20) because Mistry teaches that a curvilinear shape is an obvious shape for a recessed channel portion (see Mistry ¶¶ [0009]-[0010], [0051], [0054], & [0074]).
However, Hanafi modified by Mistry does not explicitly teach that the second insulating layer is a continuous layer entirely covering the first gate portion in the recess and extending onto sidewalls of the second gate portion.
However, Doris is a pertinent art that teaches that the second insulating layer (Fig. 7B, 30, ¶ [0050]) is a continuous layer entirely covering the first gate portion (Fig. 7B, portion of 32 below the top surface of 16, ¶¶ [0032] & [0053]) in the recess (Fig. 7B, portion of 32 and 30 recessed into 16) and extending onto sidewalls of the second gate portion (Fig. 7B, portion of 32 above the top surface of 16).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hanafi modified by Mistry’s gate dielectric layer to extend onto sidewalls of Hanafi’s gate in order to provide increased gate insulation.
Regarding claim 2, Hanafi modified by Mistry modified by Doris teaches the device of claim 1, and Doris teaches that the second insulating layer (Fig. 7B, 30, ¶ [0050]) entirely separates (Fig. 7) the first gate (Fig. 7B, 32, ¶ [0053]) from the SOI substrate (Fig. 7B, 16, ¶ [0032]).
Regarding claim 3, Hanafi modified by Mistry modified by Doris teaches the device of claim 2, and Hanafi teaches that the first gate portion (Fig.12, portion of 38 recessed in 14) has a first dimension (D1 in annotated Hanafi Fig. 12 below) along a first direction (horizontal in Fig. 12), and the second gate portion (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) has a second dimension (D2 in annotated Hanafi Fig. 12 below) between a first edge and a second edge (left and right curved portions of the recessed portion of 38) along the first direction (see annotated figure below), the first dimension being greater than the second dimension.
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Regarding claim 4, Hanafi modified by Mistry modified by Doris teaches the device of claim 3, and Hanafi teaches that the first gate portion (Fig.12, portion of 38 recessed in 14) has a third dimension (D3 in annotated figure below) along a second direction (vertical in Fig. 12) transverse to the first direction (horizontal in Fig. 12), and the second gate portion (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) has a fourth dimension (D4 in annotated Fig. 12 below) along the second direction, the first dimension (D1 in annotated figure above) being greater than the second dimension (D2 in annotated figure above).
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Regarding claim 6, Hanafi modified by Mistry modified by Doris teaches the device of claim 1, and Hanafi teaches that the first gate portion (Fig.12, portion of 38 recessed in 14) has a first dimension (D1 in annotated Hanafi Fig. 12 below) between the first side (leftmost side of Hanafi modified by Mistry’s recess) and the second side (rightmost side of Hanafi modified by Mistry’s recess), and the second gate portion (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) has a second dimension (D2 in annotated Hanafi Fig. 12 below) between a first sidewall and a second sidewall (left and right sides of 38 above the recess), the first dimension being greater than the second dimension.
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Regarding claim 7, Hanafi modified by Mistry modified by Doris teaches the device of claim 6, and Hanafi teaches that the first gate portion (Fig.12, portion of 38 recessed in 14) extends into the substrate (Fig. 12, 14 + 12 + 10, ¶ [0025]) past the first surface (Fig. 12, top surface of 14, ¶ [0025]) of the first silicon layer.
Regarding claim 8, Hanafi modified by Mistry teaches the device of claim 7, and Hanafi teaches that the second insulating layer (Fig. 12, 36, ¶ [0040]) is between the first silicon layer (Fig. 12, 14, ¶ [0025]) and the first gate portion (Fig.12, portion of 38 recessed in 14) that extends past the first surface (Fig. 12, top surface of 14, ¶ [0025]) of the first silicon layer.
Regarding independent claim 18, Hanafi teaches a device (Fig. 13), comprising:
a substrate (Fig. 12, 14 + 12 + 10, ¶ [0025]) having a surface (Fig. 12, top of 14), the substrate including:
a first silicon layer (Fig. 12, 14, ¶ [0025]), the surface is of the first silicon layer;
a buried oxide layer (Fig. 12, 12, ¶ [0025]);
a second silicon layer (Fig. 12, 10, ¶ [0025]), the buried oxide layer is on the second silicon layer and the first silicon layer is on the buried oxide layer, the substrate is a silicon-on-insulator (SOI) substrate (¶ [0025]); and
a curved recess (Figs. 8 & 12, opening in 14 vertically under topmost surface of 14 is at least partially curved, see Fig. 8) in the surface;
a recessed gate (Fig. 12, 38, ¶ [0041]) having a curved portion (Fig.12, portion of 38 recessed in 14 is at least partially curved) in the curved recess and a central portion (Fig.12, portion of 38 vertically above topmost surface of 14/42) on the curved portion, the curved portion extending in a first direction (vertical in Fig. 12) to the central portion; and
a first oxide layer (Fig. 12, 36, ¶ [0040] teaches that 36 can be an oxide) between the recessed gate and the substrate (Fig. 12).
However, Hanafi does not explicitly teach the curved recess being curved from a first side to an opposite second side; the first oxide layer extending on the surface of the substrate and in the curved recess being a continuous layer entirely covering the curved portion in the curved recess and extending onto sidewalls of the central portion.
However, Mistry is a pertinent art that teaches that the recess (Figs. 18-20, 712, ¶ [0070]) is curved from a first side to an opposite second side (Mistry’s recess 712 is curved from the left side to the right side).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bottom surface of Hanafi’s recess to be curved according to the teaching of Mistry (Figs. 18-20) because Mistry teaches that a curvilinear shape is an obvious shape for a recessed channel portion (see Mistry ¶¶ [0009]-[0010], [0051], [0054], & [0074]).
However, Hanafi modified by Mistry does not explicitly teach that the first oxide layer extending on the surface of the substrate and in the curved recess being a continuous layer entirely covering the curved portion in the curved recess and extending onto sidewalls of the central portion.
However, Doris is a pertinent art that teaches that the first oxide layer (Fig. 7B, 30, ¶ [0050] teaches that 30 can be an oxide layer) extending on the surface of the substrate (Fig. 7B, 16, ¶ [0032]) and in the curved recess (Fig. 7B, recess in 16) being a continuous layer (Fig. 7B) entirely covering the curved portion in the curved recess (Fig. 7B, portion of 32 and 30 recessed into 16) and extending onto sidewalls of the central portion (Fig. 7B, portion of 32 above the top surface of 16).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hanafi modified by Mistry’s gate dielectric layer to extend onto sidewalls of Hanafi’s gate in order to provide increased gate insulation.
Regarding claim 19, Hanafi modified by Mistry modified by Doris teaches the device of claim 18, and Hanafi teaches that the central portion of the recessed gate (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) has a first dimension in (D1 in annotated Hanagi Fig. 12 below) the first direction (vertical in Fig. 12), the curved portion has a second dimension (D2 in annotated figure below) in the first direction, the second dimension is less than the first dimension (see annotated figure below).
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Regarding claim 20, Hanafi modified by Mistry modified by Doris teaches the device of claim 19, and Hanafi teaches that the central portion of the recessed gate (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) has a third dimension (D3 in annotated Hanafi Fig. 12 below) in a second direction (horizontal in Fig. 12) transverse the first direction, the curved portion has a fourth dimension (D4 in annotated Hanafi Fig. 12 below) in the second direction, the fourth dimension is greater than the third dimension (see annotated figure below).
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Regarding claim 21, Hanafi modified by Mistry modified by Doris teaches the device of claim 18, and Hanafi teaches that the curved portion of the recessed gate (Fig.12, portion of 38 recessed in 14 is at least partially curved) has a convex surface (Fig. 12, curved portions of 38 recessed in 14 are convex) in the substrate.
Regarding claim 22, Hanafi modified by Mistry modified by Doris teaches the device of claim 18, and Hanafi teaches that the central portion of the recessed gate (Fig.12, portion of 38 vertically above topmost surface of 14/42) is surrounded by a plurality of spacers (Fig. 12, 26, ¶ [0033]) formed on the surface of the substrate.
Regarding claim 23, Hanafi modified by Mistry modified by Doris teaches the device of claim 22, and Hanafi teaches that the spacers (Fig. 12, 26, ¶ [0033]) are entirely separated from the central portion (Fig.12, portion of 38 vertically above topmost surface of 14/42) of the recessed gate by an insulating layer (Fig. 12, 34, ¶ [0038]).
Regarding independent claim 24, Hanafi teaches a device (Fig. 12), comprising:
a substrate (Fig. 12, 14 + 12 + 10, ¶ [0025]) having a first surface (Fig. 12, top of 14) opposite a second surface (Fig. 12, 10, ¶ [0025]) along a first direction (vertical in Fig. 12);
a plurality (¶ [0034] teaches that Hanafi’s invention can include a plurality of their MOSFET devices across portions of their SOI structure ) of curved recesses (Figs. 8 & 12, opening in 14 vertically under topmost surface of 14 is at least partially curved, see Fig. 8) in the first surface;
a recessed gate (Fig. 12, 38, ¶ [0041]) in each curved recess, each recessed gate having a first, curved portion (Fig.12, portion of 38 recessed in 14 is at least partially curved) in the curved recess and a second portion (Fig.12, portion of 38 vertically above topmost surface of 14/42) on the first portion, the first portion extending along the first direction to the second portion (Fig. 12);
a first insulating layer (Fig. 12, 36, ¶ [0040]) between each recessed gate and the substrate, the first insulating layer being a continuous layer extending in the curved recesses (Fig. 12, 36 is in-between 38 and 14 and extends at least partially in Hanafi’s curved recess); and
a second insulating layer (Fig. 12, 20, ¶ [0032]) on the first surface of the substrate.
However, Hanafi does not explicitly teach the curved recesses being curved from a first side to an opposite second side; the first insulating layer being a continuous layer extending in the curved recesses entirely from the first side to the second side.
However, Mistry is a pertinent art that teaches the curved recesses (Figs. 18-20, 712, ¶ [0070]) being curved from a first side to an opposite second side (Mistry’s recess 712 is curved from the left side to the right side).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the bottom surface of Hanafi’s recess to be curved according to the teaching of Mistry (Figs. 18-20) because Mistry teaches that a curvilinear shape is an obvious shape for a recessed channel portion (see Mistry ¶¶ [0009]-[0010], [0051], [0054], & [0074]).
However, Hanafi modified by Mistry does not explicitly teach the first insulating layer being a continuous layer extending in the curved recesses entirely from the first side to the second side and along sidewalls of each second portion.
However, Doris is a pertinent art that teaches that the first insulating layer (Fig. 7B, 30, ¶ [0050]) being a continuous layer extending in the curved recesses (Fig. 7B, portion of 32 and 30 recessed into 16) entirely from the first side to the second side (Fig. 7B, 30 extends from the left side to the right side of Doris’s recess) and along sidewalls of each second portion (Fig. 7B, portion of 32 above the top surface of 16).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hanafi modified by Mistry’s gate dielectric layer to extend onto sidewalls of Hanafi’s gate in order to provide increased gate insulation.
Regarding claim 25, Hanafi modified by Mistry modified by Doris teaches the device of claim 24, and Hanafi teaches that the substrate (Fig. 12, 14 + 12 + 10, ¶ [0025]) includes:
a first silicon layer (Fig. 12, 14, ¶ [0025]), the first surface (Fig. 12, top of 14) is of the first silicon layer;
a buried oxide layer (Fig. 12, 12, ¶ [0025]); and
a second silicon layer (Fig. 12, 10, ¶ [0025]), the buried oxide layer is on the second silicon layer and the first silicon layer is on the buried oxide layer (Fig. 12).
Regarding claim 26, Hanafi modified by Mistry modified by Doris teaches the device of claim 24, and Hanafi teaches that the substrate (Fig. 12, 14 + 12 + 10, ¶ [0025]) is a silicon-on-insulator (SOI) substrate (¶¶ [0025]-[0028]).
Regarding claim 27, Hanafi modified by Mistry modified by Doris teaches the device of claim 24, and Hanafi teaches that each (¶ [0034] teaches that Hanafi’s invention can include a plurality of their MOSFET devices across portions of their SOI structure) first portion (Fig.12, portion of 38 recessed in 14) has a first dimension (D1 in annotated Hanafi Fig. 12 below) along the first direction (vertical in Fig. 12) and each second portion (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) has a second dimension (D2 in annotated figure below) along the first direction greater than the first dimension.
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Regarding claim 28, Hanafi modified by Mistry modified by Doris teaches the device of claim 24, and Hanafi teaches that each (¶ [0034] teaches that Hanafi’s invention can include a plurality of their MOSFET devices across portions of their SOI structure) first portion (Fig.12, portion of 38 recessed in 14) has a first dimension (D1 in annotated Hanafi Fig. 12 below) along a second direction (horizontal in Fig. 12) transverse to the first direction (vertical in Fig. 12) and each second portion (Fig.12, portion of 38 vertically above topmost surface of 14/42, ¶ [0041]) has a second dimension (D2 in annotated Hanafi Fig. 12 below) along the second direction smaller than the first dimension.
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Regarding claim 29, Hanafi modified by Mistry modified by Doris teaches the device of claim 24, and Hanafi teaches that the sidewalls of each second portion (Fig.12, portion of 38 vertically above topmost surface of 14/42) are surrounded by a plurality of spacers (Fig. 12, 26, ¶ [0033]).
Regarding claim 30, Hanafi modified by Mistry modified by Doris teaches the device of claim 29, and Hanafi teaches that each (¶ [0034] teaches that Hanafi’s invention can include a plurality of their MOSFET devices across portions of their SOI structure) spacer (Fig. 12, 26, ¶ [0033]) is separated from a respective second portion (Fig.12, portion of 38 vertically above topmost surface of 14/42) by the first insulating layer (Hanafi modified by Mistry modified by Doris’s gate dielectric would extend onto the sidewalls of Hanafi’s gate and would separate Hanafi’s gate from Hanafi’s spacers in a similar manner to Doris’s device, see Doris Fig. 7) and each spacer is on the second insulating layer (Fig. 12, 20, ¶ [0032]).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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