DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18473870, filed 09/25/2023 is a Continuation of 16729256, filed 12/27/2019, now U.S. Patent # 11768661.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/25/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Claim Objections
Applicant is advised that should claims 1, 3 and 7 be found allowable, claims 11, 12 and 15 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim 20 is objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 20 line 3, “integrated circuit device” should read “the integrated circuit device” instead because integrated circuit device is already recited in claim 18 from which the claim depends.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “wherein the logic block is configurable to: generate eight partial products”.
This limitation is unclear because it merely states a function (that the logic block must somehow generate eight partial products) that is not performed by any structure recited in the claim. It is unclear whether the recited functions follow from the structure recited in the claim, i.e., the plurality of lookup tables, the adding circuitry, the circuitry, and the first adder, so it is unclear whether the function requires some other structure or is simply a result of operating the logic block in a certain manner. See paragraph [0071] which discloses that the logic block in Fig. 3 only generates six partial products. In contrast, see paragraph [0111] which discloses that the logic block in Fig. 25 generates eight partial products by including the additional circuitry 250. For purposes of examination, claim 4 is interpreted to depend on claim 2 which includes the additional circuitry.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 4 recites “wherein the logic block is configurable to: generate eight partial products”. This limitation lacks written description support because the specification fails to discloses the logic block of claim 1 comprising the plurality of lookup tables, the adding circuitry, the circuitry, and the first adder is configurable to generate eight partial products. See paragraph [0071] which discloses that the logic block in Fig. 3 comprising the plurality of lookup tables 60A-60D, the adding circuitry 80, the circuitry 82, and the first adder 90A and/or 90B only generates six partial products. In contrast, see paragraph [0111] which discloses that the logic block in Fig. 25 generates eight partial products by including the additional circuitry 250. It is not apparent that the logic block of claims 1/4 is capable of generating eight partial products without including the additional circuitry 250.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 6-7, 11-12, 15 and 18-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 3, 5, 2, 2, 2, 5, 2, 2, and 2 respectively of U.S. Patent No. US 11,768,661 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-3, 6-7, 11-12, 15 and 18-19 under examination are anticipated by claims 2, 3, 5, 2, 2, 2, 5, 2, 2, and 2 respectively of the reference patent. Every limitation in the application under examination claims is recited in the conflicting reference patent claim as shown in the Table below.
18473870
US 11,768,661 B2
1. A logic block implementable on an integrated circuit device, the logic block comprising:
1. An integrated circuit, comprising a logic block configurable to perform multiplication operations, wherein the logic block comprises:
a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs;
a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs
adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;
adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs
circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs; and
circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs
a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.
2. The integrated circuit of claim 1, further comprising a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.
11. An integrated circuit device, comprising
1. An integrated circuit, comprising
a logic block, wherein the logic block comprises:
a logic block configurable to perform multiplication operations, wherein the logic block comprises:
a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs;
a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs
adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;
adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs
circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs; and
circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs
a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.
2. The integrated circuit of claim 1, further comprising a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.
Mapping for the other claims are not being shown for purposes of brevity.
Claims 4, 8-10, 13-14 and 16-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-4 and 16 of U.S. Patent No. US 11,768,661 B2, hereinafter ‘661, in view of Walters (NPL – “Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs”). Walters is cited in the IDS submitted on 09/25/2023.
Regarding claim 4, ‘661 teaches all the limitations of claim 1 as stated above. Further, ‘661 teaches wherein the logic block is configurable to: generate eight partial products (‘661 claim 4 “wherein the logic block is configurable to generate eight partial products”).
‘661 does not explicitly teach wherein the logic block is configurable perform signed and unsigned multiplication operations.
However, on the same field of endeavor, Walters discloses a logic block is configurable to perform signed and unsigned multiplication operations (Walters section 2.4 second paragraph; section 5.1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify ‘661 using Walters and configure the logic block to perform signed and unsigned multiplication operations using the algorithm in section 2.4 of Walters in order to reduce the number of partial products and to implement a more versatile multiplier (Walters section 2.4 and Fig. 4).
Therefore, the combination of ‘661 as modified in view of Walters teaches wherein the logic block is configurable to: generate eight partial products; and perform signed and unsigned multiplication operations.
Regarding claim 8, ‘661 teaches all the limitations of claim 1 as stated above.
‘661 does not explicitly teach wherein: the first plurality of outputs comprises four partial products generated based on the plurality of inputs; and the third plurality of outputs comprises two partial products.
However, on the same field of endeavor, Walters discloses wherein: a first plurality of outputs comprises four partial products generated based on a plurality of inputs; and a third plurality of outputs comprises two partial products (Walters Figs. 1 and 8 and section 2.1 and 5.2; first plurality of outputs – O5 and O6; third plurality of outputs – Si or Xp).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify ‘661 using Walters and configure the logic block such that the first plurality of outputs comprises four partial products generated based on the plurality of inputs; and the third plurality of outputs comprises two partial products in order to implement a multiplier using a plurality of look-up tables (Walters section 5-5.2).
Therefore, the combination of ‘661 as modified in view of Walters teaches wherein: the first plurality of outputs comprises four partial products generated based on the plurality of inputs; and the third plurality of outputs comprises two partial products.
Regarding claim 9, ‘661 as modified in view of Walters teaches all the limitations of claim 8 as stated above. Further, ‘661 as modified in view of Walters teaches wherein the first portion of the third plurality of outputs comprises a first partial product of the two partial products (Walters Figs. 1 and 8 and section 2.1 and 5.2).
Regarding claim 10, ‘661 as modified in view of Walters teaches all the limitations of claim 9 as stated above. Further, ‘661 as modified in view of Walters teaches further comprising a second adder configurable to determine a second sum of a second portion of the second plurality of outputs and a second partial product of the two partial products (Walters Figs. 1 and 8 and section 2.1 and 5.2).
Regarding claim 13, ‘661 teaches all the limitations of claim 11 as stated above.
‘661 does not explicitly teach further comprising a second adder configurable to determine a second sum of the second plurality of outputs and a second portion of the third plurality of outputs.
However, on the same field of endeavor, Walters discloses a logic block comprising a second adder configurable to determine a second sum of a second plurality of outputs and a second portion of a third plurality of outputs (Walters Figs. 1 and 8 and section 2.1 and 5.2; second adder - XORCY).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify ‘661 using Walters and configure the logic block to include a second adder configurable to determine a second sum of the second plurality of outputs and a second portion of the third plurality of outputs since logic blocks normally have the same structure (Walters Figs. 1 and 8).
Therefore, the combination of ‘661 as modified in view of Walters teaches further comprising a second adder configurable to determine a second sum of the second plurality of outputs and a second portion of the third plurality of outputs.
Regarding claim 14, ‘661 as modified in view of Walters teaches all the limitations of claim 13 as stated above. Further, ‘661 as modified in view of Walters teaches further comprising additional circuitry configurable to receive the portion of the plurality of inputs and the sum and determine a third sum of the portion of the plurality of inputs and the sum (‘661 claim 3).
Regarding claim 16, claim 16 of ‘661 teaches all the limitations of claim 16 as shown in the Table below with the exception the limitations that are lined-through.
18473870
US 11,768,661 B2
11. An integrated circuit device, comprising
13. A logic block implementable on a programmable logic device,
a logic block, wherein the logic block comprises:
the logic block comprising:
a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs;
a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs,
adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;
adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;
circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs; and
circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs
15. The integrated circuit device of claim 11, wherein:
a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs; and
wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs
the logic block further comprises a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:
a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:
receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal; and
receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal
provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal.
provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal
16. The integrated circuit device of claim 15, wherein:
16. The logic block of claim 13, wherein:
the first portion of the plurality of lookup tables is configurable to receive a third bit value, a fourth bit value, and a fifth bit value of the plurality of inputs;
the first portion of the plurality of lookup tables is configurable to receive a third bit value, a fourth bit value, and a fifth bit value of the plurality of inputs;
the second portion of the plurality of lookup tables is configurable to receive the third bit value, the fourth bit value, and a sixth bit value of the plurality of inputs; and
the second portion of the plurality of lookup tables is configurable to receive the third bit value, the fourth bit value, and a sixth bit value of the plurality of inputs; and
the circuitry is configurable to receive the second bit value or the fifth bit value of the plurality of inputs.
the circuitry is configurable to receive the second bit value or the fifth bit value of the plurality of inputs.
‘661 does not explicitly teach a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.
However, on the same field of endeavor, Walters discloses a logic block comprising first adder configurable to determine a sum of a first portion of a second plurality of outputs and a first portion of a third plurality of outputs (Walters Figs. 1 and 8 and section 2.1 and 5.2; first adder - XORCY).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify ‘661 using Walters and configure the logic block to include a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs for adding partial products for implementing multiplication operations (Walters Figs. 1 and 8 and section 2.1 and 5.2).
Therefore, the combination of ‘661 as modified in view of Walters teaches a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.
Regarding claim 17, ‘661 teaches all the limitations of claim 11 as stated above.
‘661 does not explicitly teach further comprising programmable logic.
However, on the same field of endeavor, Walters discloses an integrated circuit further comprising programmable logic (Walters section 1 and 2.1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify ‘661 using Walters and configure the integrated circuit further include programmable logic for implementing combinational and sequential circuits such as a soft multiplier (Walters section 1 and 2.1).
Therefore, the combination of ‘661 as modified in view of Walters teaches further comprising programmable logic.
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of ‘661, in view of Shankar et al. (US 5436860 A), hereinafter Shankar.
Regarding claim 5, ‘661 teaches all the limitations of claim 1 as stated above.
‘661 does not explicitly teach wherein the circuitry is configurable to receive an enable/disable signal to disable the circuitry when the circuitry is not used.
However, on the same field of endeavor, Shankar discloses a circuitry configured to receive a disable signal to disable the circuitry when the circuitry is not used (Shankar Fig. 5 and col 11 lines 23-33).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify ‘661 and generalize the teaching of Shankar by disabling the circuitry when not in use in order to save power (Shankar col 11 lines 23-33).
Therefore, the combination of ‘661 as modified in view of Shankar teaches wherein the circuitry is configurable to receive an enable/disable signal to disable the circuitry when the circuitry is not used.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of ‘661, in view of Pugh et al. (US 20210042087 A1), hereinafter Pugh.
Regarding claim 20, ‘661 teaches all the limitations of claim 18 as stated above.
‘661 does not explicitly teach wherein when the instructions are executed by a second integrated circuit device, the logic block of integrated circuit device is configured to perform the multiplication operations.
However, on the same field of endeavor, Pugh discloses a machine-readable storage medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) (Pugh claim 13; second integrated circuit device - one or more processors; logic block – FPGA logic blocks).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify ‘661 and generalize the teaching of Pugh by having a second integrated circuit device such as one or more processors execute the instructions to control configuration of the logic block of the integrated circuit device to perform the multiplication operations because computer instructions are normally executed a processor (Pugh paragraph [0110]; claim 13).
Therefore, the combination of ‘661 as modified in view of Pugh teaches wherein when the instructions are executed by a second integrated circuit device, the logic block of integrated circuit device is configured to perform the multiplication operations.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-11, 13 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Walters.
Regarding claim 11, Walters teaches integrated circuit device, comprising
a logic block, wherein the logic block comprises (Walters Fig. 1 and section 2.1 logic block – FPGA or configurable logic block (CLB)):
a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs (Walters Fig. 1 and section 2.1 plurality of lookup tables - plurality of LUT5s or LUT6s; plurality of inputs- inputs D6:D1, A6:A1; first plurality of outputs - output of each LUT5 or LUT6);
adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs (Walters Fig. 1 and section 2.1 adding circuity- MUXCY forming a carry chain; second plurality of outputs- Ci+1 to Ci+4);
circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs (Walters Fig. 1 and section 2.1 circuitry – multiplexer outputting 06; a portion of the plurality of inputs - D6 or A6; one or more partial products - 06 output; a third plurality of outputs - propi-propi+3); and
a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs (Walters Fig. 1 and section 2.1 first adder - one of the XORCY such as the leftmost XORCY; sum - Si+3; a first portion of the second plurality of outputs - Ci+3; a first portion of the third plurality of outputs - propi+3).
Regarding claim 13, Walters teaches all the limitations of claim 11 as stated above. Further, Walter teaches further comprising a second adder configurable to determine a second sum of the second plurality of outputs and a second portion of the third plurality of outputs (Walters Fig. 1 and section 2.1 second adder - XORCY right of the leftmost XORCY; second sum - Si+2; a second portion of the third plurality of outputs - propi+2).
Regarding claim 17, Walters teaches all the limitations of claim 11 as stated above. Further, Walter teaches further comprising programmable logic (Walters section 1 and 2.1; programmable logic - configurable logic).
Regarding claim 1, it is directed to the logic block of claim 11. All components of the logic block of claim 1 are included in the logic block of claim 11. Claim 11 analysis applies equally to claim 1.
Regarding claim 8, Walters teaches all the limitations of claim 1 as stated above. Further, Walter teaches wherein: the first plurality of outputs comprises four partial products generated based on the plurality of inputs; and the third plurality of outputs comprises two partial products (Walter Figs. 1 and 8 and section 2.1 and 5.2; four partial products – O5 and/O6; partial products – at least two of the propi-propi+3).
Regarding claim 9, Walters teaches all the limitations of claim 8 as stated above. Further, Walter teaches wherein the first portion of the third plurality of outputs comprises a first partial product of the two partial products (Walter Figs. 1 and 8 and section 2.1 and 5.2; first partial product - propi+3).
Regarding claim 10, Walters teaches all the limitations of claim 9 as stated above. Further, Walter teaches further comprising a second adder configurable to determine a second sum of a second portion of the second plurality of outputs and a second partial product of the two partial products (Walters Fig. 1 and section 2.1 second adder - XORCY right of the leftmost XORCY; second sum - Si+2; second portion of the second plurality of outputs – ci+2; a second portion of the third plurality of outputs - propi+2).
Regarding claim 18, it is directed to a non-transitory computer-readable medium comprising instructions that, when executed cause the logic block of claim 11 to be configured to perform multiplication operations. All components of the logic block of claim 18 are included in the logic block of claim 11. Claim 11 analysis applies equally to claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Walters as applied to claim 1 above, and further in view of Shankar. Shankar is cited in the IDS submitted on 09/25/2023.
Regarding claim 5, Walters teaches all the limitations of claim 1 as stated above.
Walters does not explicitly teach wherein the circuitry is configurable to receive an enable/disable signal to disable the circuitry when the circuitry is not used.
However, on the same field of endeavor, Shankar discloses a circuitry configured to receive a disable signal to disable the circuitry when the circuitry is not used (Shankar Fig. 5 and col 11 lines 23-33).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Walters and generalize the teaching of Shankar by disabling the circuitry when not in use in order to save power (Shankar col 11 lines 23-33).
Therefore, the combination of Walters as modified in view of Shankar teaches wherein the circuitry is configurable to receive an enable/disable signal to disable the circuitry when the circuitry is not used.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Walters as applied to claim 8 above, and further in view of Pugh.
Regarding claim 20, Walters teaches all the limitations of claim 18 as stated above.
Walters does not explicitly teach wherein when the instructions are executed by a second integrated circuit device, the logic block of integrated circuit device is configured to perform the multiplication operations.
However, on the same field of endeavor, Pugh discloses a machine-readable storage medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) (Pugh claim 13; second integrated circuit device - one or more processors; logic block – FPGA logic blocks).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Walters and generalize the teaching of Pugh by having a second integrated circuit device such as one or more processors execute the instructions to control configuration of the logic block of the integrated circuit device to perform the multiplication operations because computer instructions are normally executed a processor (Pugh paragraph [0110]; claim 13).
Therefore, the combination of Walters as modified in view of Pugh teaches wherein when the instructions are executed by a second integrated circuit device, the logic block of integrated circuit device is configured to perform the multiplication operations.
Allowable Subject Matter
Claims 2-41, 6-7, 12, 14-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the double patenting rejections are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
The reasons for the indication of allowable subject matter are the same reasons provided in the non-final office action submitted on 01/24/2023 in the parent application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Walters (US 20160246571 A1) related to a programmable logic device for performing multiplication operations. The programmable logic device is similar to the configurable logic block of the primary reference (see Fig. 1 of the primary reference and Fig. 2 US 20160246571 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
1 Note: No prior art was applied to claim 4 because claim 4 is interpreted to depend of claim 2. See 112(b) section above.
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