Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment and Request for Reconsideration filed August 11, 2026. Applicant’s amendments to claims 1, 9, 11 and 18-19 have been entered. Claims 5 and 6 are canceled.
Claims 1-4 and 7-20 are pending, with claims 11-20 currently withdrawn from consideration.
Response to Amendment
The amendments to the claims filed August 11, 2026 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the Non-Final Office Action filed May 7, 2026.
Response to Arguments
Applicant's arguments filed August 11, 2026 have been fully considered but they are not persuasive.
In response to Applicant's arguments on pages 10-11 against the Sheridan and Chang references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As explained in the previous Office Action, and again in the rejection of the claims below, the rejection does not rely on either Sheridan or Chang individually. Sheridan is relied upon to teach the general structural arrangement, and Chang is applied to show that a person having ordinary skill in the art would have known that the conductivity types of each layer may be selected according to desired device functionality. Therefore, this argument is not persuasive.
In response to Applicant's argument on page 10 that Chang does not cure the deficiency of Sheridan, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). As explained in the previous Office Action, and again in the rejection of the claims below, Chang is applied to show that a person having ordinary skill in the art would have known that the conductivity types of each layer may be selected according to desired device functionality. Therefore, this argument is not persuasive.
Applicant argues on page 11 that there is no teaching, suggestion, or motivation to combine the references. This argument is not persuasive because obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Applicant has claimed a semiconductor structure comprising, inter alia, three layers of material, each having a conductivity type that is either the same or opposite as another layer, resulting in six possible combinations. The top layer [the second semiconductor layer] has an ion implanted region having the opposite conductivity type of the top layer. Applicant’s disclosure does not provide any evidence that the selection of the conductivity type for each layer is critical or yields unexpected results. Chang teaches that doping type of each layer may be interchanged as needed (Chang, [0017]). Therefore, as explained in the previous Office Action, and again in the rejection of claims below, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan with the teachings of Chang, insofar as trying each of the less than two dozen possible conductivity types for each layer and the ion implanted region, arriving at Applicant’s claimed invention with predictable results and without undue experimentation because a person having ordinary skill would have pursued the limited finite number of known potential options with a reasonable expectation of success. The motivation for doing so would be, as recognized by Chang, to control mobility of charge carriers (Chang, [0017]), thereby improving performance of the device.
In response to applicant's arguments on pages 10-11 that the references fail to show certain features of the invention, “Sheridan does not disclose a source electrode in direct contact with the first end of the implanted gate region, as required by amended claim 1,” it is noted that the features upon which applicant relies (i.e., an implanted gate region) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Additionally, although Applicant’s specification describes an ion implanted region, Applicant’s specification does not describe an implanted gate region, nor does Applicant’s disclosure describe the claimed ion implanted region as a gate region. Furthermore, the source electrode in direct contact with the first end of the implanted gate region, is taught by Sheridan, as discussed below. Therefore, this argument is not persuasive.
In response to Applicant’s argument on page 11 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from independent claim 1, as amended, see the rejections of the claims below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 7, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sheridan et al., US 2010/0148186 A1 (hereinafter Sheridan) in view of Chang et al., US 2021/0376090 A1 (hereinafter Chang).
Regarding claim 1, as amended, Sheridan discloses: A vertically conductive semiconductor structure, comprising: a heavily doped layer (Sheridan, FIG. 2, substrate, N-type, doping concentration greater than 1E19/cm3, [0036; 0052-0055]; Applicant’s specification defines heavily doped as greater than 1E19/cm3, [0102]), a first semiconductor layer (Sheridan, FIG. 2, N-type drift layer, [0036; 0054]), and a second semiconductor layer (Sheridan, FIG. 2, channel layer, [0036; 0054]) that are arranged from bottom to top (Sheridan, see FIG. 2), wherein conductivity types of the heavily doped layer and the first semiconductor layer are same (Sheridan, FIG. 2, N-type substrate [the heavily doped layer] and N-type drift layer [the first semiconductor layer] have same conductivity type, [0036; 0054]), (Sheridan, “Group III nitride compounds (e.g., gallium nitride GaN),” [0052]); an ion implanted region in the second semiconductor layer (Sheridan, FIG. 2, P-type gate region, [0037-0041]), wherein conductivity types of the ion implanted region and the second semiconductor layer are opposite (Sheridan, FIG. 2, P-type gate region [the ion implanted region] and N-type channel layer [the second semiconductor layer] have opposite conductivity type, [0041; 0054]), (Sheridan, FIG. 2, upper surface of raised portion of P-type gate region, shown co-planar with top surface of channel) and a second end that are opposite to each other in a thickness direction (Sheridan, FIG. 2, lower boundary of channel), wherein the first end is flush with a surface of the second semiconductor layer far from the first semiconductor layer (Sheridan, FIG. 2 shows upper surface of raised portion of channel [the first end] flush with upper surface of channel layer [the second semiconductor layer] far from N-type drift layer [the first semiconductor layer]), and the second end connects the first semiconductor layer (Sheridan, see FIG. 2, “a conducting channel is formed between drain and source,” i.e., electrically connected, [0035]), and a width of the ion implanted region from bottom to top varies (Sheridan, FIG. 2 shows width of P-type gate region [the ion implanted region], indicated by Wch, varies from bottom to top, “the sidewalls can be sloped sufficiently to insure that the channel width (Wch) at the source end of the channel is smaller than Wch at the drain end of the channel,” [0037]); a source electrode in direct contact with the first end of the ion implanted region (Sheridan, FIG. 2, source terminal shown in connected to and in direct contact with upper surface of raised portion of P-type gate region [the first end of the ion implanted region]); a gate electrode at both sides of the source electrode (Sheridan, FIG. 2, gate terminals shown at both sides of source terminal), wherein the gate electrode is in direct contact with the second semiconductor laver at both sides of the ion implanted region (Sheridan, FIG. 2 shows gate terminal in direct contact with channel layer [the second semiconductor layer] at both sides of P-type gate region [the ion implanted region]); and a drain electrode in direct contact with a surface of the heavily doped laver far from the first semiconductor layer (Sheridan, FIG. 2 shows drain terminal in direct contact with lower surface of substrate [the heavily doped layer], i.e., far from the N-type drift layer [the first semiconductor layer]).
Although Sheridan teaches that the conductivity types of the P-type gate region [the ion implanted region] and the N-type channel layer [the second semiconductor layer] are opposite, as discussed above, Sheridan does not explicitly teach: conductivity types of the first semiconductor layer and the second semiconductor layer are opposite, and conductivity types of the ion implanted region and the first semiconductor layer are the same.
However, Chang, in the same field of endeavor, teaches that the conductivity type of each layer may be selected according to the desired device functionality, e.g. a p-type layer may be arranged on an n-type layer, or vice versa (Chang, [0029; 0015-0017]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan with the teachings of Chang, insofar as selecting appropriate conductivity types for each layer, arriving at Applicant’s claimed invention with predictable results and without undue experimentation because a person having ordinary skill would have pursued the limited finite number of known potential options with a reasonable expectation of success. The motivation for doing so would be, as recognized by Chang, to control mobility of charge carriers, thereby improving performance of the device.
Regarding claim 2, Sheridan in view of Chang teaches: The structure according to claim 1, wherein from bottom to top, the width of the ion implanted region periodically varies, gradually increases (Sheridan, FIG. 2 shows width of P-type gate region [the ion implanted region], indicated by Wch, gradually increases from bottom to top, “the sidewalls can be sloped sufficiently to insure that the channel width (Wch) at the source end of the channel [the top end] is smaller than Wch at the drain end of the channel [the bottom end],” [0037]), gradually decreases, first increases and then decreases, or first decreases and then increases.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Sheridan include one or more of Applicant’s claimed alternative elements, for example: from bottom to top, the width of the ion implanted region gradually increases.
Regarding claim 4, Sheridan in view of Chang teaches: The structure according to claim 1, wherein at least one of: from bottom to top, a concentration of doped ions in the ion implanted region is unchanged (Sheridan, FIG. 1A, “uniformly doped sidewalls,” [0031], i.e., a concentration of doped ions in the ion implanted region is unchanged), from bottom to top, a concentration of doped ions in the ion implanted region periodically varies, from bottom to top, a concentration of doped ions in the ion implanted region gradually increases, or from bottom to top, a concentration of doped ions in the ion implanted region gradually decreases (Sheridan, FIG. 3, “the p-type implant concentration [the concentration of doped ions in the ion implanted region] and hence the implant damage can be reduced at the gate-source junction,” [0043], i.e., from bottom to top, a concentration of doped ions in the ion implanted region gradually decreases).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Sheridan include one or more of Applicant’s claimed alternative elements, as discussed above.
Regarding claim 7, Sheridan in view of Chang teaches: The structure according to claim 1, wherein the ion implanted region (Sheridan, FIG. 2, P-type gate region) further comprises a heavily doped region far from the first semiconductor layer (Sheridan, FIG. 2 shows ion implanted P-type gate region [the heavily doped region] on opposite side of structure from N-type drift layer [the first semiconductor layer], i.e., far from the first semiconductor layer; implanted P-type gate region has doping concentration greater than 5E18/cm3, i.e., heavily doped, [0054]), wherein conductivity types of the heavily doped region and the second semiconductor layer are opposite (Sheridan, ion implanted P-type gate region [the heavily doped region] has conductivity of P-type, channel layer [the second semiconductor layer] has conductivity of N-type, i.e., opposite, [0036]).
Regarding claim 8, Sheridan in view of Chang teaches: The structure according to claim 1, further comprising a buffer layer between the heavily doped layer and the first semiconductor layer (Sheridan, FIG. 2 shows buffer layer between substrate [the heavily doped layer] and N-type drift layer [the first semiconductor layer], [0036]).
Regarding claim 10, Sheridan teaches nearly every element of claim 10 but is silent regarding: wherein the second semiconductor layer comprises a first doped layer and a second doped layer that are stacked, wherein the first doped layer is close to the first semiconductor layer, and the second doped layer is far from the first semiconductor layer, and a conductive-ion doping concentration of the first doped layer is lower than a conductive-ion doping concentration of the second doped layer.
However, Chang, in the same field of endeavor, discloses a vertical group III-V device structure and teaches that the active layer 106, analogous to the channel layer of Sheridan [the second semiconductor layer], comprises a first doped layer (Chang, FIG. 3B, second doped region 108, [0034]) and a second doped layer that are stacked (Chang, FIG. 3B, contact region 303, [0034]), wherein the first doped layer is close to the first semiconductor layer (Chang, FIG. 3B shows second doped region 108 [the first doped layer] close to the bottom of the structure, [0034]), and the second doped layer is far from the first semiconductor layer (Chang, FIG. 3B shows contact region 303 [the second doped layer] far from the bottom of the structure, [0034]), and a conductive-ion doping concentration of the first doped layer is lower than a conductive-ion doping concentration of the second doped layer (Chang, “contact region 303 [the second doped layer] may comprise the second doping type (e.g., n-type) with a higher doping concentration than the first doped region 105 and/or the second doped region 108 [the first doped layer], i.e., the conductive-ion doping concentration of the first doped layer is lower than a conductive-ion doping concentration of the second doped layer, [0034]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan with the teachings of Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Chang, to control the formation of the conductive channel between the upper contacts and the bottom electrode, thereby providing for improved device functionality.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sheridan in view of Chang and further in view of Derluyn et al., US 2008/0006845 A1 (hereinafter Derluyn).
Regarding claim 3, Sheridan in view of Chang teaches nearly every element of claim 3 but is silent regarding: a passivated layer on the surface of the second semiconductor layer far from the first semiconductor layer, wherein a material of the passivated layer is AlGaN, and a content of Al in the AlGaN increases from bottom to top in the thickness direction of the passivated layer.
However, Derluyn, in the same field of endeavor, teaches a passivated layer on the surface of the active layers, analogous to the claimed surface of the second semiconductor layer, and that the thickness and concentration of Al in an AlGaN passivation layer create or enhance a 2 DEG layer, resulting in high 2 DEG density (Derluyn, [000043-0044]). Derluyn teaches that the aluminum content can be varied from 30% over 35% to 40% (Derluyn, [0066]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan in view of Chang with the teachings of Derluyn, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Derluyn, to obtain a high 2 DEG density for very thin AlGaN layers, thereby improving device performance and reliability.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sheridan in view of Chang and further in view of Sun et al., US 2017/0236951 A1 (hereinafter Sun).
Regarding claim 9, Sheridan in view of Chang teaches: The structure according to claim 1, wherein the first semiconductor layer comprises a first surface facing away from the heavily doped layer (Sheridan, FIG. 2, upper surface of N-type drift layer, [0036; 0054]), (Sheridan, FIG. 2, upper surface of channel layer, [0036; 0054]) is provided with a plurality of second protrusions corresponding to the plurality of first protrusions in position (Sheridan, FIG. 2 shows upper surface of channel layer [the second semiconductor layer] is provided with a raised region, i.e., protrusion, [0036]), or a surface of the second semiconductor layer facing away from the first semiconductor layer is flat.
Sheridan in view of Chang is silent regarding: wherein the first surface is provided with a plurality of first protrusions, and the ion implanted region is above each of the plurality of the first protrusions.
However, Sun, in the same field of endeavor, discloses a vertical semiconductor transistor wherein the first surface is provided with a plurality of first protrusions (Sun, FIG. 10 shows protrusions on upper surface of drift region 1008, analogous to the drift layer taught by Sheridan [the first semiconductor layer], [0076]), and the ion implanted region is above each of the plurality of the first protrusions (Sun, FIG. 10 shows gate regions 1006, analogous to the P-type gate region taught by Sheridan [the ion implanted region] is above the protrusions on upper surface of drift region 1008 [the first protrusions]). Sun teaches that this structural arrangement reduces the magnitude of the electric field at the intersection of the channel 1004, gate 1006, and drift region 1008, results in higher breakdown voltage, and thereby improves reliability of the vertical transistor, [0075-0076].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan in view of Chang with the teachings of Sun, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Sun, to control and shape the electric field within the vertical transistor, resulting in a higher breakdown voltage, thereby improving device performance and reliability.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
