DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election Requirement filed 31 March 2026. Claims 1-9 are pending in this application. Claims 3, 5, 7-9 are withdrawn from consideration and Claims 1-2, 4, 6 are examined in this office action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on 05 February 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Umemoto et. al (US 2019/0386122 A1)
Regarding Claim 1, Umemoto discloses (as shown in Fig. 4-5, 14A) A semiconductor device ([0106] FIG. 14A is a plan view of an emitter layer 31, an emitter electrode 32, and an emitter wiring line 34 of a semiconductor device according to the second embodiment.) ([0105] Next, a semiconductor device according to a second embodiment will be described with reference to FIGS. 14A to 15B. Hereinafter, descriptions of configurations that are common to those of the semiconductor device according to the first embodiment (FIGS. 4, 5, and 6) will be omitted.) comprising:
a substrate ([0067] substrate 60);
a bipolar transistor ([0067] The collector layer 41, the base layer 51, and the emitter layer 31 form an HBT.) above the substrate (60), the bipolar transistor (HBT) including a collector layer ; ([0067] collector layer 41), a base layer ([0067] base layer 51 ), and an emitter layer ([0067] emitter layer 31) that are stacked in order from a substrate (60) side; ([0067] A sub-collector layer 40 is disposed on a substrate 60 made of a semi-insulating semiconductor. A collector layer 41 is disposed on a partial region of the sub-collector layer 40, and a base layer 51 is disposed on the collector layer 41… An emitter layer 31 is disposed on a partial region of the base layer 51. )
at least one emitter electrode ([0064] emitter electrode 32) above the emitter layer (31) ([0068] An emitter electrode 32 is disposed in a partial region on the upper surface of the emitter layer 31.), the emitter electrode (32) being electrically coupled to the emitter layer (31); ([0068] The interface between the emitter electrode 32 and the emitter layer 31 corresponds to an ohmic contact interface 35.)
an interlayer insulating film ([0069] An insulating film 61) on the emitter electrode (32), ([0069] An insulating film 61 is disposed so as to cover the collector electrodes 42, the base electrode main portions 52A, and the emitter electrode 32.)
and at least one emitter contact hole ([0047] contact hole 33) in the interlayer insulating film (61), ([0069] contact holes 33 formed in the insulating film 61)
the emitter contact hole (33) being surrounded by the emitter electrode (32) when viewed in plan view; (See Fig. 4, showing the contact hole 33 surrounded by the emitter electrode 32 in plan view)
and an emitter wire ([0069] emitter wiring line 34) on the interlayer insulating film (61), the emitter wire (34) being coupled to the emitter electrode (32) through the emitter contact hole (33), ([0069] The emitter wiring line 34 is connected to the emitter electrode 32 through a contact hole 33 formed in the insulating film 61.)
wherein when viewed in plan view, the emitter electrode (32) and the emitter contact hole (33) are elongated in one direction, (See Fig. 4)
and a first condition is satisfied with respect to the at least one emitter electrode (32) and the emitter contact hole (33) surrounded by the emitter electrode (32) when viewed in plan view;
such that in the first condition, a length of the emitter contact hole (33) is 85% or less of a length of the emitter electrode (32), and of two side ends of the emitter electrode (32), a distance from each side end to the emitter contact hole (33) is 5% or more of the length of the emitter electrode.
([0106] In one example, the distance a1 with respect to the longitudinal direction and the distance a2 with respect to the width direction are each about 0.5 μm or less, and the distance b1 with respect to the longitudinal direction is 4 μm or more… [0110] Each of the emitter layers 31 has a length of 40 μm and a width of 3 μm)
Therefore, as shown in Fig. 14A, the emitter electrode (32) has a length of the emitter layer (31) minus 2*a1. This means the emitter electrode (32) has a length of at least 39 µm (40 µm – 2*(<0.5 µm)). The emitter contact hole (33) has a length of the emitter layer (31) minus 2*b1. This means the emitter contact hole (32) has a length of at most 32 µm (40 µm – 2*(>4 µm)). Therefore, the emitter contact hole (33) is at most ~82% (32 µm/39 µm).
Furthermore, the emitter electrode (32) extends beyond the contact hole (33) in the extension direction by the length b1 (from the end of the contact hole 33 to the end of the emitter layer 31) minus the length a1 (from the end of the contact hole 33 to the end of the emitter layer 31). This means the distance between the end of the emitter electrode (32) and the contact hole (31) is b1 (>4 µm) – a1 (<0.5µm). Therefore, the distance between the end of the emitter electrode (32) and the contact hole (31) is at least 3.5 µm. This means the distance form the ends of the emitter contact hole (33) is at least ~9% (3.5 µm/ 39µm)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Alternatively, Claim 1 can be rejected as obvious under 35 USC 103 in view of Kurokawa (US 2019/0172806 A1) in view of Umemoto et. al (US 2019/0386122 A1)
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et. al (US 2021/0083080 A1) in view of Umemoto et. al (US 2019/0386122 A1)
Regarding Claim 1, Sasaki discloses (as shown in Fig. 2A, 5A-B) A semiconductor device ([0083] FIG. 5A illustrates a layout of constituent elements of a semiconductor device according to still another comparative example) comprising:
a substrate ([0065] substrate 70);
a bipolar transistor above the substrate (70), the bipolar transistor including a collector layer ([0068] The collector layer CL), a base layer ([0068] the base layer BL), and an emitter layer ([0068] the emitter layer EL) that are stacked in order from a substrate side; ([0068] The collector layer CL, the base layer BL, and the emitter layer EL are arranged in the stated order from closest to the substrate 70 in the thickness direction of the substrate 70 to constitute a heterojunction bipolar transistor (HBT).)
at least one emitter electrode ([0068] emitter electrode E0) above the emitter layer (EL), ([0068] An emitter layer EL is disposed between the emitter electrode E0 and the base layer BL)
the emitter electrode (E0) being electrically coupled to the emitter layer (EL); ([0070] The emitter electrode E0 is electrically connected to the emitter layer EL)
an interlayer insulating film on the emitter electrode (EL), ([0071] The collector electrode C0, the emitter electrode E0, and the base electrode B0 are covered with an insulating film (not illustrated))
and at least one emitter contact hole ([0072] cavity EV1) in the interlayer insulating film, ([0072] The first-layer emitter line E1 extends through a cavity EV1 in the insulating film disposed thereunder and is electrically connected to the emitter electrode E0 accordingly.)
the emitter contact hole (EV1) being surrounded by the emitter electrode when viewed in plan view; (See Fig. 5A)
and an emitter wire ([0071] first-layer emitter line E1) on the interlayer insulating film, ([0071] A first-layer collector line C1, a first-layer emitter line E1, and a first-layer base line B1 are disposed on the insulating film.)
the emitter wire (E1) being coupled to the emitter electrode (EL) through the emitter contact hole (EV1), ([0072] The first-layer emitter line E1 extends through a cavity EV1 in the insulating film disposed thereunder and is electrically connected to the emitter electrode E0 accordingly.)
wherein when viewed in plan view, the emitter electrode (E0) and the emitter contact hole (EV1) are elongated in one direction, ([0148] The emitter layer EL and the emitter electrode E0 are preferably extended in the first direction D1 in view of, for example, the radio-frequency performance (e.g., the performance at 2.5 GHz) and the breakdown withstand voltage.)
However, Sasaki fails to disclose:
and a first condition is satisfied with respect to the at least one emitter electrode (E0) and the emitter contact hole (EV1) surrounded by the emitter electrode (E0) when viewed in plan view; such that in the first condition, a length of the emitter contact hole (EV1) is 85% or less of a length of the emitter electrode (E0), and of two side ends of the emitter electrode (E0), a distance from each side end to the emitter contact hole (EV1) is 5% or more of the length of the emitter electrode (E0).
Sasaki does not disclose the relative length of the of the emitter contact hole (EV1) to the length of the emitter electrode (E0).
Umemoto discloses (as shown in Fig. 14A) :
and a first condition is satisfied with respect to the at least one emitter electrode (32) and the emitter contact hole (33) surrounded by the emitter electrode (32) when viewed in plan view;
such that in the first condition, a length of the emitter contact hole (33) is 85% or less of a length of the emitter electrode (32), and of two side ends of the emitter electrode (32), a distance from each side end to the emitter contact hole (33) is 5% or more of the length of the emitter electrode.
([0106] In one example, the distance a1 with respect to the longitudinal direction and the distance a2 with respect to the width direction are each about 0.5 μm or less, and the distance b1 with respect to the longitudinal direction is 4 μm or more… [0110] Each of the emitter layers 31 has a length of 40 μm and a width of 3 μm)
Therefore, as shown in Fig. 14A, the emitter electrode (32) has a length of the emitter layer (31) minus 2*a1. This means the emitter electrode (32) has a length of at least 39 µm (40 µm – 2*(<0.5 µm)). The emitter contact hole (33) has a length of the emitter layer (31) minus 2*b1. This means the emitter contact hole (32) has a length of at most 32 µm (40 µm – 2*(>4 µm)). Therefore, the emitter contact hole (33) is at most ~82% (32 µm/39 µm).
Furthermore, the emitter electrode (32) extends beyond the contact hole (33) in the extension direction by the length b1 (from the end of the contact hole 33 to the end of the emitter layer 31) minus the length a1 (from the end of the contact hole 33 to the end of the emitter layer 31). This means the distance between the end of the emitter electrode (32) and the contact hole (31) is b1 (>4 µm) – a1 (<0.5µm). Therefore, the distance between the end of the emitter electrode (32) and the contact hole (31) is at least 3.5 µm. This means the distance from the ends of the emitter contact hole (33) is at least ~9% (3.5 µm/ 39µm)
Umemoto teaches that increasing the distance (a1) between the end of the emitter electrode (32) and the end of the contact hole (33) can increase the transition voltage of the device. ([0082] The results of the evaluation experiment in FIG. 8B show that a significant effect of increasing the transition voltage Vt is obtained when the distance a1 with respect to the longitudinal direction is 3 μm or more) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to increase the distance between ends of the emitter electrode and ends of the contact hole, as in Umemoto, in the device in Sasaki in order to increase the transition voltage.
Regarding Claim 2, Sasaki further discloses (as shown in Fig. 5A) the emitter wire (E1) is within an area having the collector layer (CL) and the base layer (BL) in a longitudinal direction of the emitter electrode (E0). (See Fig. 5A)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Umemoto as applied to claim 1 above, and further in view of Kurokawa (US 2019/0172806 A1).
Regarding Claim 4, Sasaki further discloses (as shown in Figs. 1, 5A-B) a conductive raised portion ([0073] The second-layer emitter line E2 extends through a cavity EV2 in the insulating film disposed thereunder and is electrically connected to the first-layer emitter line E1 accordingly... An emitter bump E3 is disposed so as to be in contact with the second-layer emitter line E2 in the cavity EV3.) on the emitter wire (E1), wherein the conductive raised portion (E2-3) is electrically coupled to the emitter wire (E1). ([0073] The second-layer emitter line E2 extends through a cavity EV2 in the insulating film disposed thereunder and is electrically connected to the first-layer emitter line E1 accordingly... An emitter bump E3 is disposed so as to be in contact with the second-layer emitter line E2 in the cavity EV3.)
However, Sasaki fails to disclose the conductive raised portion (E3) being configured to be coupled to an external circuit,
Kurokawa discloses (as shown in Fig. 2) the conductive raised portion ([0050] the bump 30 ) being configured to be coupled to an external circuit. ([0050] Thus, in addition to its original function of serving as an external connection terminal, the bump 30 also functions as a collective wiring line that connects the two conductor patterns of the emitter electrodes E0 to each other.)
Kurokawa teaches that the bump (30) serves two function of connecting the emitter electrodes together and serving as an external connection terminal. Kurokawa further teaches that doing so allows the manufacturing cost to be reduced by not needing to provide wiring lines crossed with collector collective wiring.
([0050] Thus, in addition to its original function of serving as an external connection terminal, the bump 30 also functions as a collective wiring line that connects the two conductor patterns of the emitter electrodes E0 to each other. Therefore, there is no need to provide wiring lines that are crossed with the collector collective wiring line CC as illustrated in FIG. 3.
[0051] As described above, since there is no need to provide two wiring line layers in the first embodiment, the number of wiring line layers can be reduced compared with the comparative example (FIG. 3). As a result of the number of wiring line layers being reduced, a reduction in manufacturing cost can be achieved.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the bump (E3) in Sasaki serve additional functions of connecting the emitter electrodes together and serving as an external connection terminal, as in Kurokawa, in order to reduce manufacturing costs.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki in view of Umemoto as applied to claim 2 above, and further in view of Kurokawa (US 2019/0172806 A1).
Regarding Claim 6, Sasaki further discloses (as shown in Figs. 1, 5A-B) a conductive raised portion ([0073] The second-layer emitter line E2 extends through a cavity EV2 in the insulating film disposed thereunder and is electrically connected to the first-layer emitter line E1 accordingly... An emitter bump E3 is disposed so as to be in contact with the second-layer emitter line E2 in the cavity EV3.) on the emitter wire (E1), wherein the conductive raised portion (E2-3) is electrically coupled to the emitter wire (E1). ([0073] The second-layer emitter line E2 extends through a cavity EV2 in the insulating film disposed thereunder and is electrically connected to the first-layer emitter line E1 accordingly... An emitter bump E3 is disposed so as to be in contact with the second-layer emitter line E2 in the cavity EV3.)
However, Sasaki fails to disclose the conductive raised portion (E3) being configured to be coupled to an external circuit,
Kurokawa discloses (as shown in Fig. 2) the conductive raised portion ([0050] the bump 30 ) being configured to be coupled to an external circuit. ([0050] Thus, in addition to its original function of serving as an external connection terminal, the bump 30 also functions as a collective wiring line that connects the two conductor patterns of the emitter electrodes E0 to each other.)
Kurokawa teaches that the bump (30) serves two function of connecting the emitter electrodes together and serving as an external connection terminal. Kurokawa further teaches that doing so allows the manufacturing cost to be reduced by not needing to provide wiring lines crossed with collector collective wiring.
([0050] Thus, in addition to its original function of serving as an external connection terminal, the bump 30 also functions as a collective wiring line that connects the two conductor patterns of the emitter electrodes E0 to each other. Therefore, there is no need to provide wiring lines that are crossed with the collector collective wiring line CC as illustrated in FIG. 3.
[0051] As described above, since there is no need to provide two wiring line layers in the first embodiment, the number of wiring line layers can be reduced compared with the comparative example (FIG. 3). As a result of the number of wiring line layers being reduced, a reduction in manufacturing cost can be achieved.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the bump (E3) in Sasaki serve additional functions of connecting the emitter electrodes together and serving as an external connection terminal, as in Kurokawa, in order to reduce manufacturing costs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON JAMES GREAVING/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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