Prosecution Insights
Last updated: April 19, 2026
Application No. 18/474,304

DISPLAY PANEL AND DISPLAY APPARATUS

Non-Final OA §102§112
Filed
Sep 26, 2023
Examiner
BOATMAN, CASEY PAUL
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kunshan Go-Visionox Opto-Electronics Co. Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
3y 7m
To Grant
97%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
52 granted / 64 resolved
+13.3% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
25 currently pending
Career history
89
Total Applications
across all art units

Statute-Specific Performance

§103
49.3%
+9.3% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
22.0%
-18.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 64 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 5-7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding Claim 5, the instant application describes “a relative position between each first circuit block and the pixel block driven by the first circuit block is the same.” Examiner notes that there appears to be a plurality of first circuit blocks and a plurality of pixel blocks driven arranged in a corresponding manner such that the relative position of each corresponding first circuit block and pixel block are the same (shown Figs. 7-8 of the instant application). For examination purposes the claim is interpreted to read “a relative position between each first circuit block and each pixel block driven by a corresponding first circuit block is the same.” Claim 7 is further interpreted to read “a relative position between each second circuit block and each pixel block driven by a corresponding second circuit block is the same.” Claims 6-9, 11-12 and 14-17 are further rejected due to their dependence on claim 5 and lack of further clarity. Regarding Claim 6, a number α of second circuits is cited. It is unclear whether or not this number is supposed to be equivalent to the number α of second circuits cited in claim 4 from which claim 6 depends. For examination purposes, “a number α of second circuits” cited in claim 6 is interpreted to be some separate integer from the number cited in claim 4. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (CN 112186021 A). Regarding Claim 1, Wu teaches a display panel (100) comprising a first display area (DA1) and a second display area (DA3), the display panel comprising: sub-pixels (110 and 150) comprising first sub-pixels (110) located in the first display area and second sub- pixels (150) located in the second display area (shown Fig. 4); pixel driving circuits (120 and 160) located in the second display area and comprising first circuits (120) configured to drive the first sub-pixels (shown, connected to first sub-pixels by connecting lines 130) and second circuits (160) configured to drive the second sub- pixels; and connection lines (130) comprising first connection lines (131) for connecting the first circuits with the first sub-pixels (shown Fig. 4); wherein at least a part of the first connection line extends along a first direction (x-axis) and is located at a side (WA) of the first circuit (shown Fig. 4, wherein WA is defined within the first display area and between first sub-pixels and second sub-pixels). Regarding Claim 2, Wu teaches the display panel according to claim 1, wherein the display panel further comprises a first signal line layer (102, layers corresponding to M2 and M3) comprising a first signal line (power supply line, in which there is “a portion of the second metal wire section 132 of the connection line 130 in the same layer as the power supply line”), at least a part of the first connection line is located in the first signal line layer (shown Fig. 5), and the first signal line comprises at least one of a data line, a scanning line, a power line, a voltage reference line, and a ground line. Regarding Claim 3, Wu teaches the display panel according to claim 2, wherein the display panel further comprises a light-transmitting signal line layer (top layer of device layer 102), the first connection line comprises a first segment located in the first display area (133, shown Fig. 5) and a second segment (131) located in the second display area, the first segment is located in the light-transmitting signal line layer (shown Fig. 5), and the second segment is located in the first signal line layer and/or the light-transmitting signal line layer (shown Fig. 5). Regarding Claim 4, Wu teaches the display panel according to claim 1, wherein the first circuit and a number α of second circuits form a first circuit block (described as a “row”, shown in DA3 of Fig. 4, extending in the x-direction, see also annotated below), α is an integer greater than 1 (shown Fig. 4), at least the part of the first connection line extending along the first direction is located at a side of the first circuit block where the first circuit connected with the first connection line is located (shown Fig. 5). PNG image1.png 100 100 image1.png Greyscale Regarding Claim 5, Wu teaches the display panel according to claim 4, wherein a number α of adjacent second sub- pixels form a pixel block (103, shown Figs. 4-5), the α second circuits in the first circuit block are configured to drive the α second sub-pixels in a same pixel block, the display panel comprises a plurality of first circuit blocks (arranged along the y-direction, shown fig. 4), and a relative position between each first circuit block and the pixel block driven by the first circuit block is the same. Regarding Claim 6, Wu teaches the display panel according to claim 5, wherein the pixel driving circuit further comprises a virtual area (portion 120), and the virtual area and a number α of second circuits (160) form a second circuit block (see annotated above). Regarding Claim 7, Wu teaches the display panel according to claim 6, wherein the a second circuits in the second circuit block are configured to drive the a second sub-pixels in a same pixel block (shown Fig. 4), the display panel comprises a plurality of second circuit blocks (shown arranged along the y-direction), and a relative position between each second circuit block and the pixel block driven by the second circuit block is the same (shown Figs. 4-5). Regarding Claim 8, Wu teaches the display panel according to claim 6, wherein along a thickness direction of the display panel, a size of an orthographic projection of the first circuit is the same as a size of the virtual area (shown Fig. 4); and a size of an orthographic projection of the first circuit block is the same as a size of an orthographic projection of the second circuit block (shown Fig. 4, see also annotated above). Regarding Claim 9, Wu teaches the display panel according to claim 6, wherein a number of the first circuits in the first circuit block is the same as a number of the virtual areas in the second circuit block (shown Fig. 4, see also annotated above). Regarding Claim 10, Wu teaches the display panel according to claim 1, wherein at least the part of the first connection line extending along the first direction is located at a side of the first circuit along a second direction (y-direction), and the first direction intersects the second direction (shown Fig. 4). Regarding Claim 11, Wu teaches the display panel according to claim 6, wherein a relative positional relationship between the first circuit and the second circuits in the first circuit block is the same as a relative positional relationship between the virtual area and the second circuits in the second circuit block (see annotated Fig. 4 above). Regarding Claim 12, Wu teaches the display panel according to claim 6, wherein a virtual circuit is arranged in the virtual area, and a structure of the virtual circuit is the same as a structure of the first circuit. Regarding Claim 13, Wu teaches the display panel according to claim 1, wherein the second display area comprises a main display area (DA2) and a transition area (DA3) located between the main display area and the first display area (shown Fig. 3), and the first circuits are located in the transition area (shown Fig. 4). Regarding Claim 14, Wu teaches the display panel according to claim 6, wherein virtual conductive lines (corresponding to lines 130 connected to the second circuit blocks) are arranged at a side of at least a part of the second circuit blocks along a second direction (shown Fig. 4), the virtual conductive lines extend along the first direction, and the first direction intersects the second direction (shown Fig. 4, configured similarly to the first circuit blocks). Regarding Claim 15, Wu teaches the display panel according to claim 14, wherein the virtual conductive lines comprise first virtual conductive lines located at at least one side of the second circuit blocks along the second direction, and a relative position between the second circuit block and the first virtual conductive line corresponding to the second circuit block is the same as a relative position between the first circuit block and the first connection line corresponding to the first circuit block (shown Fig. 4). Regarding Claim 16, Wu teaches the display panel according to claim 15, wherein a plurality of rows of the second circuit blocks are arranged at at least one side (a bottom side along the y-direction, shown Fig. 4) of the first circuit block along the second direction (shown Fig. 4), the first virtual conductive lines are arranged at a same side of the rows of the second circuit blocks along the second direction (shown Fig. 4). Regarding Claim 17, Wu teaches the display panel according to claim 14, wherein the virtual conductive lines comprise second virtual conductive lines located at at least one side of the first connection lines along the first direction (shown Fig. 4). Regarding Claim 18, Wu teaches the display panel according to claim 1, wherein the connection lines connected with the sub-pixels of a same color are manufactured using a same material (shown, wherein pixels of a same color are arranged connected to a same metal layer of at least a same metal material, see Figs. 4-5). Regarding Claim 19, Wu teaches the display panel according to claim 1, wherein the first sub-pixels and the second sub-pixels are distributed in rows and columns (shown Fig. 4), the first circuits and the second circuits are distributed in rows and columns (shown Fig. 4), at least a part of the first circuits and the second circuits are arranged side by side along the first direction and located in a same row (see annotated Fig. 4 above), and the first circuits and the second circuits located in a same row are configured to drive the first sub-pixels and the second sub-pixels located in a same row (shown Fig. 4). Regarding Claim 20, Wu teaches a display apparatus comprising the display panel according to claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Xu (US 20210359080 A1) teaches a display panel comprising a first area, second area, and a transition area wherein connecting lines of pixel driving circuits are arranged at a side of the second area. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.P.B./Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Sep 26, 2023
Application Filed
Mar 03, 2026
Non-Final Rejection — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
97%
With Interview (+15.4%)
3y 7m
Median Time to Grant
Low
PTA Risk
Based on 64 resolved cases by this examiner. Grant probability derived from career allow rate.

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