Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment to claims 1, 5, 7, 8, 9, 10, 11, 12, 15, 16, 17 and 20 submitted June 10, 2026 are acknowledged and have since been entered. Cancellation of claims 4, 6 and 14 are further acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 20 recites the limitation "the first display area" and “the second display area”. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, the limitations are interpreted to be “a first display area” and “a second display area” respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 7-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cai (CN 111708199 A) in further view of Chang (US 20210351255 A1).
Regarding Claim 1, Cai teaches a display panel (see Figs. 2, 3, 4 and 7) comprising a first display area (AA1) and a second display area (AAG and AA2), the display panel comprising:
sub-pixels (sp, shown Fig. 3) comprising first sub-pixels (sp1) located in the first display area and second sub-pixels (sp, shown Fig. 3 located in AAG and AA2) located in the second display area;
pixel driving circuits (DL1) located in the second display area and comprising first circuits configured to drive the first sub-pixels (shown Fig. 4), the first circuits being located in the second display area (shown Figs. 3-4); and connection lines (X, shown Fig. 4) comprising first connection lines for connecting the first circuits with the first sub-pixels (see Fig. 7) wherein at least a part of the first connection line extends along a first direction (x-direction) and is located at a side of the first circuit (shown Fig. 4);
the first circuit being a part of a first circuit block (see annotated below, corresponding to a block of first and second sub-pixels), at least the part of the first connection line extending along the first direction is located at a side of the first circuit block where the first circuit connected with the first connection line is located (see Figs. 2-3 and 7);
at least one of the pixel driving circuits further comprises a dummy area (DLx, a dummy pixel circuit which includes a dummy area, shown Fig. 7) located in the second display area (shown Fig. 7 being located in AAG), and the dummy area forms a part of a second circuit block (see annotated below); and
the display panel further comprises dummy conductive lines (X1x, shown Fig. 7) that are arranged at a side of at least a part of the second circuit blocks along a second direction (y-direction, shown Fig. 7) and extend along the first direction intersecting the second direction (shown Fig. 7).
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Cai further shows first sub-pixels being connected to first circuits, but does not explicitly describe a number α of second circuits configured to drive the second sub- pixels, the second circuits being located in the second display area (shown Figs. 3-4), and the number α of second circuits being in the first circuit block and second circuit block. As annotated above, Cai shows a first circuit block corresponding to an upper first circuit comprising at least six second sub-pixels in the AAG region, which are arranged in two rows, but is silent regarding the disposition of pixel circuitry corresponding to the second sub-pixels.
Chang teaches a display panel comprising a first display area (21, shown Fig. 2) and a second display area (22) wherein a plurality of second circuits (25) are disposed in a one-to-one correspondence to second sub-pixels in the second display area (see Chang: Fig. 3 and [0031]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a one-to-one correspondence of second pixel circuits to second sub-pixels as suggested by Chang to the second sub-pixels of Cai as this would advantageously enable independent control of the pixels, “which is beneficial to improve the display quality” (see also Chang: [0041]).
As applied to Cai, this modification would teach a number α of second circuits being part of the first circuit block, wherein α is an integer greater than 1, and the number α of second circuits further being part of the second circuit block corresponding to the dummy area.
Regarding Claim 2, Cai as modified by Chang teaches the display panel according to claim 1, wherein the display panel further comprises a first signal line layer (shown Fig. 4, comprising upper portions of the source/drain regions of DL1 and a lower portion of the first connection line) comprising a first signal line (a line connected to a source on the left side of transistor T shown in Fig. 4, wherein a power supply voltage line must be implemented to drive the transistor of the pixel circuit and would at least partially be located in the first signal line layer to electrically connect to the source of transistor T), at least a part of the first connection line is located in the first signal line layer and the first signal line comprises at least one of a data line, a scanning line, a power line, a voltage reference line, and a ground line.
Regarding Claim 3, Cai as modified by Chang teaches the display panel according to claim 2, wherein the display panel further comprises a light-transmitting signal line layer (the layer immediately above the signal line layer of Fig. 4), the first connection line comprises a first segment located in the first display area and a second segment located in the second display area (shown Fig. 4), the first segment is located in the light-transmitting signal line layer (shown Fig. 4), and the second segment is located in the first signal line layer and/or the light-transmitting signal line layer (shown Fig. 4).
Regarding Claim 5, Cai as modified by Chang teaches the display panel according to claim 1, wherein a number α of adjacent second sub-pixels form a pixel block, the α second circuits in the first circuit block are configured to drive the α second sub-pixels in a same pixel block (as modified by Chang in Claim 1, the second circuits and second sub-pixels have a one-to-one correspondence), the display panel comprises a plurality of first circuit blocks (shown Fig. 7), and a relative position between each of the plurality of first circuit blocks and one of the pixel blocks driven by a corresponding one of the plurality of the first circuit blocks is the same (see Figs. 2, 3 and 7).
Regarding Claim 7, Cai as modified by Chang teaches the display panel according to claim 5, wherein the α second circuits in the second circuit block are configured to drive the α second sub-pixels in a same pixel block (as modified by Chang in claim 1, the second circuits and second sub-pixels have a one-to-one correspondence), the display panel comprises a plurality of second circuit blocks (shown Fig. 7), and a relative position between each of the plurality of second circuit blocks and one of the pixel blocks driven by a corresponding one of the plurality of the second circuit blocks is the same (shown Fig. 7).
Regarding Claim 8, Cai as modified by Chang teaches the display panel according to claim 5, wherein along a thickness direction of the display panel, a size of an orthographic projection of the first circuit is the same as a size of the dummy area (shown Fig. 7); and
a size of an orthographic projection of the first circuit block is the same as a size of an orthographic projection of the second circuit block (see Figs. 2, 3 and 7, wherein the plurality of circuit blocks are shown being the same size along a vertical direction).
Regarding Claim 9, Cai as modified by Chang teaches the display panel according to claim 5, wherein a number of the first circuits in the first circuit block is the same as a number of the dummy areas in the second circuit block (shown Fig. 7, wherein a first circuit block has one first circuit and the second circuit block has one dummy area).
Regarding Claim 10, Cai as modified by Chang teaches the display panel according to claim 1, wherein at least the part of the first connection line extending along the first direction is located at a side of the first circuit along a second direction (shown Fig. 7).
Regarding Claim 11, Cai as modified by Chang teaches the display panel according to claim 5, wherein a relative positional relationship between the first circuit and the second circuits in the first circuit block is the same as a relative positional relationship between the dummy area and the second circuits in the second circuit block (see Figs. 2, 3 and 7).
Regarding Claim 12, Cai as modified by Chang teaches the display panel according to claim 5, wherein a dummy circuit is arranged in the dummy area, and a structure of the dummy circuit is the same as a structure of the first circuit (shown Fig. 7, wherein DLx and DL1 are structurally consistent).
Regarding Claim 13, Cai as modified by Chang teaches the display panel according to claim 1, wherein the second display area comprises a main display (AA2) area and a transition area (AAG) located between the main display area and the first display area, and the first circuits are located in the transition area (see Figs. 2, 3 and 7).
Regarding Claim 15, Cai as modified by Chang teaches the display panel according to claim 5, wherein the dummy conductive lines comprise first dummy conductive lines (X1x, shown Fig. 7) located at at least one side of the second circuit blocks along the second direction (shown Fig. 7), and a relative position between the second circuit block and the first dummy conductive line corresponding to the second circuit block is the same as a relative position between the first circuit block and the first connection line corresponding to the first circuit block (shown Fig. 7).
Regarding Claim 16, Cai as modified by Chang teaches the display panel according to claim 15, wherein a plurality of rows of the second circuit blocks are arranged at at least one side of the first circuit block along the second direction (shown Fig. 7, wherein at least two rows of second circuit blocks defined by dummy areas DLx are shown located at one side of the top first circuit block along the second direction), the first dummy conductive lines are arranged at a same side of the rows of the second circuit blocks along the second direction (shown Fig. 7, wherein lines corresponding to X1x are shown being located at a bottom side of the dummy areas).
Regarding Claim 17, Cai as modified by Chang teaches the display panel according to claim 5, wherein the dummy conductive lines comprise second dummy conductive lines located at at least one side of the first connection lines along the first direction (shown Fig. 7, wherein dummy conductive lines to the right side of the first display area are shown being laterally adjacent along the x-direction to first connection lines of DL1).
Regarding Claim 18, Cai as modified by Chang teaches the display panel according to claim 1. Cai and Chang are silent regarding a material selection of the connection lines connected with sub-pixels of a same color.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a same conductive material for the connection lines connected with sub-pixels of a same color to reduce manufacturing complexity and maintain consistent electrical characteristics as this is a well-known practice in the art.
Regarding Claim 19, Cai as modified by Chang teaches the display panel according to claim 1, wherein the first sub-pixels and the second sub-pixels are distributed in rows and columns, the first circuits and the second circuits are distributed in rows and columns, at least a part of the first circuits and the second circuits are arranged side by side along the first direction and located in a same row, and the first circuits and the second circuits located in a same row are configured to drive the first sub-pixels and the second sub-pixels located in a same row (shown Figs. 2, 3 and 7).
Regarding Claim 20, Cai as modified by Chang teaches a display apparatus (i.e., “any electronic device with a display function”) comprising a display panel (see Figs. 2, 3, 4 and 7) comprising:
sub-pixels (sp, shown Fig. 3) comprising first sub-pixels (sp1) located in a first display area (AA1) and second sub-pixels (sp, shown Fig. 3 located in AAG and AA2) located in a second display area (AAG and AA2);
pixel driving circuits (DL1) located in the second display area and comprising first circuits configured to drive the first sub-pixels (shown Fig. 4), the first circuits being located in the second display area (shown Figs. 3-4); and connection lines (X, shown Fig. 4) comprising first connection lines for connecting the first circuits with the first sub-pixels (see Fig. 7) wherein at least a part of the first connection line extends along a first direction (x-direction) and is located at a side of the first circuit (shown Fig. 4);
the first circuit being a part of a first circuit block (see annotated below, corresponding to a block of first and second sub-pixels), at least the part of the first connection line extending along the first direction is located at a side of the first circuit block where the first circuit connected with the first connection line is located (see Figs. 2-3 and 7);
at least one of the pixel driving circuits further comprises a dummy area (DLx, a dummy pixel circuit which includes a dummy area, shown Fig. 7) located in the second display area (shown Fig. 7 being located in AAG), and the dummy area forms a part of a second circuit block (see annotated below); and
the display panel further comprises dummy conductive lines (X1x, shown Fig. 7) that are arranged at a side of at least a part of the second circuit blocks along a second direction (y-direction, shown Fig. 7) and extend along the first direction intersecting the second direction (shown Fig. 7).
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Cai further shows first sub-pixels being connected to first circuits, but does not explicitly describe a number α of second circuits configured to drive the second sub- pixels, the second circuits being located in the second display area (shown Figs. 3-4), and the number α of second circuits being in the first circuit block and second circuit block. As annotated above, Cai shows a first circuit block corresponding to an upper first circuit comprising at least six second sub-pixels in the AAG region, which are arranged in two rows, but is silent regarding the disposition of pixel circuitry corresponding to the second sub-pixels.
Chang teaches a display panel comprising a first display area (21, shown Fig. 2) and a second display area (22) wherein a plurality of second circuits (25) are disposed in a one-to-one correspondence to second sub-pixels in the second display area (see Chang: Fig. 3 and [0031]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a one-to-one correspondence of second pixel circuits to second sub-pixels as suggested by Chang to the second sub-pixels of Cai as this would advantageously enable independent control of the pixels, “which is beneficial to improve the display quality” (see also Chang: [0041]).
As applied to Cai, this modification would teach a number α of second circuits being part of the first circuit block, wherein α is an integer greater than 1, and the number α of second circuits further being part of the second circuit block corresponding to the dummy area.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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