Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 9-13, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lehwalder et al. U.S. PGPUB No. 2020/0201408.
Per Claim 1, Lehwalder discloses:
an apparatus (electronic device 102) comprising:
a first intellectual property (IP) circuit to execute operations on data (Paragraphs 23 and 24; Processor 150 comprises multiple processor cores.);
and a power controller coupled to the first IP circuit (Paragraph 22; Dynamic voltage adjustment circuitry 140),
wherein the power controller is to:
receive a boost value, the boost value based at least in part on one or more characteristics of a power supply coupled to the apparatus; determine a boosted maximum power level for the apparatus based at least in part on the boost value and a legacy maximum power level for the apparatus, the boosted maximum power level greater than the legacy maximum power level (Paragraph 25; “If the target frequency is higher than the current processor frequency then Vcc may be increased and the increased value for Vcc may be signaled by the bus 161 to the DVAC 140 and once the voltage is established, a phase locked loop (not shown) may lock the processor onto the target frequency.”; The “increased value for Vcc” reads on the boost value. The establishment of the voltage represents the claimed boosted maximum power level. Paragraph 27 discusses a high performance turbo mode state that increases the maximum power level and is based at least in part on the max output capacity of the power supply.);
and provide a boosted maximum power budget for the first IP circuit based at least in part on the boosted maximum power level, the boosted maximum power budget for the first IP circuit greater than a legacy maximum power budget for the first IP circuit (Paragraph 27, “The maximum turbo level of the processor 150 may be adjusted depending on the maximum output capacity of the power supply with respect to a minimum system input voltage.”);
wherein the first IP circuit, in response to receipt of an input voltage violation signal, is to reactively reduce power consumption equal to or below the legacy maximum power budget for the first IP circuit (Paragraph 29, Fig. 2; “The “Prochot #” is a signal 231 that may be used to “throttle” the one or more processors to activate a power reduction in response to a threshold condition being triggered.”).
Per Claim 2, Lehwalder discloses the apparatus of claim 1, wherein the first IP circuit is to receive the input voltage violation signal directly from a controller coupled to the power supply (Paragraph 29, Fig. 2; The charger 230 incorporates the power monitoring circuitry 142 of Fig. 1. PROCHOT# signal is provided to CPU 250 from charger 230.).
Per Claim 3, Lehwalder discloses the apparatus of claim 2, further comprising a hardwire path coupled to the first IP circuit to provide the input voltage violation signal directly from the controller to the first IP circuit (Figures 2 and 3; PROCHOT# signal 231 and critical warning output port 382).
Per Claim 4, Lehwalder discloses the apparatus of claim 1, wherein the power controller is to receive the boost value from a system software (Paragraph 25; The DVAC 140 adjusts Vcc based on the processor activity and a maximum power available from a selected power source. Once a battery is selected as the power source, then Vcc depends on the charge level of the battery. A power control unit of the processor sets a target frequency, and if it is higher than the current processor frequency, then Vcc is increased by a calculated/determined value. Software is necessary to determine this value. Paragraph 92 further teaches the use of software and/or hardware to perform the disclosed steps of the invention.).
Per Claim 7, Lehwalder discloses the apparatus of claim 1, wherein the first IP circuit, within less than 10 microseconds from receipt of the input voltage violation signal, is to reactively reduce the power consumption equal to or below the legacy maximum power budget for the first IP circuit (Paragraph 52; “allowing the data processing apparatus 310 to take action to reduce power rapidly within microseconds of the occurrence of the critical power condition”).
Per Claim 9, Lehwalder The apparatus of claim 7, wherein the first IP circuit is to autonomously reactively reduce the power consumption equal to or below the legacy maximum power budget for the first IP circuit, in response to receipt of the input voltage violation signal (Paragraphs 29 and 42; “The PROCHOT# is a signal 231 that may be used to throttle the one or more processors to activate a power reduction in response to a threshold condition being triggered.”).
Per Claim 10, Lehwalder discloses the apparatus of claim 1, further comprising a second IP circuit to execute operations on second data (Paragraph 24; “multiple processor cores”), wherein the power controller is to provide a second legacy maximum power budget for the second IP circuit, the second IP circuit to not exceed the second legacy maximum power budget (The teachings of paragraphs 27 and 29 are equally applicable to a second processor core. Paragraph 42 teaches one or more cores.).
Per Claim 11, Lehwalder discloses a method comprising: receiving, in at least one intellectual property (IP) circuit of a system on chip (SoC) (Paragraph 29; SOC 250 may comprise one or more processors), an indication that an input voltage to a voltage regulator coupled to the SoC has fallen below a threshold level (Paragraphs 29; “Prochot # is a signal 231 that may be used to throttle the one or more processors to activate a power reduction in response to a threshold condition being triggered.”; Paragraph 30; “Vsys has an under-voltage detect”); and in response to the indication, autonomously, in the at least one IP circuit, reducing power consumption of the at least one IP circuit to a level below a legacy maximum IP power budget, the legacy maximum IP power budget set by a power controller of the SoC (Paragraphs 29 and 42; “The PROCHOT# is a signal 231 that may be used to throttle the one or more processors to activate a power reduction in response to a threshold condition being triggered.”; Paragraphs 25 and 27 discuss the DVAC 140 and power profiles.).
Per Claim 12, Lehwalder discloses the method of claim 11, further comprising receiving the indication in the at least one IP circuit via a hardwire connection to a voltage regulator controller coupled to the SoC (Paragraph 29, Fig. 2; The charger 230 incorporates the power monitoring circuitry 142 of Fig. 1. PROCHOT# signal is provided to CPU 250 from charger 230. Paragraphs 29 and 42; voltage regulator unit 250).
Per Claim 13, Lehwalder discloses the method of claim 11, further comprising reducing the power consumption of the at least one IP circuit to the level below the legacy maximum IP power budget within 10 microseconds from receipt of the indication (Paragraph 52; “allowing the data processing apparatus 310 to take action to reduce power rapidly within microseconds of the occurrence of the critical power condition”).
Per Claim 16, Lehwalder discloses the method of claim 11, further comprising maintaining a power consumption of a second IP circuit at a level below a legacy maximum second IP power budget, the legacy maximum second IP power budget set by the power controller (Paragraph 24; “multiple processor cores”; The teachings of paragraphs 27 and 29 are equally applicable to a second processor core. Paragraph 42 teaches one or more cores.)
Per Claim 17, Lehwalder discloses a system comprising: a voltage regulator to receive a system voltage and output an operating voltage (Paragraphs 29 and 42; voltage regulator 250); a voltage regulator controller to identify when the system voltage falls below a threshold voltage (Paragraph 29; power monitoring circuitry 142); a system on chip (SoC) coupled to the voltage regulator (Paragraph 29; SoC and voltage regulator unit 250), the SoC to receive the operating voltage (Fig. 2) and comprising: at least one first intellectual property (IP) circuit to execute operations on first data; at least one second IP circuit to execute operations on second data (Paragraphs 23 and 24; Processor 150 comprises multiple processor cores that receive and operate on data.); and a power controller (Paragraph 22; Dynamic voltage adjustment circuitry 140) to: receive a boost value, the boost value based at least in part on one or more characteristics of the voltage regulator; determine a boosted maximum power level for the SoC based at least in part on the boost value and a legacy maximum power level for the SoC, the boosted maximum power level greater than the legacy maximum power level (Paragraph 25; “If the target frequency is higher than the current processor frequency then Vcc may be increased and the increased value for Vcc may be signaled by the bus 161 to the DVAC 140 and once the voltage is established, a phase locked loop (not shown) may lock the processor onto the target frequency.”; The “increased value for Vcc” reads on the boost value. The establishment of the voltage represents the claimed boosted maximum power level. Paragraph 27 discusses a high performance turbo mode state that increases the maximum power level and is based at least in part on the max output capacity of the power supply.); and determine a boosted maximum power budget for the at least one first IP circuit based at least in part on the boosted maximum power level, the boosted maximum power budget for the at least one first IP circuit greater than a legacy maximum power budget for the at least one first IP circuit (Paragraph 27, “The maximum turbo level of the processor 150 may be adjusted depending on the maximum output capacity of the power supply with respect to a minimum system input voltage.”), wherein the at least one first IP circuit, is to reduce power consumption equal to or below the legacy maximum power budget for the at least one the first IP circuit, in reaction to the input voltage falling below the threshold voltage (Paragraph 29, Fig. 2; “The “Prochot #” is a signal 231 that may be used to “throttle” the one or more processors to activate a power reduction in response to a threshold condition being triggered.”); and a non-volatile memory coupled to the SoC (Paragraphs 24, 26, and 93).
Per Claim 18, Lehwalder discloses the system of claim 17, wherein the voltage regulator controller is to send a voltage violation signal to the SoC when the system voltage falls below the threshold voltage (Paragraphs 29, 30; Fig. 2; PROCHOT#).
Per Claim 19, Lehwalder discloses the system of claim 18, further comprising a hardwire path coupled between the voltage regulator controller and the at least one first IP circuit, the voltage regulator controller to send the voltage violation signal to the at least one first IP circuit via the hardwire path (Figures 2 and 3; PROCHOT# signal 231 and critical warning output port 382).
Per Claim 20, Lehwalder discloses the system of claim 18, wherein the at least one first IP circuit is to autonomously reduce the power consumption equal to or below the legacy maximum power budget for the at least one first IP circuit based on the voltage violation signal (Paragraphs 29 and 42; “The PROCHOT# is a signal 231 that may be used to throttle the one or more processors to activate a power reduction in response to a threshold condition being triggered.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lehwalder et al. U.S. PGPUB No. 2020/0201408 in view of Kim et al. U.S. PGPUB No. 2012/0173895.
Per Claims 5 and 6, Lehwalder does not specifically teach a configuration storage to store the boost value and determining a boosted max power level to comprise the sum of a boosted value and a legacy max power level. Per Claim 8, Lehwalder does not specifically teach a storage to store the power budgets
However, Kim, of a common assignee to Lehwalder, teaches retrieving a power budget value from a power budget-frequency register 102-A. The power budget factor/value represents an amount of power required to increase or boost the frequency of a processing domain for a specific power budget (Paragraphs 21, 23, 25, and 28; Fig. 3).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to store the Vcc values of Lehwalder within a register storage, as taught by Kim, because it advantageously leads to efficiency and increased performance (Kim, Paragraph 19).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14 distinguishes over Lehwalder and the prior art because no combination nof Lehwalder and the prior art teaches or makes obvious that the SoC and the IP circuits of the SoC comprise separate boosted maximum power budgets. Lehwalder teaches a boosted power mode for a specific processor/core 150 (Paragraph 29) but does not specifically teach that SoC 250 comprises a separate boosted maximum power budget from which the boosted maximum power budget of the processor is based on.
Claim 15 inherits the allowable subject matter of claim 14.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Prior Art
The prior art made of record but not relied upon in the Examiner’s rejections is cited as it is considered pertinent to the applicant’s disclosure due to various teachings of PROCHOT “voltage violation” signals, turbo mode processing, and voltage violation mitigation techniques.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
