DETAILED ACTION
The communication is in response to the application filed 9/26/2023 which claims 1-20 are pending in the application. Claims 1, 17 and 20 are independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 8 is objected to because of the following informalities: “analysing” should be “analyzing”. Appropriate correction is required.
Claim 11 is objected to because of the following informalities: “analysing” should be “analyzing”. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 8, 11 and 12 are rejected under 35 U.S.C. 101 because the claims is directed to an abstract idea without significantly more.
Step 1: Claims 8, 11 and 12 are directed to a method (series of steps) and therefore is a process which is one the statuary categoric of invention.
Step 2A, Prong 1:
Claim 8 recite the limitation “analysing system information during processing of the primary workload and/or the secondary workload;”. This limitation is a method (series of step) that, under the broadest reasonable interpretation, cover the performance of in the mind, with the use of generic computer components. In within the claims the word “analysing” encompasses user mentally, based on observation, evaluation, judgement or opinion.
If a claim limitation, under its broadest reasonable interpretation, covers the performance of the limitation in the mind, then its falls within the “Mental Process” grouping of abstract ideas the concepts performed in the minds including an observation, evaluation, judgement, and opinion.
Step 2A, Prong 2:
The judicial exception is not integrated into a practical application, 8 claim recite additional elements “in response to the analysis, updating system information in storage.” This amounts to data gathering which is considered to be insignificant extra solution activity (See MPEP 2106.05(g); Because claim 8 inherited from what in claim 1, claim 1 recite the limitations “
A method of operating a data processor unit to generate processing tasks: the data processor unit comprising:
a control circuit to receive, from a host processor unit, a request for the data processor unit to perform processing jobs (This amounts to data gathering which is considered to be insignificant extra solution activity (See MPEP 2106.05(g)); and to generate a workload for each job, where each workload comprises one or more tasks; and first and second execution units to process the workloads, (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
the method comprising: receiving, at the control circuit, a request (This amounts to data gathering which is considered to be insignificant extra solution activity (See MPEP 2106.05(g)); to perform first and second processing jobs; (This limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP 2106.05(f))
generating, at the control circuit in response to the request, a primary workload for the first processing job, and a secondary workload for the second processing job; (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
generating, at the control circuit, one or more operation instructions to control processing of the primary and/or secondary workloads at the first and/or second execution units; (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
processing, at the first execution unit, the primary workload in accordance with the operation instructions; and (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
processing, at the second execution unit, the secondary workload in parallel with the primary workload in accordance with the operation instructions. (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
The “system information in storage”, “first execution unit”, “second execution unit”, “control circuit”, “primary/secondary workload” “first/secondary processing job”, “host processor unit” and “data processor unit” are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that is amounts no more than mere instruction to apply the exception using a generic computer component. Accordingly, this additional element doesn’t integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (See MPEP 2106.059f)). The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to the amount to significantly more than the judicial exception. The limitations of “receiving”, “updating” are considered mere data gathering which the courts have identified as well well-understood, routine, and conventional. (MPEP 2106.05(d)). These limitations “generating” and “processing” are considered no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)). As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of the “control circuit”, “first execution unit”, “second execution unit”, “system information in storage”, “primary/secondary workload” “first/secondary processing job”, “host processor unit” and “data processor unit” are merely a generic computer or generic computer components to apply the judicial exception which cannot provide an inventive concept.
Claim 1 recite the limitations:
“A method of operating a data processor unit to generate processing tasks: the data processor unit comprising:
a control circuit to receive, from a host processor unit, a request (This amounts to data gathering which is considered to be insignificant extra solution activity (See MPEP 2106.05(g)); for the data processor unit to perform processing jobs and to generate a workload for each job, where each workload comprises one or more tasks; and first and second execution units to process the workloads, (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
the method comprising: receiving, at the control circuit, a request to (This amounts to data gathering which is considered to be insignificant extra solution activity (See MPEP 2106.05(g)); perform first and second processing jobs; (This limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP 2106.05(f))
generating, at the control circuit in response to the request, a primary workload for the first processing job, and a secondary workload for the second processing job; (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
generating, at the control circuit, one or more operation instructions to control processing of the primary and/or secondary workloads at the first and/or second execution units; (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
processing, at the first execution unit, the primary workload in accordance with the operation instructions; and (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
processing, at the second execution unit, the secondary workload in parallel with the primary workload in accordance with the operation instructions. (This additional element does not integrate the abstract idea into a practical application because they amount to no more than mere instructions to apply the abstract idea using generic computer components. (see MPEP 2106.05(f)))
Claim 11 recite the limitation “analysing, with an analysis unit, the system information in storage during processing of the primary workload and/or the secondary workload.” This limitation is a method (series of step) that, under the broadest reasonable interpretation, cover the performance of in the mind, with the use of generic computer components. In within the claims the word “analysing” encompasses user mentally, based on observation, evaluation, judgement or opinion.
If a claim limitation, under its broadest reasonable interpretation, covers the performance of the limitation in the mind, then its falls within the “Mental Process” grouping of abstract ideas the concepts performed in the minds including an observation, evaluation, judgement, and opinion.
Claim 12 recite the limitation “determining an operational status of the first execution unit and/or the second execution unit based on or in response to the analysis of the system information in storage during processing of the primary workload and/or the secondary workload.” This limitation is a method (series of step) that, under the broadest reasonable interpretation, cover the performance of in the mind, with the use of generic computer components. In within the claims the word “determining” encompasses user mentally, based on observation, evaluation, judgement or opinion.
If a claim limitation, under its broadest reasonable interpretation, covers the performance of the limitation in the mind, then its falls within the “Mental Process” grouping of abstract ideas the concepts performed in the minds including an observation, evaluation, judgement, and opinion.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-2 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Robatmili (US 2016/0292012) in view of, Kitano (US 2016/0014198) in view of, Pulshipher (US 7,117,500) in view of, Rastogi (US 2011/0321051).
As per claim 1, Robatmili primarily teaches the invention as claimed
including a method of operating a data processor unit to generate processing tasks ([0064] central controller may generate multiple tasks):
the data processor unit (fig. 4, block 402 iteration space splitter controller ITSS central controller and [0004] “the central controller of the processor”) comprising:
first and second execution units to process the workloads [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”,
the method comprising:
generating, at the control circuit, one or more operation instructions to control processing of the first and/or second workloads at the first and/or second execution units [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or
processor core and the second task to execute by a second processor or processor core in parallel”;
processing, at the first execution unit, the first workload in accordance with the operation instructions [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel”; and
processing, at the second execution unit, the second workload in parallel with the first workload in accordance with the operation instructions [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel”.
Robatmili does not explicitly disclose:
a control circuit to receive, from a host processor unit, a request for the data processor unit to perform processing jobs and to generate a workload for each job, where each workload comprises one or more tasks; and
receiving, at the control circuit, a request to perform first and second processing jobs;
generating, at the control circuit in response to the request, a primary workload for the first processing job, and a secondary workload for the second processing job;
primary workloads/tasks and secondary workload/tasks executing in parallel.
However, Kitano disclose:
a control circuit to receive, from a host processor unit, a request for the data processor unit to perform processing jobs [0054] “The job client 12 feeds a job i.e., processing request which is to be executed by the information processing apparatus 11” and to generate a workload for each job, where each workload comprises one or more tasks [0083]” When the job receiver 41 receives a job, a request is given to the task generator 42 to divide the job into tasks”; and
generating, at the control circuit in response to the request, a workload/task for the first processing job, and a workload/task for the second processing job “[0083] When the job receiver 41 receives a job, a request is given to the task generator 42 to divide the job into tasks”.
Robatmili and Kitano are combinable because they are in similar fields which is allocating task within a data unit.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of Kitano to have control circuit to receive a request from a data processing unit which then can generate based on the request received to create a workload for each task and within that request then assign a task to a primary or first secondary processing job. Motivation to combine would be precisely assign a task/workload to a primary or secondary processing job after generating a response from the circuit control for task/workload that was requested.
Robatmili in view of Kitano do not explicitly disclose:
receiving, at the control circuit, a request to perform first and second processing jobs;
primary workloads/tasks and secondary workload/tasks executing in parallel.
However, Pulshipher disclose:
receiving, at the control circuit, a request to perform first and second processing jobs “col. 27, ll. 36-37 receiving a work request, said work request specifying a first job and a second job”.
Robatmili and Pulshipher are both combinable because they are in similar fields which is a request that define tasks within a computing environment.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Pulshipher to receiving a request from the control circuit to perform first and second processing jobs. Motivation to combine would be directing having the control circuit from the data processing unit receive the request and upon that request to perform first and second processing.
Robatmili in view of Kitano in view of Pulshipher do not explicitly disclose primary workloads/tasks and secondary workload/tasks executing in parallel.
However, Rastogi disclose primary tasks and secondary tasks executing in parallel [0022] “primary tasks and secondary tasks and” [0024]” execution of the primary tasks and secondary tasks may be parallelized”.
Robatmili and Rastogi are combinable because they in similar fields which is processing tasks in parallel.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Rastogi have a primary and secondary task to be parallel. Motivation to combine would be to sync the primary and secondary task.
As per claim 2 Robatmili, Kitano, Pulshipher and Rastogi disclose a method of claim 1 detailed above.
Robatmili disclose “where generating, at the control circuit, one or more operation instructions”
[0064] central controller may generate multiple tasks): the data processor unit (fig. 4, block 402 iteration space splitter controller ITSS central controller and second execution units [0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel;
Robatmili does not explicitly disclose “generating the operation instructions in response to job information in the request.”
However, Kitano disclose “generating the operation instructions in response to job information in the request.” [0083] “When the job receiver 41 receives a job, a request is given to the task generator 42 to divide the job into tasks;”
Robatmili and Kitano are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Kitano control circuit to create one or more instruction in response of the job request. Motivation to combine be having a direct line of communication.
As per claim 20 Robatmili discloses:
A non-transitory computer readable storage medium comprising code which when implemented on a processor causes the processor to: [0104] “the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium.”
generate one or more operation instructions to control processing of the primary and/or secondary workloads at first and/or second execution units
initiate, at the first execution unit, processing of the primary workload and
initiate, at the second execution unit….
[0004] “initializing, by the central controller of the processor or processor core…...assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”
Robatmili does not explicitly disclose “
obtain a request, the request received by a control circuit from a host processor unit, for a data processor to perform processing of first and second processing jobs;
generate, responsive to the request, a primary workload for the first processing job, and a secondary workload for the second processing job:
……. processing of the secondary workload in parallel with the processing of the primary workload in accordance with the operation instructions.”
However, Kitano does disclose “obtain a request, the request received by a control circuit from a host processor unit, for a data processor ….;
generate, responsive to the request, a primary workload for the first processing job, and a secondary workload for the second processing job [0054] “The job client 12 feeds a job i.e., processing request which is to be executed by the information processing apparatus 11” [0083] “When the job receiver 41 receives a job, a request is given to the task generator 42 to divide the job into tasks;”
Robatmili and Kitano are combinable because they are in similar fields which is allocating task within a data unit.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of Kitano to have control circuit to receive a request by the control circuit from the host processor unit to then generate a response based on the request received to perform the first and second processing job. Motivation to combine would be properly perform the first and second processing job after generating a response from the circuit control.
Robatmili in view of Kitano do not explicitly disclose:
“…. perform processing of first and second processing jobs”
However, Pulshipher disclose:
to perform first and second processing jobs “col. 27, ll. 36-37 receiving a work request, said work request specifying a first job and a second job”.
Robatmili and Pulshipher are both combinable because they are in similar fields which is a request that define tasks within a computing environment.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili, with the teaching of the Kitano and with the teaching of Pulshipher to receiving a request and to perform first and second processing jobs. Motivation to combine would be directing the request from data processing unit receive and perform first and second processing jobs.
Robatmili in view of Kitano, and in view of Pulshipher does not explicitly disclose “……. processing of the secondary workload in parallel with the processing of the primary workload in accordance with the operation instructions”
However, Rastogi disclose primary tasks and secondary tasks executing in parallel ([0022] primary tasks and secondary tasks and [0024] execution of the primary tasks and secondary tasks may be parallelized).
Robatmili and Rastogi are combinable because they in similar fields which is processing data in parallel.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Rastogi to have a primary and secondary task to be parallel in accordance with the operation instruction. Motivation to combine would be to sync the primary and secondary workload.
Claims 3, 4, 9 and 13 are rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Pulshipher (US 7,117,500) in view of, Rastogi (US 2011/0321051) in view of Mitsugu Nagoya (JP 4087427 B2).
As per claim 3 Robatmili Kitano, Pulshipher and Rastogi disclose a method of claim 1 detailed above.
Robatmili disclose “where generating, at the control circuit, one or more operation instructions” [0004] assigning, by the central controller of the processor or processor core,
Robatmili does not explicitly disclose “generating the operation instructions based on or in response to system information in storage “
However, Nagoya, disclose an operation management within a system “data processing system may further include an operation management unit that manages an operation status of the plurality of data holding units,”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to generate one or more operation instruction from the control circuit to then response based on the unit in the system information in storage. Motivation to combine would be store the operations and the system information in a dedicated management system.
As per claim 4 Robatmili disclose a method of claim 3 detailed above.
Robatmili disclose a “first execution unit and/or second execution unit” and “processing workloads” [0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”
Robatmili does not explicitly disclose “updating, with the first execution unit and/or the second execution unit, the system information in storage in response to processing the respective workloads.”
However, Nagoya disclose an operation management within a system and within the operation management is an operation monitoring server “When the operation management unit updates the database held in the data holding unit, the waiting data holding unit is in operation. After storing the update data of the database held by any one of the data holding units, “and “…The operation status column 113 is updated by the operation monitoring server 110 every time the operation status of the communication control devices 10a, 10b…”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to update the first and/or second execution unit in response to processing the workloads and then having that information in storage. Motivation to combine would be store the operations and the system information in a dedicated management system, and updating the units within the management system.
As per claim 9 Robatmili disclose a method of claim 8 detailed below.
Robatmili does not explicitly disclose “where the system information in storage is indicative of a status of at least one component of the data processor unit.”
However, Nagoya, disclose an operation management within a system “data processing system may further include an operation management unit that manages an operation status of the plurality of data holding units,”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to show the status of at least one component of the data processor unit. Motivation to combine would be store the system information in a management system and show the status of the units.
As per claim 13 Robatmili disclose a method of claim 12 detailed below.
Robatmili disclose a “first execution unit and/or second execution unit” [0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”
Robatmili does not disclose “based on or in response to the operational status of the first execution unit and/or the second execution unit, issuing further operation instructions to the first execution unit and/or the second execution unit.”
However, Nagoya disclose an operation management unit “When the operation management unit detects that the operating data holding unit is in an inoperable state …. The operation may be switched to the data holding unit in standby. As a result, even if one of the data holding units is stopped due to a failure or the like...” and “The operational status includes, for example, “in operation”, “standby”, “failure”, “data updating”, and the like. The operation status column 113 is updated by the operation monitoring server 110 every time the operation status of the communication control devices 10a, 10b...”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to determine based on that status of the operational management to give further instruction to the first and/or second execution unit. Motivation to combine would be to properly give instruction to the first and/or second execution unit based on the operational response.
Claim 5 are rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Pulshipher (US 7,117,500) in view of, Rastogi (US 2011/0321051) in view of Haefele et al. (US 20210194720)
As per claim 5 Robatmili, Kitano, Pulshipher and Rastogi disclose a method of claim 1 detailed above.
Robatmili disclose “where processing, at the second execution unit, the secondary workload…. in accordance with the operation instructions” [0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel.
Robatmili does not explicitly disclose “where processing, at the second execution unit, the secondary workload in parallel with the primary workload in accordance with the operation instructions comprises: processing tasks of the secondary workload at the second execution unit at a different rate in comparison to the rate at which the first execution unit processes tasks of the primary workload.” As required by the claim.
However, Rastogi does disclose:
“where processing, at the second execution unit, the secondary workload in parallel with the primary workload in accordance with the operation instructions” ([0022] primary tasks and secondary tasks and [0024] execution of the primary tasks and secondary tasks may be parallelized).
Robatmili and Rastogi are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Rastogi have a primary and secondary task to be parallel. Motivation to combine would be to sync the primary and secondary task.
Robatmili in view of Rastogi does not explicitly disclose “processing tasks of the secondary workload at the second execution unit at a different rate in comparison to the rate at which the first execution unit processes tasks of the primary workload.”
However, Haefele disclose “processing tasks of the secondary workload at the second execution unit at a different rate in comparison to the rate at which the first execution unit processes tasks of the primary workload” [0011] “the first task program runs on a first execution unit and the second task program runs on a second execution unit in the control unit.” [0016] “first task program and the second task program advantageously have different cycle times, a cycle time of the first task program being less than the cycle time of the second task program”
Robatmili and Haefele are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Haefele to compare or distinguish the processing task of the secondary workload rate based on the primary workload. Motivation to combine would be to compare second workload of the secondary execution unit rate to the first workload of the first execution unit.
Claims 6-7 are rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili et al (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Pulshipher (US 7,117,500) in view of, Rastogi (US 2011/0321051), in view of Haefele et al. (US 20210194720) in view of Alla et al. (US 2021/0200255 A1)
As per claim 6 Robatmili, Kitano, Pulshipher, Rastogi, and Haefele disclose a method of claim 5 detailed above.
Robatmili disclose “first and second execution units to process the workloads. “([0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores),
Robatmili does not explicitly disclose “where the different rate is a reduced rate, and where the second execution unit processes tasks of the secondary workload at a reduced processing speed or reduced clock speed”
However, Alla disclose “where the different rate is a reduced rate, and where the second execution unit processes tasks of the secondary workload at a reduced processing speed or reduced clock speed” [0011] "configuring the upper clock rate of the GPU based on the second request may include operations, features, means, or instructions for reducing the upper clock rate of the GPU based on the second workload type” [0106] "In some examples, the clock rate manager 630 may reduce the upper clock rate of the GPU 605 based on the second workload type. "
Robatmili and Alla are combinable because there are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Alla to reduce the processing speed or reduced clock speed of the secondary execution units. Motivation to combine would be to properly reduce the speed on the secondary task load.
As per claim 7 Robatmili, Kitano, Pulshipher, Rastogi, and Haefele disclose a method of claim 5 detailed above.
Robatmili disclose “first and second execution units to process the workloads. “([0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores).
Robatmili does not explicitly disclose “where the tasks of the secondary workload are issued to the second execution unit at a different frequency in comparison to the frequency that the tasks of the primary workload are issued to the first execution unit.”
However, Alla does explicitly disclose ““where the tasks of the secondary workload are issued to the second execution unit at a different frequency in comparison to the frequency that the tasks of the primary workload are issued to the first execution unit.” [0026] “may adaptively perform different processing operations (e.g., process different workload batches) at different upper clock rates (e.g., at different operating frequency, different speeds, etc.) according to workload types”
Robatmili and Alla are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Alla to have Alla teaching of the use of the upper clock that can calculate the frequency of the workload that is given, which would have been obvious compare the different workloads that is assigned to each unit. Motivation to combine be to distinctly compare the primary and secondary task/workloads that are at different frequency.
Claims 8 and 10-12 are rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over, in view of, Robatmili et al. (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Pulshipher (US 7,117,500) in view of, Rastogi (US 2011/0321051) in view of Mitsugu Nagoya (JP 2087427 B2), and in view of Lee et al. (US20160321102 A1)
As per claim 8 Robatmili Kitano, Pulshipher and Rastogi disclose a method of claim 1 detailed above.
Robatmili disclose a “first and/or second workload/task” [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”
Robatmili does not explicitly disclose “analysing system information during processing of the primary workload and/or the secondary workload; and in response to the analysis, updating system information in the management unit.”
However, Nagoya disclose an operation management within a system “data processing system may further include an operation management unit that manages an operation status of the plurality of data holding units,” “When the operation management unit updates the database held in the data holding unit, the waiting data holding unit is in operation. After storing the update data of the database held by any one of the data holding units,”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to have the primary and/or secondary workload that is processing then updated in storage. Motivation to combine would be update and store the system information in a dedicated management unit.
Robatmili in view of Nagoya does not explicitly disclose “analysing system information”
However, Lee disclose a scheduler [0135] “…. the scheduler 420, which is run in the first core (or second core C2) and which monitors the workload of the task executed in the first core (or second core C2),”
Robatmili and Lee are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Lee to analyze the system information and based on the that analysis that information can but update to the management unit. Motivation to combine would be fully monitor the workloads and based of the analysis update to the management unit.
As per claim 10 Robatmili Kitano, Pulshipher, Rastogi, Nagoya and Lee disclose a method of claim 8 detailed above.
Robatmili does not explicitly disclose “where the system information in storage comprises real-time or current system information.”
However, Lee disclose a scheduler timer [0071] “FIGS. 1 and 3, the scheduling timer 423 included in the scheduler 420 may generate a scheduling tick ST1 at regular intervals and may send the scheduling tick”
Robatmili and Lee are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Lee to analyze the system information and based on the that analysis that information can deploy a scheduler timer which would indicate the time of the processing of the workloads. Motivation to combine would be fully monitor and indicate the time the workloads was process.
Robatmili in view of Lee does not explicitly disclose “system information in storage”
However, Nagoya, disclose an operation management within a system “data processing system may further include an operation management unit that manages an operation status of the plurality of data holding units,”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to have the system information in storage. Motivation to combine would be to dedicated management unit to store the system information.
As per claim 11 Robatmili Kitano, Pulshipher, Rastogi, Nagoya and Lee disclose a method of claim 8 detailed above.
Robatmili disclose a “processing primary and/or secondary workload” [0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”
Robatmili does not explicitly disclose “analysing, with an analysis unit, the system information in storage during processing of the primary workload and/or the secondary workload.”
However, Nagoya, disclose an operation management within a system “data processing system may further include an operation management unit that manages an operation status of the plurality of data holding units,”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to have the primary and/or secondary workload that is processing store in the storage. Motivation to combine would be store the system information in a dedicated management unit.
Robatmili in view of Nagoya disclose explicitly disclose “analysing”
However, Lee disclose a scheduler [0135] “…. the scheduler 420, which is run in the first core (or second core C2) and which monitors the workload of the task executed in the first core (or second core C2),”
Robatmili and Lee are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Lee to analyze the system information and based on the that analysis that. Motivation to combine would be fully monitor the workloads during the process in the management unit.
Under the broadest reasonable interpretation Lee does not explicitly state “analysis unit” however Lee disclose a scheduler that monitors that is within a unit. Which is basically encompassing the functionality of “analysis unit”.
As per claim 12 Robatmili Kitano, Pulshipher, Rastogi, Nagoya and Lee disclose a method of claim 11 detailed above.
Robatmili disclose a “first execution unit and/or second execution unit” and “primary and/or secondary workload” [0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”
Robatmili does not disclose “determining an operational status of the first execution unit and/or the second execution unit based on or in response to the analysis of the system information in storage during processing of the primary workload and/or the secondary workload.”
However, Nagoya, disclose an operation management within a system “data processing system may further include an operation management unit that manages an operation status of the plurality of data holding units,”
Robatmili and Nagoya are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Nagoya to determine the operational status of the first and/or secondary unit. Motivation to combine would be to properly display status of the unit based on the determination.
Robatmili in view of Nagoya does not explicitly disclose “analysis”
However, Lee disclose a scheduler [0135] “…. the scheduler 420, which is run in the first core (or second core C2) and which monitors the workload of the task executed in the first core (or second core C2),”
Robatmili and Lee are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Lee to make analyze the system information. Motivation to combine would be fully monitor the workloads.
Claims 14 and 15 are rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili et al. (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Pulshipher (US 7,117,500), in view of Rastogi (US 2011/0321051), in view of Cardenas et al. (US 2023/0118846 A1)
As per claim 14 Robatmili, Kitano, Pulshipher and Rastogi disclose a method of claim 1 detailed above.
Robatmili does disclose processing a first and secondary execution unit ([0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel).
Robatmili does not explicitly disclose “processing the primary and/or secondary workload based on or in response to an estimate of the effect that processing the primary and/or secondary workloads would have on system resources.”
However, Rastogi disclose “the primary and/or secondary workload and workload being parallel” ([0022] primary tasks and secondary task and [0024] execution of the primary tasks and secondary tasks may be parallelized).
Robatmili and Rastogi are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Rastogi to have a first and secondary units with their assigned primary and secondary workloads. Motivation to combine would be to have each workload assigned to a unit.
Robatmili in view of Rastogi does not explicitly disclose “in response to an estimate of the effect that processing the primary and/or secondary workloads would have on system resources.”
However, Cardenas, does disclose “in response to an estimate of the effect that processing the primary and/or secondary workloads would have on system resources.” [0015] “…workload failures may still impact an overall performance and/or latency of the computing system because resources used…”
Robatmili and Cardenas are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Cardenas to predict or estimate the workloads would have on the system. Motivation to combine would be to reveal the effect of processing the primary and/or secondary workload would have on the computer system.
As per claim 15 Robatmili, Kitano, Pulshipher, Rastogi, and Cardenas disclose a method of claim 14 detailed above.
Robatmili Kitano, Pulshipher and Rastogi does not explicitly disclose “executing the primary workload and/or the secondary workload to meet an operation target, a resource usage target and/or a resource budget.”
However, Cardenas does disclose “to meet an operation target, a resource usage target and/or a resource budget” [0050] “In an example, method 300 includes determining, based on the monitored resource usage, the reduced first amount of the resources at block 330.”
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Cardenas to execute a primary and/or secondary workload to meet a resource usage. Motivation to combine would be to minimize the of processing the primary and/or secondary workload would have on the computer system based on the resource usage.
Claim 16 is rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Pulshipher (US 7,117,500) in view of, Rastogi (US 2011/0321051), in view of McEwen (US 2017/0230376 A1)
As per claim 16 Robatmili, Kitano, Pulshipher and Rastogi disclose a method of claim 1 detailed above.
Robatmili, Kitano, Pulshipher and Rastogi does not explicitly disclose “where processing, at the first execution unit, the primary workload in accordance with the operation instructions and/or processing, at the second execution unit, the secondary workload in parallel with the primary workload in accordance with the operation instructions is based on the processing phase of the workload.”
However, McEwen does disclose “…processing phase of the workload “[0022] “The requests may be analyzed to determine whether to schedule tasks associated with the requests in a queue for processing during a first processing phase (e.g., a period of time).”
Robatmili and McEwen are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the McEwen to process the phase of the workload based on the second execution unit and the secondary workload that is parallel with the primary workload. Motivation to combine would be to sync the primary and secondary workload based on their performance.
Claims 17 is rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili (US 2016/0292012) in view of, Kitano (US 2016/0014198) in view of, Rastogi (US 2011/0321051).
As per claim 17 Robatmili discloses:
A data processor unit (fig. 4, block 402 iteration space splitter controller ITSS central controller and [0004] the central controller of the processor)
“first execution unit and/or second execution unit” and “primary and/or secondary workload” [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores”
one or more operation instructions to control the processing of the primary and/or secondary workloads; a first execution unit to execute the primary workload in accordance with the operation instructions therefor second execution units [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel;”
a first execution unit to execute the primary workload in accordance with the operation instructions therefor [0004] “assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel;”
Robatmili does not explicitly disclose “a control circuit configured to receive, from a host processor unit, a request for the data processor unit to perform first and second processing jobs and, in response to the request, to generate:
a primary workload comprising one or more tasks for the first processing job;
a secondary workload comprising one or more tasks for the second processing job;
a second execution unit to execute the secondary workload in parallel with the primary workload and in accordance with the operation instructions therefor.”
However, Kitano does disclose “a control circuit configured to receive, from a host processor unit, a request for the data processor unit to perform first and second processing jobs and, in response to the request, to generate:
a primary workload comprising one or more tasks for the first processing job;
a secondary workload comprising one or more tasks for the second processing job;” [0054] “The job client 12 feeds a job i.e., processing request which is to be executed by the information processing apparatus 11” [0083] “When the job receiver 41 receives a job, a request is given to the task generator 42 to divide the job into tasks;”
Robatmili and Kitano are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of Kitano to have control circuit to receive a request from a data processing unit which then can generate based on the request received to create a workload for each task and within that request then assign a task to a primary or first secondary processing job. Motivation to combine would be precisely assign a task/workload to a primary or secondary processing job after generating a response from the circuit control for task/workload that was requested.
Robatmili in view of Kitano does not explicitly disclose “a second execution unit to execute the secondary workload in parallel with the primary workload and in accordance with the operation instructions therefor”
However, Rastogi disclose primary tasks and secondary tasks executing in parallel ([0022] primary tasks and secondary tasks and [0024] execution of the primary tasks and secondary tasks may be parallelized).
Robatmili and Rastogi are combinable because they in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of the Rastogi have a primary and secondary task to be parallel. Motivation to combine would be to sync the primary and secondary task.
Claim 18 is rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili et al. (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Rastogi (US 2011/0321051) in view of Saeed et al. (US 2021/0304489 A1), in view of Venkataraman et al. (US 2020/0073714 A1)
As per claim 18 Robatmili Kitano, and Rastogi disclose apparatus of claim 17 detailed above.
Robatmili does disclose “first and second execution units to process the workloads ([0004] assigning, by the central controller of the processor or processor core, the first task to execute by a first processor or processor core and the second task to execute by a second processor or processor core in parallel and fig. 2 the processor has multiple processor cores),”
Robatmili does not disclose “where a first execution unit comprises an execution engine and where the second execution unit comprises a neural engine.”
However, Saeed disclose an execution unit as stated in the claim [0321] “FIG. 6, each shader core of the graphics processor 60 includes an appropriate programmable execution unit (execution engine) 65 that is operable to execute graphics shader programs for execution threads to perform graphics processing operations.”
Robatmili and Saeed are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of Saeed to have the first execution unit to have an execution engine. Motivation to combine would be to have a dedicated engine to the first execution unit.
Robatmili in view of the Saeed does explicitly disclose a “neural engine” as required by the claim,
However, Venkataraman does disclose a “neural engine” [0002] “graphics processing units (GPUs), which may include multiple GPU cores or execution units, neural engines optimized for accelerating neural network operations, and other types of processors” [0056] “The GPU 2230 and neural engine 2235 can perform operations at the request of application processors within the processor complex 111.”
Robatmili and Venkataraman are combinable because they are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of Venkataraman to have the second execution unit to have a neural engine. Motivation to combine would be to have a dedicated engine to the second execution unit.
Claim 19 is rejected in view of is rejected under 35 U.S.C. 103 as being unpatentable over Robatmili et al. (US 2016/0292012), in view of, Kitano (US 2016/0014198) in view of, Rastogi (US 2011/0321051) in view of, Pennala et al. (US20190056955 A1)
As per claim 19 Robatmili Kitano, and Rastogi disclose apparatus of claim 17 detailed above.
Robatmili does disclose “data processor unit” [0064] central controller may generate multiple tasks)
Robatmili does not explicitly disclose “where the data processor unit comprises one or more shader cores, each shader core having two or more execution units”
However Pennala disclose “where the data processor unit comprises one or more shader cores, each shader core having two or more execution units” [0055] “a graphics processing unit (and e.g. each graphics processing unit) of the one or more graphics processing units includes one or more execution units, such as one or more shader (programmable processing) cores.…plural graphics processing units, different graphics processing units may have different sets of one or more execution units, and they may have one or more other execution units in addition to one or more shader cores…graphics processing unit includes a plurality of shader cores…”
Robatmili and Pennala are combinable because there are in similar fields.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed inventions to modify the teaching Robatmili and with the teaching of Pennala have a data processing unit that comprise one of more shader cores and each shader core having two or more execution units. Motivation to combine would be to dedicate each shader core to two or more execution units.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
You, Yo et al. (US 20240184632 A1) disclose an apparatus, a method, and a computer program product. The apparatus includes at least one processor; and at least one non-transitory memory including computer program code; wherein the one or more task group types comprise one or more of: a first at least one task group which enables executing a workflow comprising one or more tasks in the first at least one task group in a synchronous mode; and a second at least one task group which enables executing a sub-workflow or another workflow including the at least one task in the second at least one task group in an asynchronous mode.
Balle, Susanne et al. (US 20180024860 A1) disclose a historical resource utilization phases of the workloads. Further, the orchestrator server is to determine, as a function of the historical resource utilization phases and as the workloads are performed, predicted resource utilization phases for the workloads.
Robertson, Don et al. (US 8826280 B1) disclose monitoring a task queue in real-time is disclosed. A request is received for task queue information regarding the task queue. The task queue is queried in real-time to obtain the requested task queue information. The obtained task queue information is provided.
Fuller, Alfred R. K. (US 8826284 B1) disclose a server system having one or more processors and memory receives, from a client, a request to perform a first task. The server system determines whether a first slot in a primary task queue having a plurality of slots is available.
Kim; Lok Won (US 20250077277 A1) disclose a neural network processing unit (NPU) includes a processing element array, a SRAM memory configured to store at least one data of the artificial neural network model processed in the processing element array; and an NPU scheduler configured to control the processing element array.
Zisman; Nitzan et al. (US 12175285 B1) disclose a task distribution technique for distributing the processing task to a group of processing units. The scheduler circuit is configured to implement the selected task distribution technique to select, from the group of processing units, a target processing unit for performing the processing task.
Kim; Hongyun (US 20240330085 A1) disclose a command processor generates a plurality of task descriptors describing neural network model tasks based on the neural network model data, and distributes the plurality of task descriptors to the neural processors.
Poornachandran; Rajesh et al. (US 20240134707 A1) disclose an apparatus, articles of manufacture, and methods for managing processing units. An example apparatus includes first processor circuitry to implement a central processing unit and second processor circuitry to perform at least one of many operations.
Xu, Leslie et al. (US 20240126599 A1) disclose a systems, apparatus, articles of manufacture, and methods are disclosed to manage workloads for an operating system wherein it causes programmable circuitry to cause a task of a workload to be executed with a first processor core configuration; cause the task to be executed with a second processor core configuration; compare a first performance metric of the execution of the task with the first processor core.
Pelster, David J et al. (US 20240094939 A1) disclose a systems and methods are provided for dynamically changing the operating clock frequency of a circuit. Control circuitry determines a first workload value for a circuit operating at a first clock frequency.
WU, Linyang et al. (US 20200012521 A1) disclose a task parallel processing method, a device, a system, a storage medium and computer equipment, which are capable of distributing and regulating tasks to be executed according to a task directed acyclic graph, and may thereby realize task parallelism of a multi-core processor and improve the efficiency of data processing.
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/A.A./Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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