Prosecution Insights
Last updated: July 17, 2026
Application No. 18/474,699

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §103§112
Filed
Sep 26, 2023
Priority
Apr 07, 2023 — RE 10-2023-0046395
Examiner
NELSON, JACOB THEODORE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
121 granted / 138 resolved
+19.7% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
22 currently pending
Career history
168
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
83.9%
+43.9% vs TC avg
§102
5.8%
-34.2% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 138 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of claims 1 - 16 in the reply filed on 03/05/2026 is acknowledged. The traversal is on the ground(s) that no serious search burden is present. This is not found persuasive because applicant’s arguments do not address the burden explained in the restriction requirement and the arguments do not specifically point out any error in examiner's reasoning. The requirement is still deemed proper and is therefore made FINAL. Claims 17 - 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/05/2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 09/26/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The abstract of the disclosure is objected to because the abstract contains information already provided the title. Specifically, the abstract states “A semiconductor device according to some example embodiments includes:…”. The title already contains the information that the invention is a semiconductor device. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2 - 5are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites the limitation "...are between " in line 5 of claim 2. There is insufficient antecedent basis for this limitation in the claim. Claim 2 states “…wherein the second element isolation layer includes a first portion surrounded by the first element isolation layer and a second portion that extends… and the second pad are between second portions of the second element isolation layer”. The claim introduces a singular second portion and then states that the second pad is between a plurality (at least two) second portions. This makes it unclear if the second portions being referred to is the singular second portion introduced earlier, if the second portions are a separate part of the device, or if the second portions include multipole of the second element isolation layers each containing either one second portion or multiple second portions. As there are multiple interpretations, the lack of antecedent basis results in the claim being indefinite. For the purpose of compact prosecution, examiner is interpreting claim 2 as stating “wherein the second element isolation layer includes a first portion… and a plurality of second portions that extends from the first portion… and the first pad and the second pad are between the plurality of second portions of the second element isolation layer”, as this interpretation appears to match the specification and drawings and allows for the pads to be between two objects which are both second portions of the isolation layer. Claims 3 – 5 depend on claim 2 and inherit all of its deficiencies. Claims 3 – 5 are rejected as being indefinite. A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 10 recites the broad recitation "a maximum width... or more", and the claim also recites "a maximum width... is about 3.8 nm” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims. Further, claim 10 is unclear if the maximum is 3.8 nm or if there is no maximum width, as the phrase after “or more” would mean that 3.8 nm is not an actual maximum and that because no upper bound is stated, the maximum is infinite. For the purpose of compact prosecution, examiner is interpreting claim 10 as stating “…a maximum width of the second element isolation layer is about 3.8 nm or less” as this interpretation has the upper bound, or the maximum width, of 3.8 nm and does not allow for a larger width beyond the maximum. Claim 13 states “…further comprising a word line capping layer on the word line, wherein the first pad is between word line capping layers”. There is insufficient antecedent basis for the limitation “word line capping layers”, as claim 13 only introduces one word line capping layer present on the word line, then states that there are multiple word line capping layers later in the claim. It is unclear if there is only one word line capping layer with multiple parts that the first pad is located between or if there are multiple word line capping layer that are separate each other that the first pad is located between. As there are multiple interpretations present, claim 13 is rejected as being indefinite. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 7 – 9, and 11 - 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200402839 A1 hereinafter Im in further view of US 20070155150 A1 hereinafter Kim. For claim 1, Im teaches a semiconductor device comprising: a substrate (Im, fig. 6I numeral 100) that includes an active region (fig. 6I numeral 101) between element isolation layers (fig. 6I numeral 103; fig. 3A – 3B numeral 103); a word line that overlaps the active region and extends in a first direction (fig. 5 numeral WL; fig. 6I numeral WL); a bit line that overlaps the active region and extends in a second direction crossing the second direction (fig. 5 numeral BL; fig. 6I numeral BLS); a buried contact connected to the active region (fig. 6I numeral LCP); and a landing pad contacted to the buried contact (fig. 6I numeral LP), wherein each of the element isolation layers includes a first element isolation layer (fig. 4A – 4B show detailed versions of the element isolation layers; fig. 4A – 4B numeral 123) and a second element isolation layer inside the first element isolation layer (fig. 4A – 4B numeral 133). Im is silent regarding first pad between and connecting the active region and the bit line and a second pad between the connecting the active region and the buried contact. Im does teach that the bit line can include a direct contact pattern that connects the bit line to the active region (fig. 6I numeral 221) and the direct contact pattern is between the first and second element isolation layers (fig. 6I shows the contact pattern 221 between element isolation layers shown by numeral 123). Kim teaches a semiconductor device (Kim, fig. 12) that includes a buried contact (fig. 12 numeral 87), a bit line (fig. 12 numeral 71) that overlaps an active region (fig. 12 numeral 52) that is within a substrate (fig. 12 numeral 51), and isolation layers that the active region is between (fig. 12 numeral 53). Kim also teaches a first pad that is between and connects the bit line and the active region (fig. 12 numeral 57 and 57S) and a second pad that is between and connects the active region and the buried contact (fig. 12 numeral 56 and 56S). The pads are shown to be between the element isolation layers (fig. 12 shows pads 57, 57S and 56, 56S between element isolation layers 53). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the pads in Kim with the bit lines and buried contacts in Im in order to reduce contact resistance between the bit line, the buried contact, and the active region (Kim, Par. [0005]). For claim 7, Im and Kim teach all of claim 1. Im also teaches the first element isolation layer and the second element isolation layer include different materials (Im, Par. [0043 – 0044] teach the first element isolation layer 123 being polycrystalline silicon and second element isolation layer 131 being silicon oxide). For claim 8, Im and Kim teach all of claim 1. Kim also teaches the widths of the first pad (Kim, fig. 12 numeral 57 and 57S) and the second pad (fig. 12 numeral 56 and 56S) are greater than a width of an uppers surface of the active region (fig. 12 shows the uppers surface of the active region 52 having a width less than the widths of the pads). For claim 9, Im and Kim teach all of claim 1. Im also teaches the element isolation layers having a decreasing width from an upper surface of the element isolation layers to a lower surface of the element isolation layers (Im, fig. 6I shows element isolation layers shown by numeral 123 decreasing in width from the upper surface to the bottom surface forming a truncated shape; fig. 4A and 4B show the decreasing width from the top of the element isolation layers to the bottom of the element isolation layers; Par. [0028]). For claim 11, Im and Kim teach all of claim 1. Im also teaches the plurality of active regions extend in a third direction oblique to the first direction and the second direction (Im, fig. 5 shows first and second directions D1 and D2 with active regions 101 extending in a direction oblique to D1 and D2), the plurality of active regions are spaced apart from each other in parallel along the first direction and the third direction (fig. 5 shows active regions 101 spaced apart in a third direction oblique to D1 and also along D1), and both ends portions of the plurality of active regions adjacent along the first direction are aligned so that both ends portions coincide with each other (fig. 5 shows end portions of adjacent active regions 101 to be next to each other along the first direction D1). Examiner is interpreting coincide to mean to occupy similar or equivalent positions on a scale or in a series. Figure 5 of Im shows the active regions in a series and the adjacent end portions of the active regions occupy similar positions in the series along the first direction D1. For claim 12, Im and Kim teach all of claim 11. Kim also teaches active regions extending in a third direction (Kim, fig.4 numeral 52) that is oblique to a first direction (fig. 4 in the horizontal direction) and a second direction (fig. 4 in the vertical direction) and that the first pad and the second pad are separated in the third direction (fig. 4 shows multiple second pads 56H and first pads 57H separated in the third direction). Allowable Subject Matter Claims 14 - 16 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 14’s “…and a pad spacer that is between the first pads and the protruding portion of the second element isolation layer and between the second pads and the protruding portion of the second element isolation layer…”. Im and Kim do not appear to teach a protruding portion of the second element isolation layer and wherein a pad spacer is between the first pads and the protruding portion of the second element isolation layer. Claim 15 – 16 are allowed primarily as being dependent on an allowable base claim. Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”. Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. For claim 6, Im and Kim do not appear to teach the first pad and the second pad overlapping the first element isolation layer in a direction perpendicular to the substrate while also the first pad and the second pad are not overlapping the second element isolation layer in the direction perpendicular to the substrate. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.T.N./Examiner, Art Unit 2815 /MONICA D HARRISON/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Sep 26, 2023
Application Filed
Apr 23, 2026
Non-Final Rejection mailed — §103, §112
May 22, 2026
Interview Requested
May 29, 2026
Examiner Interview Summary
May 29, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+7.9%)
2y 10m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 138 resolved cases by this examiner. Grant probability derived from career allowance rate.

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