DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device and Method of Manufacturing a Semiconductor Device that Performs a Heat Treatment Causing the Titanium Film and the Semiconductor Substrate to React With Each Other.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzawa (US 2020/0051852).
Regarding Claim 1, Suzawa discloses a semiconductor device (trench-gate IGBT [0059] Fig 1), comprising: a semiconductor substrate (semiconductor substrate 10 [0059]) having a main surface (shown in annotated Fig 1), the main surface (shown in annotated Fig 1) having a recess (shown in annotated Fig 1) formed therein;
a device structure (shown in annotated Fig 1) provided at the main surface (shown in annotated Fig 1) of the semiconductor substrate (10);
an interlayer insulating film (HTO film 11 [0072] and BSPG film 12 [0071]) provided on the main surface (shown in annotated Fig 1) of the semiconductor substrate (10) and covering the device structure (shown in annotated Fig 1);
a contact hole (contact hole 14 [0062]) that, in a depth direction (vertical direction shown in Fig 1) of the semiconductor device (IGBT shown in Fig 1), penetrates through the interlayer insulating film (11 and 12) to reach the main surface (shown in annotated Fig 1) of the semiconductor substrate (10), thereby exposing a portion of the device structure (shown in annotated Fig 1),
the contact hole (14) having: a side wall, and a bottom that is configured by the recess (shown in annotated Fig 1) at the main surface (shown in annotated Fig 1) of the semiconductor substrate (10);
a barrier metal (barrier metal 15 [0073]), including a titanium film (titanium film [0080]) provided along the side wall of the contact hole (14), and a titanium nitride film (titanium nitride film [0080]) that is stacked on the titanium film (titanium film) and formed on the bottom of the contact hole (14);
a titanium silicide film (the titanium film and titanium nitride film of the barrier metal 15 are caused to react with each other by annealing to form a titanium silicide ohmic contact [0009]) provided in the semiconductor substrate (10), along an inner wall of the recess (shown in annotated Fig 1) of the semiconductor substrate (10);
a tungsten film (tungsten film 16 [0065]) provided in the contact hole (14), on the barrier metal (14); and
a metal electrode (emitter electrode 17 [0059]) containing aluminum (aluminum [0073]), provided on the interlayer insulating film (11 and 12) and the tungsten film (16),
wherein in the depth direction (vertical direction shown in Fig 1) of the semiconductor device (10), an upper surface of the titanium nitride film (top portion of barrier metal 15) at the bottom of the contact hole (14) is closer to the metal electrode (17) than is the main surface (shown in annotated Fig 1) of the semiconductor substrate (10).
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Regarding Claim 3, Suzawa discloses the limitations of claim 1 as explained above. Suzawa further discloses
wherein the titanium nitride film (top portion of barrier metal 15) has an indentation (shown in annotated Fig 1) formed at the upper surface thereof in a bottom corner of the contact hole (14).
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Regarding Claim 4, Suzawa discloses a method of manufacturing (method [0056]) a semiconductor device (trench-gate IGBT [0059] Fig 1), the method (method) comprising:
preparing a semiconductor substrate (semiconductor substrate 10 [0059]) having a main surface (shown in annotated Fig 1);
forming a device structure (shown in annotated Fig 1) at the main surface (shown in annotated Fig 1) of the semiconductor substrate (10);
forming an interlayer insulating film (HTO film 11 [0072] and BSPG film 12 [0071]) on the main surface (shown in annotated Fig 1) of the semiconductor substrate (10), the interlayer insulating film (11 and 12) covering the device structure (shown in annotated Fig 1);
forming a contact hole (contact hole 14 [0062]) from an upper surface of the interlayer insulating film (11 and 12), to penetrate through the interlayer insulating film (11 and 12) in a depth direction (vertical direction shown in Fig 1) of the semiconductor device (10) and to form a recess (shown in annotated Fig 1) at the main surface (shown in annotated Fig 1) of the semiconductor substrate (10), the contact hole (14) exposing a portion of the device structure (shown in annotated Fig 1), and having: a side wall, and a bottom that is configured by the recess (shown in annotated Fig 1) at the main surface (shown in annotated Fig 1) of the semiconductor substrate (10);
sequentially forming a titanium film (titanium film [0080]) and a titanium nitride film (titanium nitride film [0080]), as a barrier metal (barrier metal 15 [0073]), along an inner wall of the contact hole (14);
performing a heat treatment thereby causing the titanium film at the bottom of the contact hole and the semiconductor substrate to react with each other (the titanium film and titanium nitride film of the barrier metal 15 are caused to react with each other by annealing (heat treatment) to form a titanium silicide ohmic contact [0009]), thereby forming a titanium silicide film (titanium silicide) in the semiconductor substrate (10) along an inner wall of the recess (shown in annotated Fig 1);
performing a chemical vapor deposition (chemical vapor deposition (CVD) [0010]) thereby depositing a tungsten film (tungsten film 16 [0065]) on the barrier metal (tungsten film 16 [0065]) in the contact hole (14), thereby embedding the tungsten film (16) in the contact hole (14); and
forming a metal electrode (emitter electrode 17 [0059]) containing aluminum (aluminum [0073]), on the interlayer insulating film (11 and 12) and the tungsten film (tungsten film 16 [0065]), wherein after the heat treatment (annealing [0009]), in the depth direction (vertical direction shown in Fig 1) of the semiconductor device (trench-gate IGBT [0059] Fig 1), an upper surface of the titanium nitride film (titanium film [0080]) at the bottom of the contact hole (14) is closer to the interlayer insulating film (11 and 12) than is the main surface (shown in annotated Fig 1) of the semiconductor substrate (10).
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Regarding Claim 5, Suzawa discloses the limitations of claim 4 as explained above. Suzawa further discloses
wherein forming the titanium nitride film (titanium nitride film [0080]) includes depositing the titanium nitride film (titanium nitride film [0080]) having a thickness obtained by adding, to a thickness of the titanium nitride film (titanium nitride film [0080]) as the barrier metal (15), a distance that the titanium nitride film (titanium nitride film [0080]) moves in the depth direction (vertical direction shown in Fig 1) when the titanium nitride film (titanium nitride film [0080]) sinks due (the examiner notes that the material being a titanium nitride film, and the annealing (heat treatment) applied, the titanium nitride would sink as a result since titanium silicide is formed [0009]) to the heat treatment (annealing (heat treatment) [0009]).
Regarding Claim 7, Suzawa discloses the limitations of claim 4 as explained above. Suzawa further discloses
wherein the recess (shown in annotated Fig 1) at the main surface (shown in annotated Fig 1) of the semiconductor substrate (10) has a depth (shown in annotated Fig 1) that is less than a thickness (shown in annotated Fig 1) of the titanium nitride film (titanium nitride film [0080]) deposited at the bottom of the contact hole (14) in the depth direction (vertical direction shown in Fig 1) of the semiconductor device (trench-gate IGBT [0059] Fig 1).
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Regarding Claim 8, Suzawa discloses the limitations of claim 4 as explained above. Suzawa does not directly disclose
wherein the recess (shown in annotated Fig 1) at the main surface (shown in annotated Fig 1) of the semiconductor substrate (10) has a depth (shown in annotated Fig 1) that is less than a combined thickness of a thickness of the titanium nitride film (titanium nitride film [0080]) deposited at the bottom of the contact hole (14), and a thickness of the titanium film (titanium film [0080]) left unreacted with the semiconductor substrate (10) at the bottom of the contact hole (14), in the depth direction (vertical direction shown in Fig 1) of the semiconductor device (trench-gate IGBT [0059] Fig 1).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Suzawa (US 2020/0051852) in view of Utsumi et al (US 2019/0140092).
Regarding Claim 2, Suzawa discloses the limitations of claim 1 as explained above. Suzawa does not directly disclose
wherein in the depth direction of the semiconductor device,
a distance between the main surface of the semiconductor substrate and the upper surface of the titanium nitride film at the bottom of the contact hole is 10 nm or more.
Utsumi et al, in the related art of semiconductor devices that include, discloses
wherein in the depth direction (vertical direction shown in Fig 7) of the semiconductor device (shown in Fig 7),
a thickness of the gate insulating film (6 [0034] Fig 7) is 20 nm to 150 nm.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzawa to include wherein in the depth direction of the semiconductor device, a distance between the main surface of the semiconductor substrate and the upper surface of the titanium nitride film at the bottom of the contact hole is 10nm or more as taught by Utsumi et al in order to optimize the electrical functioning of the device while meeting small size requirements and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further because it would have been an obvious matter of design choice to optimize the distance between the main surface of the semiconductor substrate and the upper surface of the titanium nitride film at the bottom of the contact hole since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
The combination of Suzawa and Utsumi et al now discloses
wherein in the depth direction (vertical direction shown in Fig 1 Suzawa) of the semiconductor device (trench-gate IGBT [0059] Fig 1 Suzawa),
a distance between the main surface (shown above in annotated Fig 1 Suzawa) of the semiconductor substrate (10 Suzawa) and the upper surface of the titanium nitride film (top portion of barrier metal 15 Suzawa) at the bottom of the contact hole (14 Suzawa) is 10 nm or more.
Regarding Claim 6, Suzawa discloses the limitations of claim 5 as explained above. Suzawa does not directly disclose
wherein after forming the titanium silicide film, in the depth direction of the semiconductor device, a distance between the main surface of the semiconductor substrate and the upper surface of the titanium nitride film at the bottom of the contact hole is 10 nm or more.
Utsumi et al, in the related art of semiconductor devices that include, discloses
wherein in the depth direction (vertical direction shown in Fig 7) of the semiconductor device (shown in Fig 7),
a thickness of the gate insulating film (6 [0034] Fig 7) is 20 nm to 150 nm.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzawa to include wherein in the depth direction of the semiconductor device, a distance between the main surface of the semiconductor substrate and the upper surface of the titanium nitride film at the bottom of the contact hole is 10nm or more as taught by Utsumi et al in order to optimize the electrical functioning of the device while meeting small size requirements and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further because it would have been an obvious matter of design choice to optimize the distance between the main surface of the semiconductor substrate and the upper surface of the titanium nitride film at the bottom of the contact hole since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A).
The combination of Suzawa and Utsumi et al now discloses
wherein after forming the titanium silicide film, in the depth direction (vertical direction shown in Fig 1 Suzawa) of the semiconductor device (trench-gate IGBT [0059] Fig 1 Suzawa),
a distance between the main surface (shown above in annotated Fig 1 Suzawa) of the semiconductor substrate (10 Suzawa) and the upper surface of the titanium nitride film (top portion of barrier metal 15 Suzawa) at the bottom of the contact hole (14 Suzawa) is 10 nm or more.
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jang et al (US 2001/0007797) which discloses a barrier metal layer, a titanium layer, a titanium nitride layer, and a contact hole and method of forming using CVD [0025]-[0026], and Shirakawa et al (US 2013/0001685) which discloses an IGBT semiconductor device [0003].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812