Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2, which depends from claim 1, recites “the at least one counter is configured to track the number of the symbols received from multiple monitored devices” and “monitor a relative synchronization of clocks of the monitored devices based on at least one value of the at least one counter.” However, in claim 1, “the at least one counter” tracks number of the symbols received from a single monitored device. Furthermore, nothing has been provided in the claims or in the specification how synchronization of clocks of multiple devices can be monitored based on value of a single counter as has been recited in claim 2. Indeed, paragraph [0056] of the specification describes using one counter to “track a number of the symbols 20 received from one of the monitored devices” and another counter to “track a number of symbols sent to that monitored device.” Therefore, the abovementioned limitation fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 2 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the abovementioned limitations have been construed as the at least one counter is configured to track the number of the symbols received from the at least one monitored device and monitor a relative synchronization of the at least one clock of the at least one monitored device based on at least one value of the at least one counter.
Claim 3, which depends from claim 1, recites “the at least one counter is configured to track the number of symbols received from, and sent to, the at least one monitored device.” However, nothing in the claims nor in the specification of the present application appear to describe how a single counter tracks both received and sent. As explained above, paragraph [0056] of the specification using one counter to “track a number of the symbols 20 received from one of the monitored devices” and a separate counter to “track a number of symbols sent to that monitored device.” Therefore, a single counter is not tracking the number of symbols received from, and sent to, the at least one monitored device. Therefore, the abovementioned limitation fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 3 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the abovementioned limitation is interpreted as the at least one counter to track the number of symbols received from the at least one monitored device and monitor synchronization of the at least one clock of the at least one monitored device based on the number of symbols received from the at least one monitored device.
Claim 4, which depends from claim 3, which further depends from claim 1, recites “the at least one counter includes: a first counter to track the number of symbols received from, the at least one monitored device; and a second counter to track the number of symbols sent to the at least one monitored device.” However, nothing in the claims nor in the specification of the present application appear to describe how a single counter includes two counters, where each of the counter one counter tracks receiving symbols and the other counter tracking transmitted symbols. Indeed, paragraph [0056] of the specification describes two separate counters for tracking symbols received and transmitted, but does not describe that a single counter includes two separate counters. Furthermore, claim 1 already recites that “the at least one counter” “track[s] a number of symbols received. . . .” Again, nothing in the claims nor in the specification describes how a counter that already tracks received symbols also tracks transmitted symbols. Therefore, the abovementioned limitation fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 4 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the abovementioned limitation is interpreted as the at least one counter to track the number of symbols received from the at least one monitored device and the device further comprising a second counter to track the number of symbols sent to the at least one monitored device.
Claim 5, which depends from claim 3, recites “compute an error value of the at least one clock of the at least one monitored device based on to the number of symbols received from, and sent to, the at least one monitored device as tracked by the at least one counter.” However, as explained above with respect to claim 3, nothing in claim 5 nor in the specification of the present application appear to describe how a single counter tracks both received and sent. As explained above, paragraph [0056] of the specification using one counter to “track a number of the symbols 20 received from one of the monitored devices” and a separate counter to “track a number of symbols sent to that monitored device.” Therefore, a single counter is not tracking the number of symbols received from, and sent to, the at least one monitored device. Therefore, the abovementioned limitation fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 5 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the abovementioned limitation is interpreted as compute an error value based on the number of symbols received from the at least one monitored device as tracked by the at least one counter and another number of symbols sent to the at least one monitored device as tracked by a second counter.
Claim 6 depends from claim 5, and accordingly incorporates all of the limitations of claim 1. Therefore, for the reasons stated above for at least claim 5, claim 6 also fails to reasonably apprise one of ordinary skill in the art of the scope of the invention, and is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13, which depends from claim 1, recites “monitor synchronization of respective clocks of respective monitored devices based on values of the at least one counter.” However, “the at least one counter” in claim 1 tracks number of the symbols received from a single monitored device. Furthermore, nothing has been provided in the claims or in the specification for synchronizing clocks of multiple devices based on values of a single counter as has been recited in claim 13. As explained above, paragraph [0056] of the specification describes using one counter to “track a number of the symbols 20 received from one of the monitored devices” and another counter to “track a number of symbols sent to that monitored device.” In other words, the specification appears to describe that a counter is associated with a single device. Therefore, the abovementioned limitation fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 13 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the abovementioned limitation has been construed as monitor synchronization of respective clock of the at least one monitored device based on values of the at least one counter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16, 21, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shapira et al. (U.S. Publication No. 2023/0163869).
Regarding claim 1, Shapira teaches “[a] monitoring device, comprising: an interface to receive symbols from at least one monitored device over at least one communication link” (see ¶ [0102]; local device (i.e., monitoring device) may run at the same speed as the link partner (i.e., monitored device); thus, the local device and the link partner are communicatively linked via a link (i.e., at least one communication link); the time/bits/symbols that passed on the link partner (i.e., via the communication link) may be extracted or determined or estimated, e.g., by accumulating bits/“symbols” on the RX side (i.e., receive symbols from at least one monitored device), and trying to “track” this value on the TX/local side; receiving symbols via communication link inherently discloses an interface to receive symbols since receiving symbols inherently requires some form of interface to coordinate with the communication link via which symbols are being received; thus, monitoring device comprises an interface to receive symbols from at least one monitored device over at least one communication link);
Shapira also teaches “at least one counter to track a number of the symbols received from the at least one monitored device over the at least one communication link” (see ¶¶ [0102] and [0104]; the time/bits/symbols that passed on the link partner (i.e., via the communication link) may be extracted or determined or estimated, e.g., by accumulating bits/“symbols” on the RX side (i.e., track a number of the symbols received from at least one monitored device); the RX-symbol rate is measured or extracted inside the physical layer of the network port e.g., by “perf count/s” (performance counters in the network device e.g., NIC); thus, at least one counter to track a number of the symbols received from the at least one monitored device over the at least one communication link); and
Shapira also teaches “processing circuitry to monitor synchronization at least one clock of the at least one monitored device based on at least one value of the at least one counter” (see ¶¶ [0085], [0087] and [0122]; frequency difference could be measured using the difference between the number of received symbols and transmitted ones on the same lane; receiving more symbols than transmitting in the same period of time indicates that the local frequency (i.e., at least one clock) is slower than the nominal frequency and local frequency should be raised (i.e., monitor synchronization); receiving fewer symbols than transmitting in the same period of time indicates that the local frequency (i.e., at least one clock) is faster than the nominal frequency and the local frequency should be lowered (i.e., monitor synchronization); Reference Clock typically adjusts the frequency of the PHC (clock) and brings the PHC's frequency close to the nominal; embodiments provide a much more stable frequency clock for a network device (and/or other value absent from SyncE) (i.e., monitor synchronization of at least one clock of the at least one monitored device), e.g., by using the extracted data from the symbol rate (i.e., based on at least one value of the at least one counter) for adjustments to the PHC; thus, monitor synchronization of at least one clock of the at least one monitored device based on at least one value of the at least one counter).
Regarding claim 2, Shapira teaches the device of claim 1, and further teaches “wherein: the at least one counter is configured to track the number of the symbols received from multiple monitored devices; and the processing circuitry is configured to monitor a relative synchronization of clocks of the monitored devices based on at least one value of the at least one counter” (see ¶¶ [0087], [0102], [0104], and [0122]; [NOTE: as explained with respect to rejection of 112(b) of claim 2, the foregoing limitations related to the counter and the monitored devices have been construed as the at least one counter is configured to track the number of the symbols received from the at least one monitored device and monitor a relative synchronization of the at least one clock of the at least one monitored device based on at least one value of the at least one counter]; RX-symbol rate is measured or extracted inside the physical layer of the network port e.g., by “perf count/s” (performance counters in the network device e.g., NIC); thus, the at least one counter is configured to track the number of the symbols received from the at least one monitored device; provide a much more stable frequency clock for a network device (and/or other value absent from SyncE) (i.e., monitor synchronization of at least one clock of the at least one monitored device), e.g., by using the extracted data from the symbol rate (i.e., based on at least one value of the at least one counter) for adjustments to the PHC; thus, monitor a relative synchronization of the at least one clock of the at least one monitored device based on at least one value of the at least one counter).
Regarding claim 3, Shapira teaches the device of claim 1, and further teaches “the interface is configured to send symbols to the at least one monitored device; the at least one counter is configured to track the number of symbols received from, and sent to, the at least one monitored device; and the processing circuitry is configured to monitor synchronization of the at least one clock of the at least one monitored device based on the number of symbols received from, and sent to, the at least one monitored device” (see ¶¶ [0073], [0085], [0087], [0102], [0104], and [0122]; [NOTE: as explained with respect to rejection of 112(b) of claim 3, the limitations “the at least one counter is configured to track the number of symbols received from, and sent to, the at least one monitored device; and the processing circuitry is configured to monitor synchronization of the at least one clock of the at least one monitored device based on the number of symbols received from, and sent to, the at least one monitored device” have been construed as the at least one counter to track the number of symbols received from the at least one monitored device and monitor synchronization of the at least one clock of the at least one monitored device based on the number of symbols received from the at least one monitored device]; TX frequency is for transmission by that local device, e.g., from/to the local device's link partner/s (i.e., to the least one monitored device); the time/bits/symbols that passed on the link partner may be extracted or determined or estimated, e.g., by accumulating bits/“symbols” on the RX side, and trying to “track” this value on the TX/local side (i.e., send symbols to the least one monitored device); transmitting symbols via communication link inherently discloses an interface to send symbols since sending symbols inherently requires some form of interface to coordinate with the communication link via which symbols are being sent; thus, the interface is configured to send symbols to the at least one monitored device; the RX-symbol rate is measured or extracted inside the physical layer of the network port e.g., by “perf count/s” (performance counters in the network device e.g., NIC); thus, the at least one counter is configured to track the number of symbols received from the at least one monitored device; frequency difference could be measured using the difference between the number of received symbols and transmitted ones on the same lane; receiving more symbols than transmitting in the same period of time indicates that the local frequency (i.e., at least one clock) is slower than the nominal frequency and local frequency should be raised (i.e., monitor synchronization); receiving fewer symbols than transmitting in the same period of time indicates that the local frequency (i.e., at least one clock) is faster than the nominal frequency and the local frequency should be lowered (i.e., monitor synchronization); Reference Clock typically adjusts the frequency of the PHC (clock) and brings the PHC's frequency close to the nominal; using the extracted data from the symbol rate (i.e., based on at least one value of the at least one counter) for adjustments to the PHC; thus, monitor synchronization of the at least one clock of the at least one monitored device based on the number of symbols received from the at least one monitored device).
Regarding claim 4, Shapira teaches the device of claim 3, and further teaches “the at least one counter includes: a first counter to track the number of symbols received from, the at least one monitored device; and a second counter to track the number of symbols sent to the at least one monitored device, and the processing circuitry is configured to monitor synchronization of the at least one clock of the at least one monitored device based on a first value of the first counter and a second value of the second counter” (see ¶¶ [0085], [0087], [0102], [0104], and [0122]; [NOTE: as explained with respect to rejection of 112(b) of claim 4, the foregoing limitations related to the counters have been construed as the at least one counter to track the number of symbols received from the at least one monitored device and the device further comprising a second counter to track the number of symbols sent to the at least one monitored device]; the time/bits/symbols that passed on the link partner (i.e., via the communication link) may be extracted or determined or estimated, e.g., by accumulating bits/“symbols” on the RX side (i.e., the at least one counter to track a number of the symbols received from at least one monitored device), and trying to “track” this value on the TX/local side (i.e., a second counter to track the number of symbols sent to the at least one monitored device); frequency difference could be measured using the difference between the number of received symbols and transmitted ones (i.e., a first value of the first counter and a second value of the second counter) on the same lane; receiving more symbols than transmitting (i.e., based on a first value of the first counter and a second value of the second counter) in the same period of time indicates that the local frequency (i.e., the at least one clock) is slower than the nominal frequency and local frequency should be raised (i.e., monitor synchronization based on a first value of the first counter and a second value of the second counter); thus, monitor synchronization of the at least one clock of the at least one monitored device based on a first value of the first counter and a second value of the second counter).
Regarding claim 5, Shapira teaches the device of claim 3, and further teaches “wherein the processing circuitry is configured to compute an error value of the at least one clock of the at least one monitored device based on to the number of symbols received from, and sent to, the at least one monitored device as tracked by the at least one counter” (see ¶¶ [0085] and [0102]; [NOTE: as explained with respect to rejection of 112(b) of claim 5, the foregoing limitation related to the number of symbols received from, and sent to, the at least one monitored device as tracked by the at least one counter has been interpreted as compute an error value based on the number of symbols received from the at least one monitored device as tracked by the at least one counter and another number of symbols sent to the at least one monitored device as tracked by a second counter]; receiving more symbols than transmitting (i.e., based on the number of symbols received from, and sent to, the at least one monitored device) in the same period of time indicates that the local frequency is slower (i.e., compute an error value of the at least one clock of the at least one monitored device) than the nominal frequency and local frequency should be raised; the time/bits/symbols that passed on the link partner (i.e., via the communication link) may be extracted or determined or estimated, e.g., by accumulating bits/“symbols” on the RX side (i.e., the at least one counter to track a number of the symbols received from at least one monitored device), and trying to “track” this value on the TX/local side (i.e., a second counter to track the number of symbols sent to the at least one monitored device); thus, compute an error value of the at least one clock of the at least one monitored device based on to the number of symbols received from, and sent to, the at least one monitored device as tracked by the at least one counter).
Regarding claim 6, Shapira teaches the device of claim 5, and further teaches “wherein the processing circuitry is configured to perform an action responsively to the error value exceeding a given threshold” (¶ [0085]; receiving more symbols than transmitting in the same period of time indicates that the local frequency is slower than the nominal frequency (i.e., the error value exceeding a given threshold) and local frequency should be raised (i.e., perform an action responsively); thus, perform an action responsively to the error value exceeding a given threshold).
Regarding claim 7, Shapira teaches the device of claim 1, and further teaches “wherein the processing circuitry is configured to provide a software interface to allow software to monitor the synchronization of the at least one clock of the at least one monitored device” (see ¶ [0106]; Time Source Selection software which serves as a software interface to the controller; Time Source Selection SW block typically selects a network port having an RX symbol rate known to a partner, from among plural network ports having an RX symbol rate known to the partner; interfacing with a “NIC” such as the MC of FIG. 4 , or any other appropriate network device. The “Set status (Reference source)” and “Local clock quality”; thus, provide a software interface to allow software to monitor the synchronization of the at least one clock of the at least one monitored device).
Regarding claim 8, Shapira teaches the device of claim 1, and further teaches “wherein the software interface is configured to receive an instruction from the software to reset the at least one counter, the processing circuitry being configured to reset the at least one counter responsively to receiving the instruction” (see ¶ [0106]; Time Source Selection software which serves as a software interface to the controller; receive inputs to Set Status (i.e., reset); thus, the software interface is configured to receive an instruction from the software to reset the at least one counter, the processing circuitry being configured to reset the at least one counter responsively to receiving the instruction).
Regarding claim 9, Shapira teaches the device of claim 1, and further teaches “wherein the software interface is configured to receive a request from the software for a current or average error value or history of the at least one clock, wherein the software interface is configured to provide the current or average error value or history of the at least one clock to the software” (see ¶ [0106]; Time Source Selection software block typically selects a network port having an RX symbol rate known to a partner, from among plural network ports having an RX symbol rate known to the partner; interfacing with a “NIC”; software block receives requests for status of local clock (history of the at least one clock) and updates; thus, provide the current or average error value or history of the at least one clock to the software).
Regarding claim 10, Shapira teaches the device of claim 1, and further teaches “wherein the software interface is configured to receive a request from the software to provide periodic error reports of at least one error of the at least one clock, wherein the software interface is configured to provide the periodic error reports to the software” (see ¶ [0106]; Time Source Selection software receives message for clock status or errors (i.e., receive a request from the software to provide periodic error reports of at least one error of the at least one clock); sends packets indicating status of clock (i.e., provide the periodic error reports to the software); thus, provide the current or average error value or history of the at least one clock to the software).
Regarding claim 11, Shapira teaches the device of claim 1, and further teaches “wherein the software interface is configured to receive an error threshold from the software, wherein the software interface is configured to provide a report to the software responsively to an error of the at least one clock exceeding the error threshold” (see ¶¶ [0106]-[0108]; Time Source Selection software receives inputs for error limits (i.e., error threshold from the software); sends packets indicating status of clock (provide the periodic error reports to the software); thus, provide a report to the software responsively to an error of the at least one clock exceeding the error threshold).
Regarding claim 12, Shapira teaches the device of claim 1, and further teaches “wherein the processing circuitry is configured to generate and provide a report responsively to monitoring the synchronization” (see ¶ [0106]; sends packets indicating status of clock (provide the periodic error reports to the software); thus, generate and provide a report responsively to monitoring the synchronization).
Regarding claim 13, Shapira teaches the device of claim 1, and further teaches “wherein the processing circuitry is configured to monitor synchronization of respective clocks of respective monitored devices based on values of the at least one counter” (see ¶¶ [0102] and [0104]; [NOTE: as explained with respect to rejection of 112(b) of claim 13, the foregoing limitation has been construed as monitor synchronization of respective clock of the at least one monitored device based on values of the at least one counter]; the RX-symbol rate is measured or extracted inside the physical layer of the network port e.g., by “perf count/s” (performance counters in the network device e.g., NIC); thus, monitor synchronization of respective clock of the at least one monitored device based on values of the at least one counter).
Regarding claim 14, Shapira teaches the device of claim 1, and further teaches “wherein the processing circuitry is configured to detect an anomaly in one of the monitored devices responsively to comparing the values of the at least one counter” (see ¶¶ [0102] and [0104]; the RX-symbol rate is measured or extracted inside the physical layer of the network port e.g., by “perf count/s” (performance counters in the network device e.g., NIC); identify counter differences (i.e., anomaly); thus, detect an anomaly in one of the monitored devices responsively to comparing the values of the at least one counter).
Regarding claim 15, Shapira teaches the device of claim 1, and further teaches “a hardware clock; and synchronization circuitry to cause synchronization of the at least one clock of the at least one monitored device to be synchronized to the hardware clock” (see ¶¶ [0087] and [0122]; Reference Clock typically adjusts the frequency of the PHC (hardware clock) and brings the PHC's frequency close to the nominal; embodiments provide a much more stable frequency clock for a network device (and/or other value absent from SyncE) (i.e., monitor synchronization of at least one clock of the at least one monitored device), e.g., by using the extracted data from the symbol rate (i.e., based on at least one value of the at least one counter) for adjustments to the PHC; thus, synchronization of the at least one clock of the at least one monitored device to be synchronized to the hardware clock).
Regarding claim 16, Shapira teaches the device of claim 1, and further teaches “a network interface controller or a network switch or a data processing unit (DPU)” (see ¶ [0106]; network device includes a network interface controller, a “NIC”).
Regarding claim 21, Shapira teaches the device of claim 1, and further teaches “wherein the at least one communication link comprises at least one of network connection; or a data communication bus” (see ¶ [0102]; receiving symbols via communication link inherently discloses an interface to receive symbols since receiving symbols inherently requires some form of interface to coordinate with the communication link; thus, communication link includes a network connection).
Regarding claim 22, it is a method claim corresponding to claim 1 that has been rejected above. Applicant’s attention is directed to the rejection of claim 1. Claim 22 is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Shapira.
Regarding claim 17, Shapira teaches the device of claim 1, and further teaches “a processor to execute software . . . a graph of clock error of the at least one clock of the at least one monitored device over time” (see ¶¶ [0071] and [0077], and FIG. 7B; graph (b) shows that in the case of a fault in the PTP, the HW UTC Time keeps on drifting; periodic extracting of the network peer oscillator frequency and/or using the network peer oscillator frequency to adjust PHC frequency, may be triggered, at a given link port, by a SW [software] component; therefore, it is inherent that the device includes a processor to execute software).
Shapira does not explicitly disclose software “to plot” of claim 17. However, the foregoing limitations were well known in the art prior to the effective filing date of the claimed invention. Since Shapira already teaches a processor to execute software and a graph of clock error of the at least one clock of the at least one monitored device over time as discussed above, and further teaches at ¶ [0086] “periodic extracting of the network peer oscillator frequency and/or using the network peer oscillator frequency to adjust PHC frequency, may be triggered, at a given link port, by a SW component” (emphasis added), it would have been obvious to one skilled in the art, prior to the effective filing date of the claimed invention, to have configured/modified the software component/module to plot said graph of clock error of the at least one clock of the at least one monitored device over time. The suggestion to do so would have been to improve latency measurement by improving clock synchronization (see ¶ [0051] of Shapira).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shapira in view of Gomez et al. (U.S. Publication No. 2023/0056803).
Regarding claim 18, Shapira teaches the device of claim 1, and further teaches “a hardware clock” (see ¶ [0073]; based on—RX-TX frequency ratio and/or—RX-PHC frequency ratio, the PHC (i.e., a hardware clock) update rate can be updated). Shapira does not explicitly disclose the hardware clock includes “an oven-controlled crystal oscillator or an atomic clock” of claim 18. However, the foregoing limitations were well known in the art prior to the effective filing date of the claimed invention. For example, Gomez teaches “an oven-controlled crystal oscillator or an atomic clock” (see ¶ [0057]; clock may be an atomic clock or include an Oven Controlled Crystal Oscillator (OCXO)).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention as taught by Shapira to incorporate the teachings of Gomez to have a hardware clock including atomic clock or include an Oven Controlled Crystal. The suggestion to do so would have been to achieve the greater precision in timing control (see ¶ [0003] of Gomez).
Regarding claim 19, Shapira teaches the device of claim 1, and further teaches “a hardware clock” (see ¶ [0073]; based on—RX-TX frequency ratio and/or—RX-PHC frequency ratio, the PHC (i.e., a hardware clock) update rate can be updated). Shapira does not explicitly disclose the hardware clock includes “synchronization circuitry to discipline the hardware clock from a remote device” of claim 19. However, the foregoing limitations were well known in the art prior to the effective filing date of the claimed invention. For example, Gomez teaches “synchronization circuitry to discipline the hardware clock from a remote device” (see ¶ [0033]; GNSS receiver generates a 1PPS signal synchronized to UTC using the GNSS signals, and based on the 1PPS signal, the GM (i.e., remote device) outputs a GM clock signal, such as a root timing reference; the GM distributes (i.e., from a remote device) the GM clock signal to other clocks in the network so the clocks can synchronize; thus, the receiving network element must include synchronization circuitry to discipline the hardware clock from a remote device).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention as taught by Shapira to incorporate the teachings of Gomez to have a hardware clock being disciplined by a remote device. The suggestion to do so would have been to achieve the greater precision in timing control (see ¶ [0003] of Gomez).
Regarding claim 20, the combination of Shapira and Gomez teaches the device of claim 19, and further teaches “wherein the synchronization circuitry is configured to discipline the hardware clock from a pulse per second signal received from a Global navigation satellite system (GNSS) receiver” (see ¶ [0033] of Gomez; GNSS receiver generates a 1PPS signal (i.e., a pulse per second signal received from a Global navigation satellite system (GNSS) receiver) synchronized to UTC using the GNSS signals, and based on the 1PPS signal, the GM outputs a GM clock signal (i.e., pulse per second signal from (GNSS) receiver is being output), such as a root timing reference; the GM distributes the GM clock signal to other clocks (i.e., received from a Global navigation satellite system (GNSS) receiver) in the network so the clocks can synchronize; thus, the synchronization circuitry is configured to discipline the hardware clock from a pulse per second signal received from a Global navigation satellite system (GNSS) receiver).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the invention as taught by Shapira to incorporate the teachings of Gomez to have the hardware clock be disciplined by a 1PPS from a GNSS receiver. The suggestion to do so would have been to achieve the greater precision in timing control (see ¶ [0003] of Gomez).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shapira et al. (U.S. Publication No. 2023/0229188) teaches monitoring clock synchronization based on symbol rate.
Tishbi et al. (U.S. Patent No. 11,962,310) teaches synchronization between clock signals.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SRIHARSHA REDDY VANGAPATY whose telephone number is (571)272-7655. The examiner can normally be reached M-F 8-5 EST.
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/SRIHARSHA REDDY VANGAPATY/Examiner, Art Unit 2475
/HASHIM S BHATTI/Primary Examiner, Art Unit 2475
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