DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/27/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" “extend” “region” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently disclose a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “stretch in a direction” “a part, portion, or area having no fixed boundaries” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between).
Claim(s) 1-3, 6-8, 11-15, 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zang et al (US 2011/0115083 A1 hereinafter Zang).
Regarding Claim 1, Zang discloses in Fig 2: A semiconductor package comprising:
a substrate (201);
a first semiconductor chip (Die) on an upper surface of the substrate;
electrically conductive bumps (204) extending between and electrically connected to the substrate (201) and the first semiconductor chip (Die);
a non-conductive film layer having at least a portion extending between the electrically conductive bumps [0020];
a second semiconductor chip (Die 2) extending on the upper surface of the substrate;
and electrically conductive wires that electrically connect respective portions of the second semiconductor chip to respective portions of the upper surface of the substrate [0019];
wherein the upper surface of the substrate includes a dam (215), which protrudes between one of: (i) a region overlapping the second semiconductor chip, and (ii) a region connected to the wires and a region overlapping the first semiconductor chip;
and wherein the upper surface of the substrate further includes a trench (211-213) recessed alongside at least a portion of the dam [0019-0022]. Examiner notes that the limitation region is being interpreted broadly as shown in note above and regions as claimed could be arbitrarily chosen to satisfy claimed limitations. Additionally, the overlap direction is not specified and thus one of ordinary skilled in the art could arbitrarily choose a direction so as to read on the claim limitation.
Regarding Claim 2, Zang discloses in Fig 2: The semiconductor package of Claim 1,
wherein the second semiconductor chip (Die 2) extends on an upper surface of the first semiconductor chip (Die);
wherein at least a portion of the dam (215) protrudes between the region connected to the wires and the region overlapping the first semiconductor chip (Die); and
wherein at least a portion of the trench (211-213) is recessed between the region
connected to the wires and the region overlapping the first semiconductor chip.
Regarding Claim 3, Zang discloses in Fig 2: The semiconductor package of Claim 1, wherein the second semiconductor chip (Die2) is attached to the upper surface of the substrate (201) through an adhesive film; and wherein at least a portion of the dam and at least a portion of the trench overlap a space between the first and second semiconductor chips (Die and Die2) – See note for definition of overlap. Additionally, the overlap direction is not specified and thus one of ordinary skilled in the art could arbitrarily choose a direction so as to read on the claim limitation.
Regarding Claim 6, Zang discloses in Fig 2: The semiconductor package of Claim 1, wherein the trench includes trenches (211-213); and wherein at least a portion of the dam (215) protrudes between the trenches.
Regarding Claim 7, Zang discloses in Fig 2: The semiconductor package of Claim 1, wherein the dam (215) has a shape that at least partially surrounds the region overlapping the first semiconductor chip (Die); and wherein the trench (211-213) has a shape extending at least partially alongside a portion of the dam (215).
Regarding Claim 8, Zang discloses in Fig 2: The semiconductor package of Claim 1, wherein the substrate (201) includes a solder resist layer (206) on the upper surface of the substrate; wherein the dam protrudes from an upper surface of the solder resist layer; and wherein the trench (211-213) has a shape in which the solder resist layer is recessed (See Fig 2).
Regarding Claim 11, Zang discloses in Fig 2: The semiconductor package of Claim 1, wherein the second semiconductor chip (Die2) includes a plurality of second semiconductor chips; wherein the first semiconductor chip (Die) extends between a portion of one of the second semiconductor chips and the substrate (201); and wherein another one of the second semiconductor chips extends between the other portion of one of the second semiconductor chips and the substrate [0029]. Examiner notes that in [0029] that Zang teaches additional chips could be stacked on Die and Die2 and thus it is understood that the second semiconductor chips would extend between second semiconductor chip and the substrate.
Regarding Claim 12, Zang discloses in Fig 2: A semiconductor package, comprising:
a substrate (201);
a first semiconductor chip (Die) extending on an upper surface of the substrate;
electrically conductive bumps (204 See Fig 2) extending between and connected to the substrate and the first semiconductor chip;
a non-conductive film layer (206) having at least a portion extending between the electrically conductive bumps;
second semiconductor chips (Die 2 [0029]) extending on the upper surface of the substrate;
and electrically conductive wires connecting one of the second semiconductor chips and the upper surface of the substrate [0019]; and
wherein the upper surface of the substrate includes a dam (215) protruding between a region overlapping another one of the second semiconductor chips and a region overlapping the first semiconductor chip, and protruding between a region connected to the wires and the region overlapping the first semiconductor chip; and
wherein the upper surface of the substrate further includes a trench (211-213) recessed alongside at least a portion of the dam [0018-0022].
Regarding Claim 13, Zang discloses in Fig 2: The semiconductor package of Claim 12, wherein the one of the second semiconductor chips (Die2) extends on an upper surface of the first semiconductor chip (Die); and wherein the other one of the second semiconductor chips is attached to the upper surface of the substrate through an adhesive film [0029]. Examiner notes stacking of plurality of chip on Die2 using die attach/underfill in [0029].
Regarding Claim 14, Zang discloses in Fig 2: The semiconductor package of Claim 13, wherein the dam (215) has a shape that at least partially surrounds the region overlapping the first semiconductor chip (Die); and wherein at least a portion of the trench (211-213) is recessed between the region overlapping the other one of the second semiconductor chips (Die2) and the dam (215), and is recessed between the region connected to the wires and the dam. Examiner notes that the bonding wire between Die2 and pad 205 would have the recessed trenches.
Regarding Claim 15, Zang discloses in Fig 2: The semiconductor package of Claim 14, wherein the trench includes at least four trenches, with two of the trenches surrounded by the dam and spaced apart from each other, and another two of the trenches spaced apart from each other without being surrounded by the dam.
Regarding Claim 17, Zang discloses in Fig 2: A semiconductor package, comprising:
a substrate (201);
first (Die) and second semiconductor chips (Die2) extending on an upper surface of the substrate;
electrically conductive bumps (204) extending between and connected to the
substrate and the first semiconductor chip; and
a non-conductive film layer (under fill) having at least a portion extending between the electrically conductive bumps; and
wherein the upper surface of the substrate includes a dam (215), which protrudes and has a shape extending to surround (partially) a region overlapping the first semiconductor chip, and a trench (211-213) that is recessed and has a shape extending partially alongside portion of the dam (215) [0018-0022].
Regarding Claim 18, Zang discloses in Fig 2: The semiconductor package of Claim 17, wherein the trench has a slit in which at least a portion of the trench extends in one direction and is then disconnected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 10, 16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al (US 2011/0115083 A1 hereinafter Zang) over Hong et al (US 2021/0057299 A1 hereinafter Hong).
Regarding Claim 9, Zang discloses in Fig 2: The semiconductor package of Claim 8.
Zang does not disclose: wherein the substrate has a structure in which at least one interconnection layer and at least one insulating layer are alternately stacked on a lower side of the solder resist layer; and wherein the trench upwardly exposes the at least one insulating layer.
However, Hong in a similar device teaches in Fig 1: wherein the substrate has a structure (120) in which at least one interconnection layer (122) and at least one insulating layer (121) are alternately stacked on a lower side of the solder resist layer; and wherein the trench upwardly exposes the at least one insulating layer (See Fig 1).
References Zang and Hong are analogous art because they both are directed to packaging semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Zang with the specified features of Hong because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Zang and Hong so that the substrate has a structure in which at least one interconnection layer and at least one insulating layer are alternately stacked on a lower side of the solder resist layer; and wherein the trench upwardly exposes the at least one insulating layer as taught by Hong in Zang’s device since, package substrates with alternating insulating layer and metal layers are most commonly used in semiconductor arts.
Regarding Claim 10, Zang discloses in Fig 2: The semiconductor package of Claim 9.
Zang does not disclose: further comprising: an encapsulant, which seals the first and second semiconductor chips; and wherein at least one of the encapsulant and the non-conductive film layer is in direct contact with the at least one insulating layer.
However, Hong in a similar device teaches in Fig 1: further comprising: an encapsulant, which seals the first and second semiconductor chips; and wherein at least one of the encapsulant (160) and the non-conductive film layer (underfill) is in direct contact with the at least one insulating layer (121: See Fig 1) [0054].
References Zang and Hong are analogous art because they both are directed to packaging semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Zang with the specified features of Hong because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Zang and Hong so that an encapsulant, which seals the first and second semiconductor chips; and wherein at least one of the encapsulant and the non-conductive film layer is in direct contact with the at least one insulating layer as taught by Hong in Zang’s device since, encapsulant prevents the external factors from affecting the die.
Regarding Claim 16(20), Zang discloses in Fig 2: The semiconductor package of Claim 15(17). Zang further discloses that the wherein the substrate includes a solder resist layer on the upper surface of the substrate; wherein the dam protrudes from an upper surface of the solder resist layer; wherein the substrate (120) includes a solder resist layer on the upper surface of the substrate,
Zang does not disclose: further comprising: further comprising:
an encapsulant sealing the first semiconductor chip; and
wherein the substrate has a structure in which at least one interconnection layer and at least one insulating layer are alternately stacked on a lower side of the solder resist layer;
and wherein the encapsulant or the non-conductive film layer is in direct contact with the at least one insulating layer through the trench.
However, Hong in a similar device teaches in Fig 1: further comprising: further comprising:
an encapsulant (160) sealing the first semiconductor chip (140); and
wherein the substrate (120) has a structure in which at least one interconnection layer (122) and at least one insulating layer (122) are alternately stacked on a lower side of the substrate surface;
and wherein the encapsulant or the non-conductive film layer is in direct contact with the at least one insulating layer through the trench (132: See Fig 1) [0054].
References Zang and Hong are analogous art because they both are directed to packaging semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Zang with the specified features of Hong because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Zang and Hong so that further comprising: an encapsulant sealing the first semiconductor chip; and wherein the substrate has a structure in which at least one interconnection layer and at least one insulating layer are alternately stacked on a lower side of the solder resist layer; and wherein the encapsulant or the non-conductive film layer is in direct contact with the at least one insulating layer through the trench as taught by Hong in Zang’s device since, encapsulant prevents the external factors from affecting the die.
Allowable Subject Matter
Claims 4-5, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 4, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein a distance between the dam and the second semiconductor chip is less than a distance between the dam and the first semiconductor chip” as recited in claim 4 in combination with the remaining features.
Dependent claim 5 is indicated as allowable based on virtue of its dependencies.
The most relevant prior art references, (US 2011/0115083 A1) to Zang in Fig 2, and US 2021/0057299 A1 to Hong et al. in Fig 1 substantially teach the limitations of the claim 4, with the exception of the limitations described in the preceding paragraph.
With respect to claim 19, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the trench includes at least four trenches, with two of the trenches surrounded by the dam and spaced apart from each other, and another two of the trenches are spaced apart from each other without being surrounded by the dam” as recited in claim 19 in combination with the remaining features.
The most relevant prior art references, (US 2011/0115083 A1) to Zang in Fig 2, and US 2021/0057299 A1 to Hong et al. in Fig 1 substantially teach the limitations of the claim 19, with the exception of the limitations described in the preceding paragraph.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NISHATH YASMEEN whose telephone number is (571)270-7564. The examiner can normally be reached Mon-Fri 9AM-6PM.
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811