DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/27/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 6, 9, 12, 13, 15, 16, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Falvo et al (US 2014/0094018 A1 herein after Falvo) and further evidenced by Arita, Kiyoshi in US 7,060,531 B2.
Regarding Claim 1, Falvo disclose in Figs 1-4: A method of singulation of dies from a wafer, wherein the wafer has a backside, a topside and comprises a semiconductor layer (110) and a coating applied to the backside of the wafer after back grinding [0037], wherein the coating comprises at least one metallization layer (130), wherein the dies (120) are separated along saw streets running in multiple directions, wherein the method comprises the steps of:
applying a layer of photoresist as an etch mask [0037] on the topside of the wafer for the step of etching the wafer in accordance with the etch mask;
dicing the wafer along the saw streets from the topside of the wafer (Fig 2b): wherein the dicing is performed through plasma dicing for a dicing depth corresponding to the interface between the semiconductor layer and the coating (Fig 2b), and wherein the layer of photoresist is applied prior to the step of dicing [0037], wherein the method further comprises the step of:
etching the wafer in accordance with an etch mask corresponding to the saw streets, for each of the remaining metallization layers in the coating (See Fig 3a-3b), for singulating the dies from the wafer [0036-0041]. Examiner notes that Falvo discloses an etch mask but does not specifically disclose a photoresist mask. It is further noted that one of ordinary skilled in the art would find it obvious that photoresist is one of most common masks used in the semiconductor industry as evidenced by Arita in US 7,060,531 B2 in Fig 4a-4b wherein a photoresist layer 31 is used to form a patterned mask in (Col 7 lines 63-67).
Regarding Claim 2, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1, wherein the layer of photoresist is applied in correspondence with the saw streets and covers bond pads of the dies [0037].
Regarding Claim 4, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1, wherein the step of etching the metallization layers in the coating comprises wet etching the metallization layers on a layer-per-layer basis [0041].
Regarding Claim 6, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1, further comprising the step of, prior to the step of dicing the wafer, attaching the wafer to a protective wafer tape on the backside of the wafer [0037, 0039].
Regarding Claim 9, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1, wherein the saw streets are configured for each die to have at least one shape selected from the group consisting of a rectangular shape, a square shape, and a hexagonal shape (See Fig 1).
Regarding Claim 11, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1.
Falvo does not disclose: wherein the saw street width is below 50um.
However, the Applicant has not disclosed that having the saw street width in a certain range solves any stated problem or is for any particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed values). On the other hand, one of ordinary skilled in the art would find it obvious that the scribe street width will affect usable Si real esteate on the wafer and thus would be considered a result effective variable. Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art at the time of the invention would recognize that it would be obvious to optimize “scribe street width” as a "result effective variable”, and arrive at the recited limitation.
Regarding Claim 12, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1, wherein the semiconductor material comprises silicon [0034].
Regarding Claim 13, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 2, wherein the saw streets are configured for each die to have at least one shape selected from the group consisting of a rectangular shape, a square shape, and a hexagonal shape (See Fig 1).
Regarding Claim 15, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 2.
Falvo does not disclose: wherein the saw street width is below 50um.
However, the Applicant has not disclosed that having the saw street width in a certain range solves any stated problem or is for any particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed values). On the other hand, one of ordinary skilled in the art would find it obvious that the scribe street width will affect usable Si real esteate on the wafer and thus would be considered a result effective variable. Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art at the time of the invention would recognize that it would be obvious to optimize “scribe street width” as a "result effective variable”, and arrive at the recited limitation.
Regarding Claim 16, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 2, wherein the semiconductor material comprises silicon [0034].
Regarding Claim 18, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 3, wherein the step of etching the metallization layers in the coating comprises wet etching the metallization layers on a layer-per-layer basis [0041].
Claim(s) 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Falvo et al (US 2014/0094018 A1 herein after Falvo) in view of Arita, Kiyoshi in US 7,060,531 B2.
Regarding Claim 3, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1.
Falvo does not disclose: further comprising the step of, after the step of etching the metallization layers in the coating, removing the layer of photoresist.
However Arita in Fig 4)(a)-4(d) discloses in a similar method that the photoresist (31c) is removed after the etching the scribe streets.
References Falvo and Arita are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo with the specified features of Arita because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo and Arita so that further comprising the step of, after the step of etching the metallization layers in the coating, removing the layer of photoresist as taught by Arita in Falvo’s method since, photoresist is a removable mask used for patterning and is not required to be in the final structure.
Regarding Claim 17, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 3.
Falvo does not disclose: further comprising the step of, after the step of etching the metallization layers in the coating, removing the layer of photoresist.
However Arita in Fig 4)(a)-4(d) discloses in a similar method that the photoresist (31c) is removed after the etching the scribe streets.
References Falvo and Arita are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo with the specified features of Arita because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo and Arita so that further comprising the step of, after the step of etching the metallization layers in the coating, removing the layer of photoresist as taught by Arita in Falvo’s method since, photoresist is a removable mask used for patterning and is not required to be in the final structure.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Falvo et al (US 2014/0094018 A1 herein after Falvo) in view of Burghout et al (US 8,664,089 B2 hereinafter Burghout) and further in view of Kim et al (US2019/0368053 A1 hereinafter Kim).
Regarding Claim 5, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 4.
Falvo does not disclose: wherein the wet etching is repeated for each metallization layer in the coating and for a respective layer and comprises at least one acid selected from the group consisting of hydrofluoric acid, nitric acid, phosphoric acid, and hydrochloric acid and any combinations thereof, and ferric nitrate.
However, Burghout in a similar process teaches in Col 3 lines 1-15 that the backside metal (28) comprises multiple metal layers.
References Falvo and Burghout are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo with the specified features of Burghout because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo and Burghout so that the coating comprises three metallization layers as taught by Burghout in Falvo’s method since, this provides a method that separates the backside layers from within the singulation lines.
However, Kim in a similar process teaches in [0023] that the etchant comprises at least one acid selected from the group consisting of hydrofluoric acid, nitric acid, phosphoric acid, and hydrochloric acid and any combinations thereof, and ferric nitrate.
References Falvo, Kim and Burghout are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo and Burghout with the specified features of Kim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo, Kim and Burghout so that the etchant comprises at least one acid selected from the group consisting of hydrofluoric acid, nitric acid, phosphoric acid, and hydrochloric acid and any combinations thereof, and ferric nitrate as taught by Kim in Burghout’s and Falvo’s method since, this provides a thin film etchant composition for preventing re-adsorption of an etched metal and uniformly etching a thin film.
Claim(s) 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Falvo et al (US 2014/0094018 A1 herein after Falvo) in view of Burghout et al (US 8,664,089 B2 hereinafter Burghout).
Regarding Claim 7, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1.
Falvo does not disclose: wherein the coating comprises three metallization layers.
However, Burghout in a similar process teaches in Col 3 lines 1-15 that the backside metal (28) comprises multiple metal layers.
References Falvo and Burghout are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo with the specified features of Burghout because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo and Burghout so that the coating comprises three metallization layers as taught by Burghout in Falvo’s method since, this provides a method that separates the backside layers from within the singulation lines.
Regarding Claim 8, Falvo and Burghout disclose: The method of singulation of dies from a wafer according to claim 7.
Falvo does not disclose: wherein the three metallization layers comprise at least one material selected from the group consisting of titanium, nickel-vanadium alloy, and silver.
However, Burghout in a similar process teaches in Col 3 lines 10-15 that the backside metal (28) comprises wherein the three metallization layers comprise at least one material selected from the group consisting of titanium, nickel-vanadium alloy, and silver.
References Falvo and Burghout are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo with the specified features of Burghout because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo and Burghout so that the three metallization layers comprise at least one material selected from the group consisting of titanium, nickel-vanadium alloy, and silver as taught by Burghout in Falvo’s method since, this provides a method that separates the backside layers from within the singulation lines.
Claim(s) 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Falvo et al (US 2014/0094018 A1 herein after Falvo) in view of Arita, Kiyoshi et al (US 2007/0262420 A1 hereinafter Arita20).
Regarding Claim 10, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 1.
Falvo does not disclose: wherein the saw streets are configured for each die to have at least one edge selected from the group consisting of rounded edges, and chamfered edges.
However, Arita20 in a similar process teaches in Fig 9A-9E: wherein the saw streets are configured for each die to have at least one edge selected from the group consisting of rounded edges, and chamfered edges [0138, 0155, 0156,0174].
References Falvo and Arita20 are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo with the specified features of Arita20 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo and Arita20 so that the saw streets are configured for each die to have at least one edge selected from the group consisting of rounded edges, and chamfered edges as taught by Arita20 in Falvo’s method since, this provides a method that suppresses the occurrence of chipping of the manufactured semiconductor chips and of which the transverse rupture strength is improved can be manufactured.
Regarding Claim 14, Falvo disclose in Figs 1-4: The method of singulation of dies from a wafer according to claim 2.
Falvo does not disclose: wherein the saw streets are configured for each die to have at least one edge selected from the group consisting of rounded edges, and chamfered edges.
However, Arita20 in a similar process teaches in Fig 9A-9E: wherein the saw streets are configured for each die to have at least one edge selected from the group consisting of rounded edges, and chamfered edges [0138, 0155, 0156,0174].
References Falvo and Arita20 are analogous art because they both are directed to manufacturing methods of semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify method of Falvo with the specified features of Arita20 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Falvo and Arita20 so that wherein the saw streets are configured for each die to have at least one edge selected from the group consisting of rounded edges, and chamfered edges as taught by Arita20 in Falvo’s method since, this provides a method that suppresses the occurrence of chipping of the manufactured semiconductor chips and of which the transverse rupture strength is improved can be manufactured [0174].
Conclusion
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811