Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen(US 2020/0228375) and Venkatesan (US 2019/0042507).
Regarding claim 1, Chen discloses a link training method, comprising: performing, by a first device link training on at least one first link, wherein the first device(Figure 6, Host side 602) is connected to a second device(Figure 6, Device side 604) via an interconnect(Figure 6, 600), the first device comprises a first transmit end and a first receive end(Figure 6, 606, 608), the second device comprises a second transmit end and a second receive end(Figure 6, 610, 612), the interconnect comprises the at least one first link from the first transmit end to the second receive end and at least one second link from the second transmit end to the first receive end(Figure 6, interconnect 600); and when link training is not performed on the at least one second link, or before link training on the at least one second link succeeds, sending, by the first device, service data to the second device through at least one first link on which link training succeeds(Paragraphs 29-32. Start the downstream link training(first link). Given the downstream link is trained(the claimed first link), the TxEQ, RxEQ, Rtx, and Rrx set for the downstream link may be used as the initial settings for upstream link training(the claimed second link). Thus, the first link is trained and used for data before the second link is trained), wherein the link training is performed on the at least one first link and the link training on the at least second link are independent with of each other(Paragraphs 29-32. Start the downstream link training(first link), It is clear the first link training of the first link is independent of second link training. Start the upstream link(the claimed second link) training towards the negotiated data rate. The process repeats as defined in phase 2 until successful upstream link is trained. The second link training is independent of the first link training).
Chen does not specifically disclose the interconnect is a cable and that service data comprises video or audio data. However, Venkatesan discloses link training via a cable, wherein the main link handles audio/video data from source to the sink(Paragraphs 20-21). Venkatesan discloses using an aux link as a feedback channel(Paragraph 16), which is similar in operation to Chens source to sink training on one channel in one direction and feedback on another channel in reverse direction. It would have been obvious to one ordinary skill in the art to combine the teachings of Chen and Venkatesan before the effective filing date of the claimed invention to link train via a cable, wherein the service data comprises video or audio data. The motivation to do so would be for two external devices to train and communicate.
Regarding claim 2, Chen and Venkatesan disclose link training method according to claim 1, wherein: a link quantity of the at least one first link and a link quantity of the at least one second link are determined by the first device, or a link quantity of the at least one first link and a link quantity of the at least one second link are determined by the first device based on a request of the second device(Venkatesan: Paragraph 33, Main link 130 includes four independent lanes (e.g., lane 231, lane 232, lane 233 and lane 234). It should be appreciated that main link 130 can include any number of lanes (e.g., more or less than four lanes). Link training can be provided to each lane independently).
Regarding claim 3, Chen and Venkatesan disclose link training method according to claim 1, wherein: the cable further comprises an auxiliary link, and the performing, by a first device, link training on [[the]] at least one first link comprises: sending a first rate to the second device through the auxiliary link, wherein the first rate is a link training rate of the at least one first link; and performing clock locking, equalization calculation, and link check on the at least one first link at the first rate when a parameter of the first transmit end is set to a first training parameter value(Venkatesan: Paragraph 24, (Venkatesan: Paragraph 33, Main link 130 includes four independent lanes (e.g., lane 231, lane 232, lane 233 and lane 234). It should be appreciated that main link 130 can include any number of lanes (e.g., more or less than four lanes). Link training can be provided to each lane independently).
Regarding claim 4, Chen and Venkatesan disclose link training method according to claim 3, wherein the performing clock locking, equalization calculation, and link check on the at least one first link comprises: sending a first clock recovery sequence to the second receive end through the first transmit end; receiving a first clock locking result from the second device through the auxiliary link, wherein the first clock locking result is that the clock locking succeeds or the clock locking fails; sending a first equalization sequence to the second receive end through the first transmit end when the first clock locking result is that the clock locking succeeds, wherein the first equalization sequence is used by the second device to perform equalization calculation; and receiving a first equalization calculation result or a first link check result from the second device through the auxiliary link, wherein the first equalization calculation result is that the equalization calculation fails, and the first link check result is that the link check succeeds or the link check fails(Venkatesan: Paragraphs 29-30: During link training, registers are read by source 110 to adjust the voltage swing and equalization, respectively. The implementation of registers extends the range and step size of the voltage swing and the step size of the equalization. Sink written registers 128 indicate the direction of the link training during the clock recovery and channel equalization).
Regarding claim 5, Chen and Venkatesan disclose link training method according to claim 4, wherein: the first clock locking result comprises a clock locking result of each of the at least one first link, and when a first link on which clock locking fails exists in the at least one first link, the first clock locking result is that the clock locking fails; or when no first link on which clock locking fails exists in the at least one first link, the first clock locking result is that the clock locking succeed(Venkatesan: Paragraphs 29-30: During link training, registers are read by source 110 to adjust the voltage swing and equalization, respectively. The implementation of registers extends the range and step size of the voltage swing and the step size of the equalization. Sink written registers 128 indicate the direction of the link training during the clock recovery and channel equalization).
Regarding claim 6, Chen and Venkatesan disclose link training method according to claim 5, wherein the parameter of the first transmit end comprises a voltage swing of each first link, and the link training method further comprises: determining whether a configuration of a voltage swing of the first link on which the clock locking fails in the at least one first link traverses all preset voltage swing values; in response to determining that the configuration of the voltage swing of the first link on which the clock locking fails in the at least one first link does not traverse all the preset voltage swing values, updating the configuration of the voltage swing of the first link on which the clock locking fails from a first value to a second value, wherein all the preset voltage swing values comprise the first value and the second value, and the second value is a value that has not been configured for the voltage swing of the first link on which the clock locking fails; and sending, to the second device through the auxiliary link, information indicating that configuration update of the voltage swing of the first link on which the clock locking fails is completed, wherein the first training parameter value comprises a voltage swing training value, and the first value is the voltage swing training value when the configuration of the voltage swing of the first link on which the clock locking fails is updated for the first time(Chen: Paragraph 42, a block 716, the PHY (Physical Layer) for the link goes into a negotiated data-rate mode with Tx and Rx equalization enabled. In a block 718 the Tx sweeps Rtx over a portion of the min-max design range for Rtx starting from the maximum value. For each Rtx step (in value), the channel is equalized for maximum eye opening at the receiver. As depicted in a block 722, when the received eye meets the performance metrics of the receiver, the Rtx calibration is completed. Generally, the performance metrics of the receiver will be one or more predefined metrics, such as specified in a standard for the link (e.g., PCIe 4.x, PCIe 5x, CXL 1.0, or any other communication link standard. In all or nearly all cases the Rtx value at which the received eye meets the performance metrics will be above the min Rtx value, thus the Tx sweep of the Rtx in block 718 will end up covering only a portion of the Rtx min-max design range).
Regarding claim 7, Chen and Venkatesan disclose link training method according to claim 4, wherein the first equalization calculation result comprises an equalization calculation result of each of the at least one first link, and when a first link on which equalization calculation fails exists in the at least one first link, the first equalization calculation result is that the equalization calculation fails(Venkatesan: Paragraphs 29-30: During link training, registers are read by source 110 to adjust the voltage swing and equalization, respectively. The implementation of registers extends the range and step size of the voltage swing and the step size of the equalization. Sink written registers 128 indicate the direction of the link training during the clock recovery and channel equalization).
Regarding claim 8, Chen and Venkatesan disclose link training method according to claim 7, wherein the first equalization calculation result further comprises a clock loss-of-lock status of each of the at least one first link, and the link training method further comprises: determining whether a first link on which a clock loss-of-lock occurs exists in the at least one first link; and in response to determining that the first link on which the clock loss-of-lock occurs exists in the at least one first link, sending the first rate to the second device through the auxiliary link, and sending the first clock recovery sequence to the second receive end through the first transmit end(Chen: Paragraph 42, a block 716, the PHY (Physical Layer) for the link goes into a negotiated data-rate mode with Tx and Rx equalization enabled. In a block 718 the Tx sweeps Rtx over a portion of the min-max design range for Rtx starting from the maximum value. For each Rtx step (in value), the channel is equalized for maximum eye opening at the receiver. As depicted in a block 722, when the received eye meets the performance metrics of the receiver, the Rtx calibration is completed. Generally, the performance metrics of the receiver will be one or more predefined metrics, such as specified in a standard for the link (e.g., PCIe 4.x, PCIe 5x, CXL 1.0, or any other communication link standard. In all or nearly all cases the Rtx value at which the received eye meets the performance metrics will be above the min Rtx value, thus the Tx sweep of the Rtx in block 718 will end up covering only a portion of the Rtx min-max design range).
Regarding claim 9, Chen and Venkatesan disclose link training method according to claim 8, wherein the parameter of the first transmit end comprises a transmit-end feedforward equalization parameter of each first link, and if no first link on which a clock loss-of-lock occurs exists in the at least one first link, and the link training method further comprises: determining whether a configuration of a transmit-end feedforward equalization parameter of the first link on which the equalization calculation fails in the at least one first link traverses all preset transmit-end feedforward equalization values; in response to determining that the configuration of the transmit-end feedforward equalization parameter of the first link on which the equalization calculation fails in the at least one first link does not traverse all the preset transmit-end feedforward equalization values, updating the configuration of the transmit-end feedforward equalization parameter of the first link on which the equalization calculation fails from a third value to a fourth value, wherein all the preset transmit-end feedforward equalization values comprise the third value and the fourth value, and the fourth value is a value that has not been configured for the transmit-end feedforward equalization parameter of the first link on which the equalization calculation fails; and sending, to the second device through the auxiliary link, information indicating that configuration update of the transmit-end feedforward equalization parameter of the first link on which the equalization calculation fails is completed, wherein the first training parameter value comprises a transmit-end feedforward equalization training value, and the third value is the transmit-end feedforward equalization training value when the configuration of the transmit-end feedforward equalization parameter of the first link on which the equalization calculation fails is updated for the first time(Chen: Paragraph 42, a block 716, the PHY (Physical Layer) for the link goes into a negotiated data-rate mode with Tx and Rx equalization enabled. In a block 718 the Tx sweeps Rtx over a portion of the min-max design range for Rtx starting from the maximum value. For each Rtx step (in value), the channel is equalized for maximum eye opening at the receiver. As depicted in a block 722, when the received eye meets the performance metrics of the receiver, the Rtx calibration is completed. Generally, the performance metrics of the receiver will be one or more predefined metrics, such as specified in a standard for the link (e.g., PCIe 4.x, PCIe 5x, CXL 1.0, or any other communication link standard. In all or nearly all cases the Rtx value at which the received eye meets the performance metrics will be above the min Rtx value, thus the Tx sweep of the Rtx in block 718 will end up covering only a portion of the Rtx min-max design range).
Regarding claim 10, Chen and Venkatesan disclose link training method according to claim 4, wherein the first link check result comprises a link check result of each of the at least one first link, and when a first link on which link check fails exists in the at least one first link, the first link check result is that the link check fails; or when no first link on which link check fails exists in the at least one first link, the first link check result is that the link check succeeds, and the link training on the at least one first link succeeds(Venkatesan: Paragraphs 29-30: During link training, registers are read by source 110 to adjust the voltage swing and equalization, respectively. The implementation of registers extends the range and step size of the voltage swing and the step size of the equalization. Sink written registers 128 indicate the direction of the link training during the clock recovery and channel equalization).
Regarding claim 11, Chen and Venkatesan disclose link training method according to claim 4, wherein the cable stores cable information of the cable, the first device stores device information of the first device, the second device stores device information of the second device, and the link training method further comprises: obtaining the device information of the first device, obtaining the cable information of the cable from the cable, and obtaining the device information of the second device from the second device through the auxiliary link; determining the first rate based on the device information of the first device, the cable information of the cable, and the device information of the second device; and determining the first training parameter value based on the first rate(Chen: Paragraph 42, a block 716, the PHY (Physical Layer) for the link goes into a negotiated data-rate mode with Tx and Rx equalization enabled. In a block 718 the Tx sweeps Rtx over a portion of the min-max design range for Rtx starting from the maximum value. For each Rtx step (in value), the channel is equalized for maximum eye opening at the receiver. As depicted in a block 722, when the received eye meets the performance metrics of the receiver, the Rtx calibration is completed. Generally, the performance metrics of the receiver will be one or more predefined metrics, such as specified in a standard for the link (e.g., PCIe 4.x, PCIe 5x, CXL 1.0, or any other communication link standard. In all or nearly all cases the Rtx value at which the received eye meets the performance metrics will be above the min Rtx value, thus the Tx sweep of the Rtx in block 718 will end up covering only a portion of the Rtx min-max design range).
Regarding claim 12, Chen and Venkatesan disclose method according to claim 11, wherein the link training method further comprises: storing at least one of the following information: the first rate, the cable information of the cable, the device information of the second device, a forward/reverse insertion status of the cable, or a configured value of the parameter of the first transmit end that is determined after the link training on the at least one first link succeeds((Venkatesan: Paragraph 34: a method 300 for adapting link training based on source capability information according to one embodiment. At step 310, equalization is initiated. In one embodiment, link training includes the process of clock recovery and channel equalization).
Claims 13-20 recite similar limitations as claims 1-12 and thus taught by Chen and Venkatesan, as explained above.
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
Applicant argues that Chen fails to disclose independent training. Examiner respectfully disagrees.
The Chen teaches in Paragraphs 29-32, start the downstream link training(first link), It is clear the first link training of the first link is independent of second link training. Start the upstream link(the claimed second link) training, while keeping the downstream link negotiated training and using it as a feedback channel. The process repeats as defined in phase 2 until successful upstream link is trained. After, first link training is done, second link training is subsequently initiated while the first link is operational. Thus, the training operations for the two links are temporally separate and independently performed. The completion of second link training is not required for the first link to operate and the second link training has its own calibration and evaluation procedure. Importantly , the claim language does not specify what is considered independent. Chen discloses sperate link training operations for the first and second links. The second link undergoes its own training procedure, including its own adjustments and evaluations, which is considered independent of the first link training operations. The claim should make clear that independence means that there is no reliance on parameters, feedback or results from the other link.
As for Applicant’s arguments that Venkatesan does not teach the newly added audio/video data in the claims, Examiner respectfully disagrees. As explained above, Venkatesan discloses link training via a cable, wherein the main link handles audio/video data from source to the sink(Paragraphs 20-21). Venkatesan discloses using an aux link as a feedback channel(Paragraph 16), which is similar in operation to Chens source to sink training on one channel in one direction and feedback on another channel in reverse direction. It would have been obvious to one ordinary skill in the art to combine the teachings of Chen and Venkatesan before the effective filing date of the claimed invention to link train via a cable, wherein the service data comprises video or audio data. The motivation to do so would be for two external devices to train and communicate.
Thus, Applicant’s arguments are not found persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMESH G PATEL whose telephone number is (571)272-3640. The examiner can normally be reached Monday-Friday, 8:15-4:15.
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/NIMESH G PATEL/Primary Examiner, Art Unit 2187
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