DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/26/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 and 15 are objected to because of the following informalities: Claim 1 recites “of its input” it appears this should be change to “of the input of the first modulator”. Claim 15 line 2 recites “at its first and second outputs” it appears this should be change to “at the/said first and second outputs of the first driver circuit”. Claim 15 line 6 recites “at its first and second outputs” it appears this should be change to “at the/said first and second outputs of the second driver circuit”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang US 2021/0328510.
Regarding Claim 1, Tang teaches (Figure 1-6) An apparatus (100) comprising: a controller (all 124, 122, 108 and 118) including: a first power stage (top buck converter) having an input and an output (inputs and output of the buck converter ); a second power stage (2nd buck converter) having an input and an output (input and outputs of the 2nd buck converter), the output of the first power stage coupled to the output of the second power stage (at Vout); a first modulator (108) having an input and an output, the first modulator configurable to provide a first modulated signal (PWM) at its output responsive to a state of its input (inputs of 108); the output of the first modulator coupled to the input of a first power stage (e.g. input Vin); a detector (all 122) having a current sense terminal (Cs) and a detector output (from 122); and a second modulator (all 124, 208 and 210) having a first input, a second input, and an output, the first input coupled to the output of the first modulator (receiving PWM signal), the second input coupled to the detector output (see fig. 2 with 124), the output of the second modulator coupled to the input of the second power stage (with 124, see fig. 2), and the second modulator is configurable to set an interval (delay) responsive to a state change of the detector output (see fig. 3 and 6), and provide the second modulated signal by delaying the first modulated signal by the interval (see fig. 3, par. 41-46 and 51). (For example: Par. 36-46 and 51)
Regarding Claim 2, Tang teaches (Figure 1-6) wherein the detector (122) is configurable to compare a current in a power converter (with 122) represented by a first signal at the current sense terminal with a second signal representing a reference current (par. 46), and set the state of the detector output responsive to a result of the comparison. (For example: Par. 36-46 and 51)
Regarding Claim 5, Tang teaches (Figure 1-6) wherein the detector ( 122) is configurable to set the detector output (from 122) from a first state to a second state (current state to next state) responsive to the current being equal to the reference current (par. 46), and the second modulator (all 124, 208 and 210) is configurable to set the interval responsive ( delay) to the detector output changing from the first state to the second state (see fig. 3 and 6, par. 41-46 and 51). (For example: Par. 64-85)
Regarding Claim 21, Tang teaches (Figures ) A method comprising: based at least in part on a feedback voltage (at vout) of a direct current (DC)-DC converter (at 104) and a reference voltage (at 114), providing a first modulated signal (PWM) to turn on a first transistor of a first half- bridge of a first power stage of the DC-DC converter (at 1st 106); comparing a current provided at a switching terminal of a second half-bridge of a second power stage of the DC-DC converter with a reference current (at 2nd 106 with 122, par. 46); and providing a second modulated signal (from 118) to turn on a second transistor of the second half-bridge (at 2nd 106) , based at least in part on delaying the first modulated signal by an interval (delay with 124, see Fig. 3 and 6; par. 41-46 and 51), the interval based at least in part on comparing the current (with 122); and combining outputs of the first and second power stages (see fig. 1). (For example: Par. 36-46 and 51)
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 6 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang US 2021/0328510 in view of Sinow US 2022/0255432.
Regarding Claims 3 and 23, Tang teaches (Figure 1-6) the apparatus.
Tang does not teach wherein the reference current is zero current.
Sinow teaches (Figure 1-9) wherein the reference current (Vzcd) is zero current (par. 113).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include w wherein the reference current is zero current, as taught by Sinow to high efficiency and low emi noise.
Regarding Claim 4, Tang teaches (Figure 1-6) the apparatus.
Tang does not teach wherein the detector has a voltage sense terminal, and the detector is configurable to set the reference current responsive to a voltage at the voltage sense terminal
Sinow teaches (Figure 1-9) wherein the detector (614, 622 and 644) has a voltage sense terminal (fig. 7, ZCD), and the detector is configurable to set the reference current responsive (sent to 614) to a voltage at the voltage sense terminal (with 1080). (For example: Par. 64-85)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include wherein the detector has a voltage sense terminal, and the detector is configurable to set the reference current responsive to a voltage at the voltage sense terminal, as taught by Sinow to high efficiency and low emi noise.
Regarding Claim 6, Tang teaches (Figure 1-6) the apparatus.
Tang does not teach wherein the detector has a voltage sense terminal, and the detector is configurable to set the detector output from the first state to the second state responsive to a voltage at the voltage sense terminal.
Sinow teaches (Figure 1-9) wherein the detector (614, 622 and 644) has a voltage sense terminal (zcd), and the detector is configurable to set the detector output (from 416) from the first state to the second state responsive to a voltage (Fig. 7 voltage at zcd terminal which generates the reference signal sent to 416) at the voltage sense terminal). (For example: Par. 64-85)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include wherein the detector has a voltage sense terminal, and the detector is configurable to set the detector output from the first state to the second state responsive to a voltage at the voltage sense terminal, as taught by Sinow to high efficiency and low emi noise.
Claim(s) 7 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang and Sinow and further in view of Mondal US 2022/0069712.
Regarding Claim 7, Tang teaches (Figure 1-6) the apparatus.
Tang does not teach wherein the voltage at the voltage sense terminal represents a voltage across a transistor of a half-bridge circuit of the power converter, and the detector is configurable to set the detector output from the first state to the second state responsive to the voltage at the voltage sense terminal being equal to zero.
Mondal teaches (Figures 1-8) wherein the voltage at the voltage sense terminal represents a voltage across a transistor (with zcd 222 or rcd 224) of a half-bridge circuit of the power converter (100), and the detector is configurable to set the detector output from the first state to the second state responsive to the voltage at the voltage sense terminal being equal to zero (determining the zcd or rcd condition). (For example: Par. 34-37)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include wherein the voltage at the voltage sense terminal represents a voltage across a transistor of a half-bridge circuit of the power converter, and the detector is configurable to set the detector output from the first state to the second state responsive to the voltage at the voltage sense terminal being equal to zero, as taught by Mondal to reduce efficiency losses in the system.
Regarding Claim 9, Tang teaches (Figure 1-6) the apparatus.
Tang does not teach wherein the half-bridge circuit is a first half-bridge circuit that is part of the first half bridge, and the apparatus further comprising: a first driver circuit having an input, a first output, and a second output, the input of the first driver circuit coupled to the output of the first modulator; a second driver circuit having an input, a first output, and a second output, the input of the second driver circuit coupled to the output of the second modulator; the first half-bridge circuit having control inputs coupled to the first and second outputs of the first driver circuit; and a second half-bridge circuit that is part of the second power stage having control inputs coupled to the first and second outputs of the second driver circuit.
Mondal teaches (Figures 1-8) wherein the half-bridge circuit (at 100) is a first half-bridge circuit (104-106) that is part of the first power stage, and the apparatus further comprising: a first driver circuit having an input, a first output, and a second output (at 212), the input of the first driver circuit coupled to the output of the first modulator (at 210, providing signal 213); a second driver circuit (at 214) having an input, a first output, and a second output, the input of the second driver circuit coupled to the output of the second modulator (at 210 producing 215); the first half-bridge circuit having control inputs coupled to the first and second outputs of the first driver circuit (gates of 104-106); and a second half-bridge (108-110) circuit that is part of the second power stage and having control inputs coupled to the first and second outputs of the second driver circuit (gates of 108-110). (For example: Par. 29-35)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include w wherein the half-bridge circuit is a first half-bridge circuit that is part of the first half bridge, and the apparatus further comprising: a first driver circuit having an input, a first output, and a second output, the input of the first driver circuit coupled to the output of the first modulator; a second driver circuit having an input, a first output, and a second output, the input of the second driver circuit coupled to the output of the second modulator; the first half-bridge circuit having control inputs coupled to the first and second outputs of the first driver circuit; and a second half-bridge circuit that is part of the second power stage having control inputs coupled to the first and second outputs of the second driver circuit, as taught by Mondal to reduce efficiency losses in the system.
Regarding Claim 10, Tang teaches (Figure 1-6) the apparatus.
Tang does not teach wherein the first half-bridge circuit is coupled to a first power terminal, the second half-bridge circuit is coupled to a second power terminal, the first half-bridge circuit has a first switching terminal, the second half-bridge circuit has a second switching terminal, and the apparatus further comprises an inductor coupled between the first and second switching terminals.
Mondal teaches (Figures 1-8) wherein the first half-bridge circuit (104-106) is coupled to a first power terminal (Vin), the second half-bridge circuit (108-110) is coupled to a second power terminal (Vbus), the first half-bridge circuit has a first switching terminal (sw1), the second half-bridge circuit has a second switching terminal (sw2), and the apparatus further comprises an inductor (L) coupled between the first and second switching terminals. (For example: Par. 34-37)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include wherein the first half-bridge circuit is coupled to a first power terminal, the second half-bridge circuit is coupled to a second power terminal, the first half-bridge circuit has a first switching terminal, the second half-bridge circuit has a second switching terminal, and the apparatus further comprises an inductor coupled between the first and second switching terminals, as taught by Mondal to reduce efficiency losses in the system.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sinow US 2022/0255432 in view of Tang US 2021/0328510.
Regarding Claim 17, Sinow teaches (Figure 1-9) A controller (110) comprising: a first modulator having (producing the PWM signal with Vo and Vref) a first modulator input to receive a power converter output voltage (Vo), (ii) a second modulator input to receive a reference voltage (Vref), and (iii) a first modulator output (outputting PWM signal), the first modulator configurable to provide a first pulse width modulation (PWM) signal at the first modulator output (par. 44); a current comparator (at 614) having (i) a current comparator input to receive a power converter switching terminal current (at Cs), and (ii) a current comparator output; and a second modulator (614) having (i) a third modulator input coupled to the current comparator output (see fig. 6), (ii) a fourth modulator input coupled to the first modulator output (pwm at 612), and (iii) a second modulator output (612 output), the second modulator configurable to set an interval responsive to a state of the current comparator output and provide a second PWM signal (output of 612) at the second modulator output by delaying the first PWM signal, (par. 75). (For example: Par. 64-85)
Sinow does not teach the second PWM signal having a start time delayed by the interval relative to the first PWM signal.
Tang teaches (Figure 1-6) the second PWM signal having a start time delayed by the interval relative to the first PWM signal.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Sinow to include the second PWM signal having a start time delayed by the interval relative to the first PWM signal, as taught by Tang to provide current balancing between the phases.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sinow and Tang and further in view of Lipcsei US 2004/0114398.
Regarding Claims 18-19, Sinow teaches (Figures 1-9) the controller which set an interval (par. 75).
Sinow does not teach a voltage comparator having (i) a voltage comparator input to receive a feedback voltage from the power converter, and (ii) a voltage comparator output that is coupled to the third modulator input of the second modulator, and the second modulator is configurable to set the interval responsive to a state change of the voltage comparator output; further comprising: a logical AND gate having (i) a first AND input coupled to the current comparator output, (ii) a second AND input coupled to the voltage comparator output, and (iii) an AND output coupled to the third modulator input.
Lipcsei teaches (Figures 1-2) a voltage comparator (cmp3) having (i) a voltage comparator input to receive a feedback voltage (vfb) from the power converter, and (ii) a voltage comparator output that is coupled to the third modulator input of the second modulator (at 242), and the second modulator is configurable to set the interval (on or off times) responsive to a state change of the voltage comparator output (from cmp3); further comprising: a logical AND gate (G2) having (i) a first AND input coupled to the current comparator output (CMP4), (ii) a second AND input coupled to the voltage comparator output (CMP3), and (iii) an AND output coupled to the third modulator input (at 242). (For Example: par. 35-44)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Sinow to include a voltage comparator having (i) a voltage comparator input to receive a feedback voltage from the power converter, and (ii) a voltage comparator output that is coupled to the third modulator input of the second modulator, and the second modulator is configurable to set the interval responsive to a state change of the voltage comparator output; further comprising: a logical AND gate having (i) a first AND input coupled to the current comparator output, (ii) a second AND input coupled to the voltage comparator output, and (iii) an AND output coupled to the third modulator input, as taught by Lipcsei in order to provide protection for unwanted conditions.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sinow and Tang and further in view of Liu US 2023/0336074 (herein Liu3).
Regarding Claim 20, Sinow teaches (Figure 1-9) the apparatus.
Sinow does not teach further comprising: a first delay and driver circuit having (i) a first driver input coupled to the first modulator output, (ii) a first driver output to provide a third PWM signal, and (iii) a second driver output to provide a fourth PWM signal; Anda second delay and driver circuit having (i) a second driver input coupled to the second modulator output, (ii) a third driver output to provide a fifth PWM signal, and (iii) a fourth driver output to provide a sixth PWM signal.
Liu3 teaches (Figures 1-5) further comprising: a first delay and driver circuit (80, 95 and 85) having (i) a first driver input coupled to the first modulator output (at PA ), (ii) a first driver output to provide a third PWM signal (S3), and (iii) a second driver output to provide a fourth PWM signal (S1); and a second delay and driver circuit (81, 96 and 86) having (i) a second driver input coupled to the second modulator output (at PB), (ii) a third driver output to provide a fifth PWM signal (S4), and (iii) a fourth driver output to provide a sixth PWM signal (S3). (For example: Par. 42-48)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Sinow to include further comprising: a first delay and driver circuit having (i) a first driver input coupled to the first modulator output, (ii) a first driver output to provide a third PWM signal, and (iii) a second driver output to provide a fourth PWM signal; and a second delay and driver circuit having (i) a second driver input coupled to the second modulator output, (ii) a third driver output to provide a fifth PWM signal, and (iii) a fourth driver output to provide a sixth PWM signal, as taught by Liu3 to achieving power saving.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Lipcsei US 2004/0114398.
Regarding Claim 22, Tang teaches (Figure 1-6) wherein the feedback voltage is a first feedback voltage (with Vout), the reference voltage is a first reference voltage (with 114).
Tang does not teach and the method further comprising: comparing a second feedback voltage with a second reference voltage; and providing the second modulated signal further based at least in part on comparing the second feedback voltage with the second reference voltage.
Lipcsei teaches (Figures 1-2) the method further comprising: comparing a second feedback voltage (Vfb) with a second reference voltage (slew); and providing the second modulated signal (G3, S2 and comp2) further based at least in part on comparing the second feedback voltage with the second reference voltage. (For Example: par. 35-44)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include the method further comprising: comparing a second feedback voltage with a second reference voltage; and providing the second modulated signal further based at least in part on comparing the second feedback voltage with the second reference voltage, as taught by Lipcsei in order to provide protection for unwanted conditions.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Endo US 2007/0018617.
Regarding Claim 24, Tang teaches (Figure 1-6) the method.
Tang does not teach wherein the reference current during a current switching cycle is based at least in part on a value of the current provided at the switching terminal during a third time occurring at a prior switching cycle, wherein during the third time, a voltage across a first current terminal and a second current terminal of the first transistor is zero.
Endo teaches (Figures 3-5) wherein the reference current (sent to Re and Ce) during a current switching cycle (n operation) is based at least in part on a value of the current provided at the switching terminal during a third time (one time of the operation of switch sw2) occurring at a prior switching cycle (n-1 operation), wherein during the third time, a voltage across a first current terminal and a second current terminal of the first transistor is zero (the comparator 31 takes into account different values of the terminals of sw2 including zero and controls the sw3 switch to produce the current signal sent to the resistors). (For Example: par. 73-75, 82-83, 88 and 93-94)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include wherein the reference current during a current switching cycle is based at least in part on a value of the current provided at the switching terminal during a third time occurring at a prior switching cycle, wherein during the third time, a voltage across a first current terminal and a second current terminal of the first transistor is zero, as taught by Endo in order to always actualize the zero-current switching and improve efficiency.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang in view of Liu US 2022/0140726.
Regarding Claim 25, Tang teaches (Figure 1-6) the method.
Tang does not teach averaging a summation of a first inductor current and a second inductor current of the DC-DC converter; and providing the first modulated signal based at least in part on the averaging.
Liu teaches (Figures 2-4) averaging a summation of a first inductor current and a second inductor current of the DC-DC converter (with 2031); and providing the first modulated signal (Ta1) based at least in part on the averaging. (For Example: par. 46-57)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Tang to include averaging a summation of a first inductor current and a second inductor current of the DC-DC converter; and providing the first modulated signal based at least in part on the averaging, as taught by Liu in order to avoid a constant and stable output voltage.
Allowable Subject Matter
Claims 8, 11-12 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 8; prior art of record fails to disclose either by itself or in combination: “…the voltage sense terminal is a first voltage sense terminal, the detector has a second voltage sense terminal, and the detector is configurable to set the detector output from the first state to the second state responsive to a second voltage at the second voltage sense terminal being equal to half of an input voltage or an output voltage of the power convert”.
Claim 11; prior art of record fails to disclose either by itself or in combination: “…wherein the first and second half-bridge circuits are coupled to a first power terminal, the first half-bridge circuit has a first switching terminal, the second half-bridge circuit has a second switching terminal, and the apparatus further comprises: a first inductor coupled between the first switching terminal and an intermediate terminal; a second inductor coupled between the second switching terminal and the intermediate terminal; and a third inductor coupled between the intermediate terminal and a second power terminal.”
Claim 15; prior art of record fails to disclose either by itself or in combination: “…wherein the first driver circuit is configurable to provide first and second control signals at its first and second outputs responsive to the first modulated signal and by inserting dead-times when both the first and second control signals are in a de-asserted state; and wherein the second driver circuit is configurable to provide third and fourth control signals at its first and second outputs responsive to the second modulated signal and by inserting dead- times when both the third and fourth control signals are in a de-asserted state.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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