DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-16) in the reply filed on 07/07/2026 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/07/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 5, claim 5 recites “wherein the at least one decoupling capacitor is disposed at a center of the top die. However, “disposed at the center” could mean two different things: 1) the actual center of the top die such that he decoupling capacitor is embedded in the top die or 2) where the center of the top die and the center of the decoupling capacitor lie along a line perpendicular to a top surface of the top die. Appropriate correction is required to clarify the language. For purposes of compact prosecution the Examiner interprets the claim language to be that of interpretation 2 offered above as this is supported by the Applicant’s drawings and written specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Alternately, Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Cheah et al. (US 2022/0068821) hereinafter “Cheah”.
Regarding claim 1, Fig. 5H of Cheah (when the page is turned upside down) teaches a semiconductor package, comprising: a top die (Item 542); first and second bottom dies (Items 536b, respectively) attached on a lower surface of the top die (Item 542) and being apart from each other (laterally) by a preset distance; and at least one decoupling capacitor (Item 536a) connected to the lower surface of the top die (Item 542) between the first bottom die (One of Item 536b) and the second bottom die (Another of Item 536b), wherein the top die (Item 542), the first bottom die (One of Item 536b) and the second bottom die (Another of Item 536b) are chiplets (Paragraph 0052).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Seidemann et al. (US 2019/0287904) hereinafter “Seidemann” in view of Marin et al. (US 2024/0128247) hereinafter “Marin” and in further view of Cheah et al. (US 2022/0068821) hereinafter “Cheah”.
Regarding claim 1, Fig. 1 of Seidemann (when the page is rotated 90 degrees to the left) teaches a semiconductor package, comprising: a top die (Item 10); first and second bottom dies (Items 11 and 12, respectively) attached on a lower surface of the top die (Item 10) and being apart from each other by a preset distance; and at least one passive device (Item 15) connected to the lower surface of the top die between the first bottom die (Item 11) and the second bottom die (Item 12).
Seidemann does not explicitly teach where the top die, the first bottom die, and the second bottom die are chiplets.
Marin teaches where chiplets (smaller sized IC dies) are used, where each chiplet is made using different manufacturing technologies and assembling them together into one microprocessor (Paragraph 0019).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the top die, the first bottom die and the second bottom die be chiplets because by having different parts of the overall design separated into different dies which are chiplets, each one optimized in terms of design and manufacturing, the overall yield and cost of the combined die solution may be improved (Marin Paragraph 0019).
Seidemann does not teach at least one decoupling capacitor connected to the lower surface of the top die between the first bottom die and the second bottom die.
Cheah teaches where a passive device (Item 236a) in a semiconductor package is a decoupling capacitor (Paragraph 0055).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the passive device of Seidemann be a decoupling capacitor because decoupling capacitors are known to be part of power delivery network in a semiconductor package with active devices (Cheah Paragraph 0017).
Regarding claim 2, Fig. 1 of Seidemann (when the page is rotated 90 degrees to the left) further teaches wherein a portion of upper surfaces of the first bottom die (Item 11) and the second bottom die (Item 12) face the top die (Item 10), and a remaining portion extends outwards on a plane of the top die (Item 10).
Regarding claim 3, Fig. 1 of Seidemann (when the page is rotated 90 degrees to the left) further teaches wherein entire upper surfaces of the first bottom die (Item 11) and the second bottom die (Item 12) face (See Examiner’s Note below) the top die (Item 10).
Examiner’s Note: The Examiner notes that the term “face” does not require that the first bottom die and the second bottom die are completely within an orthographic projection of the top die. Instead, both the first and second bottom die face a direction upward which is in the direction toward where the top die is located.
Regarding claim 4, Fig. 1 of Seidemann (when the page is rotated 90 degrees to the left) further teaches wherein the first bottom die (Item 11) and the second bottom die (Item 11) have a same size.
Regarding claim 5, Fig. 1 of Seidemann (when the page is rotated 90 degrees to the left) further teaches where the at least one passive device (which is a decoupling capacitor when combined with Cheah as stated in the rejection of claim 1 above) is disposed at a center of the top die (See 112(b) rejection of claim 5 above for interpretation).
Regarding claim 15, the combination of Seidemann, Marin and Cheah teaches all of the elements of the claimed invention as stated above.
Seidemann does not teach where a third bottom die is attached to the lower surface of the top die.
Fig. 5H of Cheah further teaches where three or more dies (Items 256b) are attached to a lower surface of the top die (Item 542).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a third bottom die be attached to the lower surface of the top die because additional dies may have additional functions which may be required by the overall package (Cheah Paragraph 0098).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Seidemann et al. (US 2019/0287904) hereinafter “Seidemann” in view of Marin et al. (US 2024/0128247) hereinafter “Marin” and Cheah et al. (US 2022/0068821) hereinafter “Cheah” and in further view of Patil et al. (US 2024/0063195) hereinafter “Patil”.
Regarding claim 6, the combination of Seidemann, Marin and Cheah teaches all of the elements of the claimed invention as stated above except where the first bottom die and the second bottom die have different sizes.
Patil teaches where different chiplets may have different sizes and or shapes (Paragraph 0045).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first bottom die and the second bottom die have different sizes because it is known that different chiplets may have different sizes such that they are configured to provide different functions with different interconnect densities (Patil Paragraph 0045).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Seidemann et al. (US 2019/0287904) hereinafter “Seidemann” in view of Marin et al. (US 2024/0128247) hereinafter “Marin” and Cheah et al. (US 2022/0068821) hereinafter “Cheah” and in further view of Zhai (US 2021/0125967) hereinafter “Zhai”.
Regarding claim 7, the combination of Seidemann, Marin and Cheah teaches all of the limitations of claim 1 as stated above except where the top die and the first and second bottom die are bonded to each other by a hybrid bonding.
Zhai teaches where dies are bonded to each other by hybrid bonding (Paragraph 0019).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the top die and the first and second bottom dies be bonded to each other by hybrid bonding because this type of bonding is known to achieve a high connection density (Zhai Paragraph 0019).
Regarding claim 8, the combination of Seidemann, Marin and Cheah teaches all of the limitations of claim 1 as stated above except where the top die and the first and second bottom die are bonded to each other by micro bump.
Zhai teaches where dies are bonded to each other by micro bump (Paragraph 0019).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the top die and the first and second bottom dies be bonded to each other by micro bump because this type of bonding is known to be a conventional bonding technique (Zhai Paragraph 0019).
Alternately, Claims 1 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 11,069,661) hereinafter “Chen” in view of Marin et al. (US 2024/0128247) hereinafter “Marin” and in further view of Cheah et al. (US 2022/0068821) hereinafter “Cheah”.
Regarding claim 1, Fig. 3 of Chen teaches a semiconductor package, comprising: a top die (Top Item 12); first and second bottom dies (Bottom Item 12 and Bottom Item 11, respectively) attached on (See Examiner’s Note below) a lower surface of the top die (Top Item 12) and being apart from each other by a preset distance (Where Bottom Item 12 and Bottom Item 11 are separated by a distance; See Examiner’s Note 2 below); and at least one decoupling capacitor (Top Item 11; Column 4, Lines 65-66) connected to (See Examiner’s Note 3 below) the lower surface of the top die (Top Item 12) between the first bottom die (Bottom Item 12) and the second bottom die (Bottom Item 11).
Chen does not explicitly teach where the top die, the first bottom die, and the second bottom die are chiplets.
Marin teaches where chiplets (smaller sized IC dies) are used, where each chiplet is made using different manufacturing technologies and assembling them together into one microprocessor (Paragraph 0019).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the top die, the first bottom die and the second bottom die be chiplets because by having different parts of the overall design separated into different dies which are chiplets, each one optimized in terms of design and manufacturing, the overall yield and cost of the combined die solution may be improved (Marin Paragraph 0019).
Chen does not teach where the capacitor is specifically a decoupling capacitor.
Cheah teaches where a passive device (Item 236a) in a semiconductor package is a decoupling capacitor (Paragraph 0055).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the capacitor of Chen be a decoupling capacitor because decoupling capacitors are known to be part of power delivery network in a semiconductor package with active devices (Cheah Paragraph 0017).
Examiner’s Note: The Examiner notes that “attached on” does not require direct contact with and allows for other intervening structures.
Examiner’s Note 2: The Examiner notes that “a preset distance” does not require that the distance be a distance in a direction parallel with a top surface of the top die and may be any distance (i.e diagonal, vertical, etc).
Examiner’s Note 3: The Examiner notes that “connected to” does not require direct contact and allows for intervening structures.
Regarding claim 9, Fig. 3 of Chen further teaches where a plurality of solder bumps (Item 13; Column 5, Lines 6-7) are provided on lower surfaces of the first bottom die (Bottom Item 12) and the second bottom die (Bottom Item 11).
Regarding claim 10, Fig. 3 of Chen further teaches a mold (Item 25) configured to encapsulate the top die (Top Item 12), the first bottom die (Bottom Item 12), the second bottom die (Bottom Item 11), and the at least one decoupling capacitor (Top Item 11), wherein an upper surface of the top die (Top Item 12) and lower surfaces of the first and second bottom dies (Bottom Items 12 and 11) are exposed (Where the first and second bottom dies are exposed [where the mold is not present] at portions where Item 14 and the solder balls Items 13 contact the respective first and second bottom dies).
Regarding claim 11, Fig. 3 of Chen further teaches where a redistribution layer (Item 10; Column 4, Lines 38-40) is bonded to the first bottom die (Bottom Item 12) and the second bottom die (Item 11) through the plurality of solder bumps (Item 13).
Examiner’s Note: The Examiner notes that “bonded to” does not require that the structures are directly contacting but instead allows for intervening structures.
Regarding claim 12, Fig. 3 of Chen further teaches a mold encapsulate (Item 16) all elements on an upper surface of the redistribution layer (Item 10).
Claims 13, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 11,069,661) hereinafter “Chen” in view of Marin et al. (US 2024/0128247) hereinafter “Marin” and Cheah et al. (US 2022/0068821) hereinafter “Cheah” and in further view of Gandhi et al. (US 2021/0366873) hereinafter “Gandhi”.
Regarding claim 13, the combination of Chen, Marin and Cheah teaches all of the elements of the claimed invention as stated above except a substrate bonded to a lower surface of the redistribution layer through the plurality of solder bumps, wherein a plurality of solder balls are provided on a lower surface of the substrate, and wherein an underfill is filled between the redistribution layer and the substrate.
Fig. 1 of Gandhi teaches a stacked structure of chiplets (Items 106) above a redistribution layer (Item 116) and a substrate (Item 134), where the substrate (Item 134) is bonded to a lower surface of the redistribution layer (Item 116) through a plurality of solder bumps (Items 118), wherein a plurality of solder balls (Item 140) are provided on a lower surface of the substrate (Item 134), and wherein an underfill (Item 150) is filled between the redistribution layer (Item 116) and the substrate (Item 134).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a substrate bonded to a lower surface of the redistribution layer through the plurality of solder bumps, wherein a plurality of solder balls are provided on a lower surface of the substrate, and wherein an underfill is filled between the redistribution layer and the substrate because the substrate provides support for the redistribution layer and stacked structure (Gandhi Paragraph 0032) and the solder balls below the substrate provide electrical signals through the substrate circuitry to the stack of chiplets (Gandhi Paragraph 0034).
Regarding claim 14, the combination of Chen, Marin and Cheah teaches all of the elements of the claimed invention as stated above.
Chen does not teach a power network established across the substrate, the redistribution layer, the first and second bottom dies, and the top die; and the at least one decoupling capacitor is connected in parallel to the power network.
Cheah teaches where a power network is established across a substrate, a redistribution layer, and various dies; and an at least one decoupling capacitor (Item 236a) is connected in parallel to the power network (Paragraph 0019).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a power network established across the substrate, the redistribution layer, the first and second bottom dies, and the top die; and the at least one decoupling capacitor is connected in parallel to the power network because this configuration is known to be part of a power delivery network in a semiconductor package with active devices (Cheah Paragraph 0017).
Regarding claim 16, the combination of Chen, Marin and Cheah teaches all of the elements of the claimed invention as stated above except where the top die is a logic die, and the first and second bottom dies are input and output dies.
Gandhi further teaches where a top die (Item 106) is a logic die (Paragraph 0024), where the logic die (Item 106) is above a lower input and output die (Item 104).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the top die is a logic die, and the first and second bottom dies are input and output dies because the I/O dies comprise routing circuitry to route electrical signals between a redistribution layer and logic devices above it (Gandhi Paragraph 0025).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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