Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Office Action is in response to the instant Application 18/476,004 filed on 9/27/2023. Claims 1-20 are pending. This Office Action is Non-Final.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 USC 101 as being directed to an abstract idea without being integrated into a practical application or being significantly more.
Regarding claims 1, 9 and 17, the claim recites the limitations “receiving, …, input data...;” “preparing,…, corresponding output data…;” and “returning, …, the corresponding output data.” Broadly interpreted, the aforementioned steps are directed to mental processes as said steps could be performed in the human mind. Therefore, the claims recite an abstract idea.
Said abstract idea and/or judicial exception is not integrated into a practical application as the claim does not recite any other active steps that could be considered that the abstract idea is being integrated into a practical application. It’s noted that the claim recites the operations “receiving input data,” “preparing an output,” and “returning an output.”
However, said operations are not sufficient to consider that the abstract idea is being interpreted into a practical application. Said operations are recited at a high level of generality in gathering/processing/storing information, which are a form of insignificant extra-solution activity.
It’s also noted that the claims recite additional limitation/elements (i.e., system, processing circuitry, processor, memory, etc.,). However, said additional elements are recited at a high-level of generality (i.e., as a generic computing device performing a generic computer functions) such that it amounts no more than mere instructions to apply the exception or abstract idea using generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claims do not include additional elements/limitations/embodiments that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea. As mentioned above, although the claims recite additional elements, said elements taken individually or as a combination, do not result in the claim amounting to significantly more than the abstract idea because as the additional elements perform generic computer content distributing functions routinely used in information technology field. As discussed above, the additional elements recited at a high-level of generality such that they amount no more than mere instructions to apply the exception using a generic computer component. Therefore, the claim is directed to non-statutory subject matter.
Regarding claims 2-8, 10-16 and 18-20, claims 2-8, 10-16 and 18-20 are also rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter for the same reasons addressed above as the claims recite an abstract idea and the claims do not positively recite any other operations that could be considered as the abstract idea is being integrated into a practical application or significantly more.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-7, 9, 12-15, 17 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Windh et al. (US 11,507,493).
As per claim 1, Windh discloses a computer-implemented method for simulating performance of a hardware offloading system, comprising: receiving, by a simulator that corresponds to a simulated architecture representing the hardware offloading system, input data from a user application for processing by the simulated architecture; preparing, by the simulator, corresponding output data for the input data without computing the corresponding output data by the simulated architecture (Windh, Col. 25 Lines 3-16 recites “At operation 1130, the state information may be used to configure a software simulator. For example, the state information, the set of instructions, and the like may be loaded into the software simulator. The software simulator is a cycle-accurate hardware simulator which uses a same application programming interface (API) as the hardware HTF. At operation 1135 the set of instructions may begin executing in the software simulator at the point of the stop condition. In some examples, the hardware HTF may also resume execution if the stop condition is a breakpoint, an assertion, or some exceptions. In some examples, some exceptions may not be recoverable and thus the thread execution may terminate permanently. To resume execution the host device may send a command to the HTF to continue.” And see Fig. 11);
and returning, by the simulator, the corresponding output data to the user application after a simulated idle time related to computing the corresponding output data by the simulated architecture (Windh, Col. 23 Lines 44-55 recites “By offloading hardware state information and by using software simulation tools that are initialized with the offloaded hardware state information, dataflow code may be debugged more effectively. Users may execute the code quickly on the hardware until near where the problem starts and then utilize slower, fine-grained simulation to identify the problem. The developer may utilize breakpoints or assertions with to halt the code executing on the hardware at this point, offload the hardware state, examine the hardware state at this point, and then, if necessary, step through the code using software simulation. The software simulator can be loaded with the hardware state saved from the hardware.”).
As per claim 4, Windh discloses the computer-implemented method of claim 1, Windh further discloses computing the simulated idle time based on a throughput metric associated with the simulated architecture (Windh, Col. 25 Lines 3-16 recites “At operation 1130, the state information may be used to configure a software simulator. For example, the state information, the set of instructions, and the like may be loaded into the software simulator. The software simulator is a cycle-accurate hardware simulator which uses a same application programming interface (API) as the hardware HTF. At operation 1135 the set of instructions may begin executing in the software simulator at the point of the stop condition. In some examples, the hardware HTF may also resume execution if the stop condition is a breakpoint, an assertion, or some exceptions. In some examples, some exceptions may not be recoverable and thus the thread execution may terminate permanently. To resume execution the host device may send a command to the HTF to continue.” And see Fig. 11).
As per claim 5, Windh discloses the computer-implemented method of claim 4, Windh further discloses wherein the simulated idle time is a function of the throughput metric and a size of the input data (Windh, Col. 25 Lines 3-16 recites “At operation 1130, the state information may be used to configure a software simulator. For example, the state information, the set of instructions, and the like may be loaded into the software simulator. The software simulator is a cycle-accurate hardware simulator which uses a same application programming interface (API) as the hardware HTF. At operation 1135 the set of instructions may begin executing in the software simulator at the point of the stop condition. In some examples, the hardware HTF may also resume execution if the stop condition is a breakpoint, an assertion, or some exceptions. In some examples, some exceptions may not be recoverable and thus the thread execution may terminate permanently. To resume execution the host device may send a command to the HTF to continue.” An instruction set would be the size of the input. And see Fig. 11).
As per claim 6, Windh discloses the computer-implemented method of claim 4, Windh further discloses configuring the throughput metric to achieve a performance metric in the simulated architecture (Windh, Col. 15 Line 51 – Col. 16 Line 2 recites “In an example, the example tile 504 can include a Spoke RAM. The Spoke RAM can be used to specify which input (e.g., from among the four SF tile inputs and the base tile input) is the primary input for each clock cycle. The Spoke RAM read address input can originate at a counter that counts from zero to Spoke Count minus one. In an example, different spoke counts can be used on different tiles, such as within the same HTF cluster 502, to allow a number of slices, or unique tile instances, used by an inner loop to determine the performance of a particular application or instruction set. In an example, the Spoke RAM can specify when a synchronous input is to be written to a tile memory, for instance when multiple inputs for a particular tile instruction are used and one of the inputs arrives before the others. The early-arriving input can be written to the tile memory and can be later read when all of the inputs are available. In this example, the tile memory can be accessed as a FIFO memory, and FIFO read and write pointers can be stored in a register-based memory region or structure in the tile memory.”).
As per claim 7, Windh discloses the computer-implemented method of claim 1, Windh further discloses wherein the simulator is executed by a first processor, and wherein the simulated architecture is associated with one or more second processors having a higher performance parameter than the first processor. (Windh, Col. 24 Lines 11-27 recites “FIG. 10 illustrates a logical diagram of obtaining state information of the tiles 1043 of an HTF 1042 according to some examples of the present disclosure. Memory device 1012 may be an example of a memory device 112 shown in FIG. 1; host 1008 may be an example of host system 108 of FIG. 1; HTF 1042 may be an example of HTF 142 of FIG. 1; and host processor 1022 may be an example of host processor 122 of FIG. 1. Tiles 1043 may execute one or more threads of instructions programmed by the host 1008. A control and status register (CSR) read request 1023 is sent by a memory interface processor 1011 of host 1008. This may be the result of a request from a simulator environment 1021, or may be sent automatically upon being notified of a stoppage of execution of one or more threads of instructions programmed by the host 1008.”).
Regarding claims 9 and 17, claims 9 and 17 are directed to an apparatus and a non-transitory computer-readable storage media associated with the method of claim 1. Claims 9 and 17 are of similar scope to claim 1, and are therefore rejected under similar rationale.
Regarding claims 12 and 20, claims 12 and 20 are directed to an apparatus and a non-transitory computer-readable storage media associated with the method of claim 4. Claims 12 and 20 are of similar scope to claim 4, and are therefore rejected under similar rationale.
Regarding claim 13, claim 13 is directed to a similar apparatus associated with the method of claim 5 respectively. Claim 13 is similar in scope to claim 5, respectively, and are therefore rejected under similar rationale.
Regarding claim 14, claim 14 is directed to a similar apparatus associated with the method of claim 6 respectively. Claim 14 is similar in scope to claim 6, respectively, and are therefore rejected under similar rationale.
Regarding claim 15, claim 15 is directed to a similar apparatus associated with the method of claim 7 respectively. Claim 15 is similar in scope to claim 7, respectively, and are therefore rejected under similar rationale.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 3, 10, 11, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Windh et al. (US 11,507,493) in view of Gasser et al. (US 11,226,885).
As per claim 2, Windh discloses the computer-implemented method of claim 1, but fails to teach wherein preparing the corresponding output data includes retrieving the corresponding output data from a memory, wherein the corresponding output data is computed during a previous run of the simulator and stored in the memory.
However, in an analogous art Gasser teaches wherein preparing the corresponding output data includes retrieving the corresponding output data from a memory, wherein the corresponding output data is computed during a previous run of the simulator and stored in the memory (Gasser, Col. 22 Lines 35-54 recites “At circle E, the distributions comparator 1010 transmits a request to the MCSS 130 to perform a simulation based on the new input distribution (e.g., via an API call as described above with reference to FIG. 4). In some embodiments, the request is to create a new template or a new version of a template specified with the template identifier(s) associated with the distributions comparator 1010 during configuration (e.g., via an API call as described above with reference to FIG. 2). In some embodiments, the MCSS 130 returns a new template identifier associated with the new or updated template. At circle F, the MCSS 130 creates a new template based on the existing template identified with the template identifier that has an updated location for the new input data distribution (e.g., either in the input distributions data store 315 or in the buffer data store 1005). The MCSS 130 then performs the Monte Carlo simulation as indicated by circles G and H-sampling, processing, and outputting an output data distribution to the output distributions data store 415 based in part on the new input distribution.”).
It would have been obvious to a person of ordinary skill in the art, at the earliest effective filing date to use Gasser’s Monte Carlo Simulation Monitoring And Optimization with Windh’s Debugging Dataflow Computer Architectures because it offers the advantage of using history data to help compare new simulated data.
As per claim 3, Windh in combination with Gasser teaches the computer-implemented method of claim 2, Gasser further teaches wherein the corresponding output data is mapped, in the memory, to the input data during the previous run of the simulator, and wherein preparing the corresponding output data includes retrieving the corresponding output data that is mapped to the input data (Gasser, Col. 22 Lines 35-54 recites “At circle E, the distributions comparator 1010 transmits a request to the MCSS 130 to perform a simulation based on the new input distribution (e.g., via an API call as described above with reference to FIG. 4). In some embodiments, the request is to create a new template or a new version of a template specified with the template identifier(s) associated with the distributions comparator 1010 during configuration (e.g., via an API call as described above with reference to FIG. 2). In some embodiments, the MCSS 130 returns a new template identifier associated with the new or updated template. At circle F, the MCSS 130 creates a new template based on the existing template identified with the template identifier that has an updated location for the new input data distribution (e.g., either in the input distributions data store 315 or in the buffer data store 1005). The MCSS 130 then performs the Monte Carlo simulation as indicated by circles G and H-sampling, processing, and outputting an output data distribution to the output distributions data store 415 based in part on the new input distribution.”).
It would have been obvious to a person of ordinary skill in the art, at the earliest effective filing date to use Gasser’s Monte Carlo Simulation Monitoring And Optimization with Windh’s Debugging Dataflow Computer Architectures because it offers the advantage of using history data to help compare new simulated data.
Regarding claims 10 and 18, claims 10 and 18 are directed to an apparatus and a non-transitory computer-readable storage media associated with the method of claim 2. Claims 10 and 18 are of similar scope to claim 2, and are therefore rejected under similar rationale.
Regarding claims 11 and 19, claims 11 and 19 are directed to an apparatus and a non-transitory computer-readable storage media associated with the method of claim 3. Claims 11 and 19 are of similar scope to claim 3, and are therefore rejected under similar rationale.
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Windh et al. (US 11,507,493) in view of Dubash (US 2023/0010063).
As per claim 8, Windh discloses the computer-implemented method of claim 1, but fails to teach receiving a direct memory access (DMA) information from the user application, wherein returning the corresponding output data to the user application is by DMA to the user application.
However, in an analogous art Dubash teaches receiving a direct memory access (DMA) information from the user application, wherein returning the corresponding output data to the user application is by DMA to the user application (Dubash, Paragraph 0060 recites “Similarly, the second peripheral system 530 contains elements that are being controlled/tested, responsive to signals produced by the second peripheral component 528. The processor 504 of the main computing system 502 processes signal data that it reads from the first dedicated memory space 510, and uses that signal data to generate additional signal data that it writes into the second dedicated memory space 512. In particular, there are a plurality of output values produced by the simulation application program being executed by the processor 504, and each one of these is written to an assigned location in the second dedicated memory space 512. The local processor of the second peripheral component 528 operates a DMA engine 536 that can directly access the second dedicated memory space 512, and write data from the second dedicated memory space 512 into corresponding locations in the local memory 534 of the second peripheral component 528.”).
It would have been obvious to a person of ordinary skill in the art, at the earliest effective filing date to use Dubash’s method and apparatus for cloning data among peripheral components and a main system with Windh’s Debugging Dataflow Computer Architectures because it offers the advantage of minimizing the CPU’s involvement in data transfers, which can lead to a more efficient use of processing resources.
Regarding claim 16, claim 16 is directed to a similar apparatus associated with the method of claim 8 respectively. Claim 16 is similar in scope to claim 8, respectively, and are therefore rejected under similar rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RODERICK TOLENTINO whose telephone number is (571)272-2661. The examiner can normally be reached Mon- Fri 8am-4pm.
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RODERICK . TOLENTINO
Examiner
Art Unit 2439
/RODERICK TOLENTINO/Primary Examiner, Art Unit 2439