Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the element package" in 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the element package" in 10. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chie et al. (JP2014204040) in view of Kim et al. (US 20220051972).
Regarding claim 1, Chie (e.g. fig. 2a) teaches an element package 21 comprising a plurality of arranged electronic elements 2, a molding portion 4 containing a molding material. The molding portion arranges for the molding material to surround the electronic elements, and a concave portion having arranged dimples 16 is disposed in some of the molding portion at the element package (see ¶0075).
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Chie does not teach that the element package 21 can be accommodated in a package substrate including a cavity as claimed. However, Kim (e.g. fig. 2) shows a packaging substrate 20 comprising a core layer comprising a glass core 21 and a cavity portion. The glass core is a glass substrate having a first surface and a second surface facing each other. The cavity portion has an accommodation space for accommodating an element package 40 as a part of the glass core is recessed or penetrated. Also, the element package is placed in the accommodation space of the cavity portion.
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It would have been obvious to one of ordinary skill in the art at the time of the invention to use the packaging substrate disclosed by Kim to accommodate within its cavity the element package disclosed by Chie since this packaging substrate can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard to be closer to each other so that electrical signals are transmitted through as short a path as possible as taught by Kim (see ¶0039). Also, since a glass substrate applied as a core of substrate is an insulator itself, there is a lower possibility of generating parasitic element compared to a conventional silicon core, and thus it is possible to simplify a process of treatment for an insulating layer and it is also applicable to a high-speed circuit (see ¶0040).
Regarding claim 2, Chie teaches that the dimple is disposed between the electronic elements adjacent to each other.
Regarding claim 3, Chie teaches that the concave portion comprise a plurality of dimples arranged in a dotted line shape in view of the direction from the first surface and the second surface (see fig. 7).
Regarding claim 4, Kim teaches an insulating layer 284 disposed on the cavity portion and the top portion of element package 40. The combination teaches that the insulating material of the insulating layer will recess in the dimples of the concave portion. Note that in Chie the concave portions are formed on the upper surface..
Regarding claim 5, Chie teaches that the molding material contains epoxy molding compound and/or modify polyimides (¶¶ 0026-0028; 0032).
Regarding claim 6, Kim teaches that the insulating layer comprises an insulating mixture of inorganic particles and a polymer resin (¶¶0143; 0149).
Regarding claim 7, Chie in view of Kim teaches that a boundary between the molding portion and the insulating layer is in the cavity portion. Also, the concave dimples are disposed in the direction of the electronic element. In this case, the insulating layer disclosed by Kim will conformally cover the upper surface of the element package disclosed by Chie.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chie et al. (JP2014204040) in view of Kim et al. (US 20220051972) and further in view of Shiobara et al. (US 5,166,228).
Regarding claim 12, Kim teaches a method of manufacturing the packaging substrate including the step of preparing a glass core with a cavity portion and an element package 40 (see ¶¶ 0215-0216; fig. 10). Also, Kim teaches the step of arranging the element package 40 in the cavity portion, and the step of forming an insulating layer 284 by placing an insulating material on the cavity portion. Chie in view of Kim teaches the packaging substrate according to claim 1 (see above). Chie in view of Kim does not teach the step of curing the resin. However, Shiobara teaches that among various resin compounds for encapsulating semiconductor devices, epoxy resin compositions comprising curable epoxy resins blended with curing agents and various additives are most widely used because they are generally improved in moldability, adhesion, electrical properties, mechanical properties and moisture resistance. It would have been obvious to one of ordinary skill in the art at the time of the invention to use an epoxy resin comprising curable epoxy resins blended with curing agents and various additives to ensure the disclosed resin have an adequate moldability, adhesion, electrical properties, mechanical properties and moisture resistance as taught by Shiobara. In this, case the step of curing the resin will be necessary to achieve the above mentioned goal.
Regarding claim 13, Chie in view of Kim further in view of Shiobara teaches that in the forming operation, the insulating material flows and a part of the insulating material moves to the concave dimples at the cavity portion. Note that the resin surrounds the element package 40.
Conclusion
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/Leonardo Andujar/
Primary Examiner
Art Unit 3991 CRU