Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-16 recite “die mounting area” which are “free of any semiconductor die” however there is no definition of how to determine if another device infringes on this claim, because dies can be mounted using solder or adhesive on metal or insulator surfaces, thus it is assumed that any place a die can be mounted is a “die mounting area”. The Examiner requests the Applicant to clarify the definition of “die mounting area” for the purpose of determining possible infringement.
Allowable Subject Matter
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 8, 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai et al. (US 20040007772 A1) hereafter referred to as Arai in view of Schwarzbauer (US 6175148 B1). Otremba et al. (US 20070216011 A1) hereafter referred to as Otremba is provided as evidence.
In regard to claim 1 Arai teaches a power electronic device [see Fig. 8A, Fig. 8B “FIG. 8B is a front view of the power semiconductor device of FIG. 8A”], comprising:
a carrier [see Fig. 8B see “collector electrode 3” and layers under it] comprising at least two [compare Fig. 8B to Fig. 4B “silicon semiconductor elements 12a, 12b of the second portion 28 are mounted onto a portion 3b of the electrode 3 via solder 14” “As compared with the power semiconductor device of the third embodiment, the both differ from each other in that only transistor 12a based on silicon is mounted on the second portion 28 side”] die mounting areas, each of the die mounting areas being configured to accept [see Fig. 4B both 12a and 12b can be mounted on electrode 3] a power semiconductor die;
at least one power semiconductor die [see Fig. 8B see “transistor 12a” is mounted] mounted on the carrier at a first one [see Fig. 8B see area in which 12a is mounted] of the die mounting areas, the power semiconductor die comprising a first side [bottom] and an opposite second side [top], wherein the first side faces [see Fig. 8B] the carrier, wherein a second one of the die mounting areas is free [see Fig. 8B see the area in which 12b is not mounted i.e. the location where 12b can be mounted is vacant] of any semiconductor die; and
but does not teach:
a contact clip arranged over the power semiconductor die and over the second die mounting area, the contact clip being at least partially arranged in a first plane,
wherein a first part of the contact clip over the power semiconductor die is bent downwards such that the first part is arranged in a second plane below the first plane and is coupled to the second side of the power semiconductor die,
wherein a second part of the contact clip over the second die mounting area is bent upwards such that the second part is arranged in a third plane above the first plane, or the second part is free of any bend such that the second part is arranged in the first plane.
See “The silicon transistor 12a is connected to the emitter electrode 4 and the gate electrode 5 by aluminum wires 16”.
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See Schwarzbauer teaches a clip with several planes, see reproduced above, for see title “Electrical Connection For A Power Semiconductor Component”, see Fig. 2 “Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is seen a contact clip 1, from which, in regions 2, electrical supplies 3 to solder lands 4 are formed by etching or laser cutting. (3) With reference to FIG. 2, the electrical supply 3 and the solder land 4 are located "underneath" the plane of the actual contact clip 1. This can be attained by an appropriate bending process after etching or laser cutting. (4) The contact clip 1, which represents a connecting clip for the electrical supply 3, the electrical supply 3, and the solder land 4 are produced from the same material and are composed, for example, of molybdenum or they comprise a tri-layer bimetallic sheet with a symmetrical layer sequence. This avoids any bimetallic effect with bending to one side. One such exemplary layer sequence is shown in FIG. 4. The sequence comprises a copper layer 5, an Invar layer 6, and a further copper layer 7. Invar is chosen since it has a particularly low coefficient of thermal expansion. (5) Referring again to FIG. 2, the contact clip 1 is passed between a copper layer 8 and a semiconductor body 9. The copper layer 8 is applied, for example using the DCB technique (DCB=direct copper bonding), onto a ceramic substrate 10, preferably composed of aluminum oxide, and is interrupted by a gap 11. The "left-hand" part of the copper layer 8 thus forms an electrode 12 for the semiconductor body 9” “As FIG. 3 shows, a filling 17 can be introduced into the area 18 between the contact clip 1 and the semiconductor body 9. This filling 17 is composed of an adhesive whose coefficient of thermal expansion is matched to the coefficient of thermal expansion of the semiconductor body 9 and of the contact clip 1. One suitable adhesive, for example, is a conventional flipchip filler. This allows any relative movement to be absorbed elastically, without deformation and fatigue of the solder points. (13) The invention thus provides an electrical connection for a power semiconductor component, which exhibits virtually no material fatigue, particularly at the solder points or soldered joints, even after large numbers of alternating load cycles”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Arai to include a clip instead of aluminum wires 16 i.e. to modify Arai to include a contact clip arranged over the power semiconductor die and over the second die mounting area, the contact clip being at least partially arranged in a first plane, wherein a first part of the contact clip over the power semiconductor die is bent downwards such that the first part is arranged in a second plane below the first plane and is coupled to the second side of the power semiconductor die, wherein a second part of the contact clip over the second die mounting area is bent upwards such that the second part is arranged in a third plane above the first plane, or the second part is free of any bend such that the second part is arranged in the first plane.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to get a rigid thick conductor which provides excellent conductance and virtually no material fatigue to get good electrical performance in power applications.
In regard to claim 2 Arai and Schwarzbauer as combined does not specifically teach further comprising:a molded body encapsulating the power semiconductor die, wherein the molded body electrically isolates the contact clip from the carrier.
However see Arai paragraph 0043 “power semiconductor elements 1, 2 are arranged in the portion 7 by pressure connection. A resin 24 is filled in the portion 7” “silicon carbide power semiconductor element 2 is enclosed within the plastic resin 24, and is operable at a temperature higher than 150.degree. C”.
See Schwarzbauer “As FIG. 3 shows, a filling 17 can be introduced into the area 18 between the contact clip 1 and the semiconductor body 9. This filling 17 is composed of an adhesive whose coefficient of thermal expansion is matched to the coefficient of thermal expansion of the semiconductor body 9 and of the contact clip 1. One suitable adhesive, for example, is a conventional flipchip filler. This allows any relative movement to be absorbed elastically, without deformation and fatigue of the solder points.”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Arai to include further comprising:a molded body encapsulating the power semiconductor die, wherein the molded body electrically isolates the contact clip from the carrier.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that encapsulation and underfill give good insulation and structural support.
In regard to claim 3 Arai and Schwarzbauer as combined teaches wherein within a circumference of the carrier, the molded body completely covers [see combination claim 2 the encapsulation/underfill allows connection to be made and surrounds the connection] an underside of the contact clip, and wherein the underside faces the carrier, except for those parts of the underside of the contact clip that are arranged over the at least one power semiconductor die.
In regard to claim 4 Arai and Schwarzbauer as combined teaches wherein a distal end of the contact clip is exposed from the molded body and forms [this is true, see Arai “The silicon transistor 12a is connected to the emitter electrode 4 and the gate electrode 5 by aluminum wires 16” , see combination wire is replaced by clip] an external contact of the power electronic device.
In regard to claim 8 Arai and Schwarzbauer as combined teaches further comprising:a second carrier [see Arai “The silicon transistor 12a is connected to the emitter electrode 4 and the gate electrode 5 by aluminum wires 16”, see combination Schwarzbauer the clip is connected to a different electrode i.e. “carrier”], wherein the contact clip electrically couples the at least one power semiconductor die to the second carrier.
In regard to claim 10 Arai and Schwarzbauer as combined does not specifically teach wherein a minimum distance between the carrier and the contact clip outside of the first part of the contact clip is 200 μm or more.
However see the Application is power semiconductor, and a person of ordinary skill in the art is aware that higher separation between electrodes gives higher voltage isolation for any given dielectric, including air.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein a minimum distance between the carrier and the contact clip outside of the first part of the contact clip is 200 μm or more ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 11 Arai and Schwarzbauer as combined does not specifically teach wherein a distance between the first plane and the second plane is 50 μm or more.
However see the Application is power semiconductor, and a person of ordinary skill in the art is aware that higher separation between electrodes gives higher voltage isolation for any given dielectric, including air.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein a distance between the first plane and the second plane is 50 μm or more ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 12 Arai and Schwarzbauer as combined does not specifically teach wherein a distance between the first plane and the third plane is equal to the distance between the first plane and the second plane.
However this is true if the “third plane” is the same plane as the “second plane”, thus under broadest reasonable interpretation, the second plane can be divided into two portions and one portion can be called as “second plane” and the other portion can be called as “third plane”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Arai to include wherein a distance between the first plane and the third plane is equal to the distance between the first plane and the second plane.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is simply ease of design by naming different portions as “second plane” and “third plane”.
In regard to claim 13 Arai and Schwarzbauer as combined teaches wherein the contact clip comprises [See Arai “silicon semiconductor elements 12a, 12b of the second portion 28 are mounted onto a portion 3b of the electrode 3 via solder 14” “collector electrode 3 and the emitter electrode 4 are generally made of copper having a high electric conductivity” i.e. semiconductor mounted on metal lead.
See Schwarzbauer “The contact clip 1, which represents a connecting clip for the electrical supply 3, the electrical supply 3, and the solder land 4 are produced from the same material and are composed, for example, of molybdenum or they comprise a tri-layer bimetallic sheet with a symmetrical layer sequence. This avoids any bimetallic effect with bending to one side. One such exemplary layer sequence is shown in FIG. 4. The sequence comprises a copper layer 5, an Invar layer 6, and a further copper layer 7”, thus under broadest reasonable interpretation, the contact clip comprises a leadframe part, because the contact clip and even electrode 3 looks like parts of a leadframe, see evidence Otremba paragraph 0035 teaches leadframe “chip carrier parts 11 and 12 are parts of a leadframe that additionally contains the leads 18 and 17. A first chip 13 and a third chip 15 are arranged on the first chip carrier part 11. A second chip 14 is arranged on the second chip carrier part 12” “According to an embodiment, if the first chip carrier part and the second chip carrier part are leads, the latter can be positioned in a simple manner by means of a leadframe, which makes the production process less expensive. The power semiconductor device preferably contains a housing composed of a molding composition which encloses the first chip, the second chip and at least one of the chip carrier parts. The molding composition not only serves for mechanical protection of the first and second chips, but also forms an electrical insulation in the interspaces between first and second chip carrier part, which are at different potentials of the supply voltage”] a leadframe part.
In regard to claim 14 Arai and Schwarzbauer as combined wherein the carrier comprises a substrate [see Arai Fig. 8B see “collector electrode 3” and layers under it are “carrier”, thus “collector electrode 3 and the emitter electrode 4 are generally made of copper having a high electric conductivity” “power semiconductor device 20 has a collector electrode 3 and an emitter electrode 4 that are extended from the first portion 26 to the second portion 28. The first portion 26 has a ceramic board 6, and a side 8 enclosing the ceramic board 6. The side 8 defines a space filled with a plastic resin” thus the substrate is “leadframe” or “direct copper bond” or “insulated metal substrate” under broadest reasonable interpretation, see evidence Otremba paragraph 0035 teaches leadframe “chip carrier parts 11 and 12 are parts of a leadframe that additionally contains the leads 18 and 17. A first chip 13 and a third chip 15 are arranged on the first chip carrier part 11. A second chip 14 is arranged on the second chip carrier part 12” “According to an embodiment, if the first chip carrier part and the second chip carrier part are leads, the latter can be positioned in a simple manner by means of a leadframe, which makes the production process less expensive. The power semiconductor device preferably contains a housing composed of a molding composition which encloses the first chip, the second chip and at least one of the chip carrier parts. The molding composition not only serves for mechanical protection of the first and second chips, but also forms an electrical insulation in the interspaces between first and second chip carrier part, which are at different potentials of the supply voltage”] of the type direct copper bond, direct aluminum bond, active metal braze, insulated metal substrate, or leadframe.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai and Schwarzbauer as combined and further in view of Chawla et al. (US 6046641 A) hereafter referred to as Chawla
In regard to claim 5 Arai and Schwarzbauer as combined does not specifically teach wherein the carrier comprises at least four die mounting areas, wherein the die mounting areas are arranged in an array, and wherein the contact clip is arranged over all of the at least four die mounting areas.
See Chawla “A power supply provides a DC source voltage (-V.sub.s) for the multiple-die power transistors, i.e., first and second kilowatt power transistor devices, or KPTs. Each such KPT device has a thermally and electrically conductive flange, e.g., a heat-sunk and grounded copper plate, and a multi-chip array formed, for example, of four semiconductor dies. Each semiconductor die has a flat lower surface with a drain region formed over a majority of its lower surface, and source and gate regions formed respectively on portions of the die away from said flat lower surface. The drains of the dies are seated on the flange so that they are in direct thermal and electrical contact with the flange. Thus, the flange serves as drain terminal and as heat sink for the associated dies” “With reference to FIGS. 4 and 5, a kilowatt power transistor 10 has a flat metal flange 12 or base, which mounts on a suitable heat sink (not shown) that can be formed as part of the chassis of an amplifier. The transistor here is a quad or four-chip array design, with four transistor chips or dies 14a, 14b, 14c, 14d mounted on the flange 12, and with their respective drain regions D grounded to the flange 12” “Each KPT Q1, Q2 forms one-half of the push-pull pair and has four high voltage MOSFET dies Q1A, Q1B, Q1C, Q1D, and Q2A, Q2B, Q2C, Q2D, respectively, whose drains are directly connected to ground via the associated copper flange 112. The source terminals of the dies for each respective KPT are direct paralleled, i.e., connected in parallel to form a 9 .OMEGA. impedance interface for each push-pull half” “gates are then paralleled”.
See Schwarzbauer “As has already been mentioned above, two solder points are provided in the present exemplary embodiment. However, more than two solder points and thus regions 2 with electrical supplies 3 and solder lands 4 can also be used”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Arai to include wherein the carrier comprises at least four die mounting areas, wherein the die mounting areas are arranged in an array, and wherein the contact clip is arranged over all of the at least four die mounting areas.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to increase power as desired by using a plurality of dies in parallel.
In regard to claim 6 Arai, Schwarzbauer and Chawla as combined does not specifically teach wherein a third one of the die mounting areas is free of any semiconductor die, wherein a third part of the contact clip over the third die mounting area is bent upwards such that the third part is arranged in the third plane, or the third part is free of any bend such that the third part is arranged in the first plane.
However see that in Schwarzbauer Fig. 2 it can be seen there is a third plane, and see combination Chawla, any number of dies can be mounted on the drain to obtain the desired power capability.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Arai to include wherein a third one of the die mounting areas is free of any semiconductor die, wherein a third part of the contact clip over the third die mounting area is bent upwards such that the third part is arranged in the third plane, or the third part is free of any bend such that the third part is arranged in the first plane.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is part reuse so that a support can have space for a plurality of dies and the number of dies chosen for desired power level and that third plane is useful for good electrical isolation.
In regard to claim 7 Arai, Schwarzbauer and Chawla as combined teaches [see combination Chawla in claim 6] wherein the power electronic device comprises at least two power semiconductor dies connected in parallel by the contact clip.
Claim(s) 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai et al. (US 20040007772 A1) hereafter referred to as Arai in view of Schwarzbauer (US 6175148 B1)
In regard to claim 15 Arai teaches a method for fabricating a power electronic device [see Fig. 8A, Fig. 8B “FIG. 8B is a front view of the power semiconductor device of FIG. 8A”], the method comprising:
providing a carrier [see Fig. 8B see “collector electrode 3” and layers under it] comprising at least two [compare Fig. 8B to Fig. 4B “silicon semiconductor elements 12a, 12b of the second portion 28 are mounted onto a portion 3b of the electrode 3 via solder 14” “As compared with the power semiconductor device of the third embodiment, the both differ from each other in that only transistor 12a based on silicon is mounted on the second portion 28 side”] die mounting areas, each of the die mounting areas being configured to accept [see Fig. 4B both 12a and 12b can be mounted on electrode 3] a power semiconductor die;
mounting at least one power semiconductor die [see Fig. 8B see “transistor 12a” is mounted] on the carrier at a first one [see Fig. 8B see area in which 12a is mounted] of the die mounting areas, the power semiconductor die comprising a first side [bottom] and an opposite second side [top], wherein the first side faces [see Fig. 8B] the carrier,leaving a second one of the die mounting areas free [see Fig. 8B see the area in which 12b is not mounted i.e. the location where 12b can be mounted is vacant] of any semiconductor die; and
but does not teach:
arranging a contact clip over the power semiconductor die and over the second die mounting area such that the contact clip is at least partially arranged in a first plane, wherein a first part of the contact clip over the power semiconductor die is bent downwards such that the first part is arranged in a second plane below the first plane and is coupled to the second side of the power semiconductor die,
wherein a second part of the contact clip over the second die mounting area is bent upwards such that the second part is arranged in a third plane above the first plane, or the second part is free of any bend such that the second part is arranged in the first plane.
See “The silicon transistor 12a is connected to the emitter electrode 4 and the gate electrode 5 by aluminum wires 16”.
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See Schwarzbauer teaches a clip with several planes, see reproduced above, for see title “Electrical Connection For A Power Semiconductor Component”, see Fig. 2 “Referring now to the figures of the drawing in detail and first, particularly, to FIG. 1 thereof, there is seen a contact clip 1, from which, in regions 2, electrical supplies 3 to solder lands 4 are formed by etching or laser cutting. (3) With reference to FIG. 2, the electrical supply 3 and the solder land 4 are located "underneath" the plane of the actual contact clip 1. This can be attained by an appropriate bending process after etching or laser cutting. (4) The contact clip 1, which represents a connecting clip for the electrical supply 3, the electrical supply 3, and the solder land 4 are produced from the same material and are composed, for example, of molybdenum or they comprise a tri-layer bimetallic sheet with a symmetrical layer sequence. This avoids any bimetallic effect with bending to one side. One such exemplary layer sequence is shown in FIG. 4. The sequence comprises a copper layer 5, an Invar layer 6, and a further copper layer 7. Invar is chosen since it has a particularly low coefficient of thermal expansion. (5) Referring again to FIG. 2, the contact clip 1 is passed between a copper layer 8 and a semiconductor body 9. The copper layer 8 is applied, for example using the DCB technique (DCB=direct copper bonding), onto a ceramic substrate 10, preferably composed of aluminum oxide, and is interrupted by a gap 11. The "left-hand" part of the copper layer 8 thus forms an electrode 12 for the semiconductor body 9” “As FIG. 3 shows, a filling 17 can be introduced into the area 18 between the contact clip 1 and the semiconductor body 9. This filling 17 is composed of an adhesive whose coefficient of thermal expansion is matched to the coefficient of thermal expansion of the semiconductor body 9 and of the contact clip 1. One suitable adhesive, for example, is a conventional flipchip filler. This allows any relative movement to be absorbed elastically, without deformation and fatigue of the solder points. (13) The invention thus provides an electrical connection for a power semiconductor component, which exhibits virtually no material fatigue, particularly at the solder points or soldered joints, even after large numbers of alternating load cycles”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Arai to include a clip instead of aluminum wires 16 i.e. to modify Arai to include arranging a contact clip over the power semiconductor die and over the second die mounting area such that the contact clip is at least partially arranged in a first plane, wherein a first part of the contact clip over the power semiconductor die is bent downwards such that the first part is arranged in a second plane below the first plane and is coupled to the second side of the power semiconductor die, wherein a second part of the contact clip over the second die mounting area is bent upwards such that the second part is arranged in a third plane above the first plane, or the second part is free of any bend such that the second part is arranged in the first plane.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to get a rigid thick conductor which provides excellent conductance and virtually no material fatigue to get good electrical performance in power applications.
In regard to claim 16 Arai and Schwarzbauer as combined does not specifically teach further comprising: encapsulating the power semiconductor die with a molded body such that within a circumference of the carrier, the molded body completely covers an underside of the contact clip, wherein the underside faces the carrier, except for those parts of the underside of the contact clip that are arranged over the at least one power semiconductor die.
However see Arai paragraph 0043 “power semiconductor elements 1, 2 are arranged in the portion 7 by pressure connection. A resin 24 is filled in the portion 7” “silicon carbide power semiconductor element 2 is enclosed within the plastic resin 24, and is operable at a temperature higher than 150.degree. C”.
See Schwarzbauer “As FIG. 3 shows, a filling 17 can be introduced into the area 18 between the contact clip 1 and the semiconductor body 9. This filling 17 is composed of an adhesive whose coefficient of thermal expansion is matched to the coefficient of thermal expansion of the semiconductor body 9 and of the contact clip 1. One suitable adhesive, for example, is a conventional flipchip filler. This allows any relative movement to be absorbed elastically, without deformation and fatigue of the solder points.”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Arai to include further comprising: encapsulating the power semiconductor die with a molded body such that within a circumference of the carrier, the molded body completely covers an underside of the contact clip, wherein the underside faces the carrier, except for those parts of the underside of the contact clip that are arranged over the at least one power semiconductor die.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that encapsulation and underfill give good insulation and structural support.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893