DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-7, 10-12, 18, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over MIPS ("Translation Look aside Buffer TLB") in view of Chang et al. (US 2016/0342526).
In regards to claim 1, MIPS teaches a device comprising:
a memory management unit (“The Translation Lookaside Buffer or TLB in a MIPS Processor is a cache of page table translations that allow the CPU to translate a virtual address to a physical address. “, slide 2) configured to:
receive, from a mapping instruction source, a mapping instruction to control address mappings (“EntryHi is read into the TLB entry using the TLB Write or TLB Write Random instructions.”, page 12) between virtual memory addresses and physical memory addresses (“The VPN is used to select the TLB entry with the correct Virtual Page Number. The TLB will then use that entry’s Physical Page number or PFN combined with the lower index bits of the virtual address to translate to the complete physical address.”, page 7), the mapping instruction specifying a mapping that maps a virtual memory address (See slide 6) to a physical memory address (See slide 9); and
generate a virtual-to-physical mapping entry including the mapping from the mapping instruction (“We can now write the new entry to the TLB using the TLB Write Random instruction.”, page 29; “PFN Physical Page Frame # translation even address EntryLo0/1”, page 5); and
store the virtual-to-physical mapping entry in a translation lookaside buffer (“We can now write the new entry to the TLB using the TLB Write Random instruction.”, page 29), wherein the virtual-to-physical mapping entry maps the virtual memory address to the physical memory address (“The VPN is used to select the TLB entry with the correct Virtual Page Number. The TLB will then use that entry’s Physical Page number or PFN combined with the lower index bits of the virtual address to translate to the complete physical address.”, page 7).
MIPS fails to teach that the mappings are between virtual memory addresses and physical memory address of a scratchpad memory. Chang teaches that the mappings are between virtual memory addresses and physical memory address of a scratchpad memory (“After receiving the virtual address 511, the TLB 520, for example, takes several bits in the virtual address 511 as a virtual page number, and finds one (herein referred to a first entry 640) of the entries according to the virtual page number. Some other bits in the virtual address 511 are taken as a tag to be compared with a tag in the first entry 640. If the tag in the virtual address 511 is the same with the tag in the first entry 640, it is called that the virtual address 511 is matched with the first entry 640. Then, the TLB 520 generates a physical address 522 according to the virtual address 511 and the physical page number recorded in the first entry 640, and the physical address 522 will be transmitted to the redirector 530.”, paragraph 0023; “The redirector 530 determines whether the physical address 522 belongs to an address space of the scratchpad memory 540. If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein”, paragraph 0024) because “the scratchpad memory has less power consumption” (paragraph 0005). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang such that the mappings are between virtual memory addresses and physical memory address of a scratchpad memory because “the scratchpad memory has less power consumption” (id.).
In regards to claim 2, MIPS further teaches that the mapping instruction specifies a range of said virtual memory addresses that are to be mapped to a respective range of physical memory addresses (“The Page Mask register allows TLB entries to map pages larger than 4K. The 1 bits in the page mask have the effect of causing the corresponding bit of the virtual address to be ignored when matching the TLB entry. Instead the bit is carried unchanged to the resulting physical address, effectively increasing the page size by a power of 4 for each mask bit up to 256MBs.”, page 13).
In regards to claim 4, MIPS further teaches a processing core (“The Translation Lookaside Buffer or TLB in a MIPS Processor is a cache of page table translations that allow the CPU to translate a virtual address to a physical address. “, slide 2) configured to execute the mapping instruction source to generate the mapping instruction to map the virtual memory address to the physical memory address (“If the TLB lookup fails - the CPU will signal an exception. The exception handler is then responsible for looking up the virtual address translation in the process’s page table and replacing an entry in the TLB with it.”, slide 7; “We can now write the new entry to the TLB using the TLB Write Random instruction.”, page 29).
In regards to claim 5, Chang further teaches that the processing core, the translation lookaside buffer, the scratchpad memory, and the memory management unit are implemented in hardware of an integrated circuit (“In the embodiment, the electronic device 500 includes a processing unit 510, a translation lookaside buffer (TLB) 520, a redirector 530, a scratchpad memory 540, a cache 550 and a recording circuit 560 in a chip 501.”, paragraph 0020).
In regards to claim 6, MIPS further teaches that the mapping instruction source is an operating system or application executed by the processing core (“The Context register is organized in such a way that the operating system can directly reference an 8-byte page table entry or PTE in memory.”, page 27);
the operating system or the application employs the virtual memory address (“When a process requests access to memory, the TLB translates the virtual address to a physical address where that data is actually stored.”, page 2); and
the processing core is configured as part of a central processing unit (“The Translation Lookaside Buffer or TLB in a MIPS Processor is a cache of page table translations that allow the CPU to translate a virtual address to a physical address.”, slide 2).
In regards to claim 7, MIPS further teaches a backing store maintained in main memory, the backing store configured to maintain mappings between virtual memory addresses and physical memory addresses (“Systems that need to map more memory pages than will fit into the TLB can use an in-memory Page Table.”, page 16). Chang further teaches volatile main memory (“In the embodiment, the external memory 570 is, for example, a dynamic random access memory.”, paragraph 0020).
In regards to claim 10, Chang further teaches static random access memory implementing the scratchpad memory (“In the embodiment, the scratchpad memory 540 and the cache 550 are, for example, static random access memories, but the invention is not limited thereto.”, paragraph 0025) to store data at the physical memory address (“When the processing unit 501 executes an instruction (e.g. ‘Store’ or ‘Load’ instruction) to access the memory, it sends a virtual address 511 to the TLB 520.”, paragraph 0022; “If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein, otherwise the physical address 522 is transmitted to the cache 550.”, paragraph 0024).
In regards to claim 11, MIPS teaches a system comprising:
a memory management unit (“There are different memory mappings depending on the state of the system and if you have a TLB or Fixed mapping MMU.”, page 4); and
a processing core (“The Translation Lookaside Buffer or TLB in a MIPS Processor is a cache of page table translations that allow the CPU to translate a virtual address to a physical address. “, slide 2) configured to:
generate a mapping instruction to control address mappings between virtual memory addresses and physical memory addresses of a memory (“We can now write the new entry to the TLB using the TLB Write Random instruction.”, page 29), the mapping instruction specifying a mapping that maps a virtual memory address (See slide 6) to a physical memory address of the memory (See slide 9), the mapping instruction instructing the memory management unit to generate a virtual-to-physical mapping entry including the mapping, and store the virtual-to-physical mapping entry in a translation lookaside buffer (“We can now write the new entry to the TLB using the TLB Write Random instruction.”, page 29; “PFN Physical Page Frame # translation even address EntryLo0/1”, page 5); and
generate a memory instruction to the memory, the memory instruction specifying the virtual memory address and instructing the memory management unit to transmit the memory instruction to the physical memory address of the memory to execute the memory instruction (“When a process requests access to memory, the TLB translates the virtual address to a physical address where that data is actually stored.”, page 2).
MIPS fails to teach that the memory is a scratchpad memory. Chang teaches that the memory is a scratchpad memory (“When the processing unit 501 executes an instruction (e.g. ‘Store’ or ‘Load’ instruction) to access the memory, it sends a virtual address 511 to the TLB 520.”, paragraph 0022; “Referring to FIG. 3 again, the redirector 530 is coupled to the TLB 520 and configured to receive the physical address 522. The redirector 530 determines whether the physical address 522 belongs to an address space of the scratchpad memory 540. If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein, otherwise the physical address 522 is transmitted to the cache 550.”, paragraph 0024) because “the scratchpad memory has less power consumption” (paragraph 0005). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang such that the memory is a scratchpad memory because “the scratchpad memory has less power consumption” (id.).
In regards to claims 12, Chang further teaches that the memory instruction is:
a load instruction to load data from the physical memory address of the scratchpad memory to the processing core (“When the processing unit 501 executes an instruction (e.g. ‘Store’ or ‘Load’ instruction) to access the memory, it sends a virtual address 511 to the TLB 520.”, paragraph 0022; “If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein, otherwise the physical address 522 is transmitted to the cache 550.”, paragraph 0024); or
a store instruction to store data from the processing core to the physical memory address of the scratchpad memory (“When the processing unit 501 executes an instruction (e.g. ‘Store’ or ‘Load’ instruction) to access the memory, it sends a virtual address 511 to the TLB 520.”, paragraph 0022; “If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein, otherwise the physical address 522 is transmitted to the cache 550.”, paragraph 0024).
In regards to claim 18, MIPS teaches a method comprising:
receiving, at a memory management unit, a mapping instruction to control address mapping (“EntryHi is read into the TLB entry using the TLB Write or TLB Write Random instructions.”, page 12; “The Translation Lookaside Buffer or TLB in a MIPS Processor is a cache of page table translations that allow the CPU to translate a virtual address to a physical address. “, slide 2) between virtual memory addresses and physical memory addresses of a memory (“The VPN is used to select the TLB entry with the correct Virtual Page Number. The TLB will then use that entry’s Physical Page number or PFN combined with the lower index bits of the virtual address to translate to the complete physical address.”, page 7), the mapping instruction specifying a mapping that maps a virtual memory address (See slide 6) to a physical memory address of the memory (See slide 9);
generating a virtual-to-physical mapping entry including the mapping from the mapping instruction (“We can now write the new entry to the TLB using the TLB Write Random instruction.”, page 29; “PFN Physical Page Frame # translation even address EntryLo0/1”, page 5);
storing the virtual-to-physical mapping entry in a translation lookaside buffer (“We can now write the new entry to the TLB using the TLB Write Random instruction.”, page 29); and
controlling access, by the memory management unit, of a memory instruction to the physical memory address (“The RI bit is the read inhibit bit. If set loads from page will cause an Read Inhibit exception. The XI bit is the Execute Inhibit bit. If set instruction fetches from page will cause an execute Inhibit exception.”, page 10) by translating the virtual memory address received via the memory instruction to the physical memory address based on the stored virtual-to-physical mapping entry in the translation lookaside buffer (“The VPN is used to select the TLB entry with the correct Virtual Page Number. The TLB will then use that entry’s Physical Page number or PFN combined with the lower index bits of the virtual address to translate to the complete physical address.”, page 7).
MIPS fails to teach that the address mappings are between virtual memory addresses and physical memory addresses of a scratchpad memory; and
translating the virtual memory address received via the memory instruction to the physical memory address of the scratchpad memory.
Chang teaches that the address mappings are between virtual memory addresses and physical memory addresses of a scratchpad memory (“After receiving the virtual address 511, the TLB 520, for example, takes several bits in the virtual address 511 as a virtual page number, and finds one (herein referred to a first entry 640) of the entries according to the virtual page number. Some other bits in the virtual address 511 are taken as a tag to be compared with a tag in the first entry 640. If the tag in the virtual address 511 is the same with the tag in the first entry 640, it is called that the virtual address 511 is matched with the first entry 640. Then, the TLB 520 generates a physical address 522 according to the virtual address 511 and the physical page number recorded in the first entry 640, and the physical address 522 will be transmitted to the redirector 530.”, paragraph 0023; “The redirector 530 determines whether the physical address 522 belongs to an address space of the scratchpad memory 540. If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein”, paragraph 0024); and
translating the virtual memory address received via the memory instruction to the physical memory address of the scratchpad memory (“After receiving the virtual address 511, the TLB 520, for example, takes several bits in the virtual address 511 as a virtual page number, and finds one (herein referred to a first entry 640) of the entries according to the virtual page number. Some other bits in the virtual address 511 are taken as a tag to be compared with a tag in the first entry 640. If the tag in the virtual address 511 is the same with the tag in the first entry 640, it is called that the virtual address 511 is matched with the first entry 640. Then, the TLB 520 generates a physical address 522 according to the virtual address 511 and the physical page number recorded in the first entry 640, and the physical address 522 will be transmitted to the redirector 530.”, paragraph 0023; “The redirector 530 determines whether the physical address 522 belongs to an address space of the scratchpad memory 540. If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein”, paragraph 0024)
because “the scratchpad memory has less power consumption” (paragraph 0005).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang such that the address mappings are between virtual memory addresses and physical memory addresses of a scratchpad memory; and
translating the virtual memory address received via the memory instruction to the physical memory address of the scratchpad memory
because “the scratchpad memory has less power consumption” (id.).
In regards to claim 21, MIPS further teaches that the memory management unit is further configured to:
receive a memory instruction that identifies the virtual memory address (“In the MIPS architecture, operating systems such as Linux use a section of memory called kuseg or Kernel / User segment for user processes. The addresses in this segment are called virtual address because they do not directly address physical memory.”, page 2); and
employ the translation lookaside buffer to translate the virtual memory address of the memory instruction to the physical memory address (“When a process requests access to memory, the TLB translates the virtual address to a physical address where that data is actually stored.”, page 2) using the virtual-to-physical mapping entry in the translation lookaside buffer (“The VPN is used to select the TLB entry with the correct Virtual Page Number. The TLB will then use that entry’s Physical Page number or PFN combined with the lower index bits of the virtual address to translate to the complete physical address.”, page 7).
Chang further teaches that the memory management unit is further configured to:
transmit the memory instruction to execute the memory instruction at the physical memory address of the scratchpad memory (“The redirector 530 determines whether the physical address 522 belongs to an address space of the scratchpad memory 540. If the physical address 522 belongs to the address space of the scratchpad memory 540, then the redirector 530 transmits the physical address 522 to the scratchpad memory 540 in order to access the data therein”, paragraph 0024).
In regards to claim 22, MIPS further teaches that the memory management unit is further configured to control access of a memory instruction to the physical memory address (“The RI bit is the read inhibit bit. If set loads from page will cause an Read Inhibit exception. The XI bit is the Execute Inhibit bit. If set instruction fetches from page will cause an execute Inhibit exception.”, page 10) by translating the virtual memory address received via the memory instruction to the physical memory address based on the stored virtual-to-physical mapping entry in the translation lookaside buffer (“The VPN is used to select the TLB entry with the correct Virtual Page Number. The TLB will then use that entry’s Physical Page number or PFN combined with the lower index bits of the virtual address to translate to the complete physical address.”, page 7).
In regards to claim 23, MIPS further teaches that the mapping instruction source is configured to control which address mappings are maintained in the translation lookaside buffer by generating the mapping instruction to add or remove the virtual-to-physical mapping entry (“This register is used write or read a particular TLB index (tlbwi/tlbr)”, slide 10).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over MIPS ("Translation Look aside Buffer TLB") in view of Chang et al. (US 2016/0342526) and Nishimoto et al. (US 6,092,172).
In regards to claim 3, MIPS in view of Chang teaches claim 1. MIPS in view of Chang fails to teach that the mapping instruction includes a coherence bit specifying a coherence behavior to manage data consistency at the physical memory address of the scratchpad memory, the coherence behavior specifying whether a write back behavior or a write through behavior is to be used for data maintained at the physical memory address of the scratchpad memory. Nishimoto teaches that the mapping instruction includes a coherence bit specifying a coherence behavior to manage data consistency at the physical memory address of the scratchpad memory, the coherence behavior specifying whether a write back behavior or a write through behavior is to be used for data maintained at the physical memory address of the memory (“The entry of the unified TLB 4 has the cache write mode bit WT to specify which one of the write-through and the write-back is used for the data cache memory 6.”, Col. 19, lines 55-57) in order that “the relation between the consistency of the cache memory and the external memory and the accessing speed can be optimized in accordance with the system construction and the contents of the process” (Col. 20, lines 4-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang and Nishimoto such that the mapping instruction includes a coherence bit specifying a coherence behavior to manage data consistency at the physical memory address of the scratchpad memory, the coherence behavior specifying whether a write back behavior or a write through behavior is to be used for data maintained at the physical memory address of the scratchpad memory in order that “the relation between the consistency of the cache memory and the external memory and the accessing speed can be optimized in accordance with the system construction and the contents of the process” (id.).
Claims 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over MIPS ("Translation Look aside Buffer TLB") in view of Chang et al. (US 2016/0342526) and Callister et al. (US 2007/0067602).
In regards to claim 8, MIPS in view of Chang teaches claim 7. MIPS in view of Chang fails to teach that the backing store supports context switches between processes executed by a respective processing core by swapping, between the translation lookaside buffer and the backing store, a first translation table of a first process including the virtual-to-physical mapping entry with a second translation table of a second process including one or more additional virtual-to-physical mapping entries. Callister teaches that the backing store supports context switches between processes executed by a respective processing core by swapping, between the translation lookaside buffer and the backing store, a first translation table of a first process including the virtual-to-physical mapping entry with a second translation table of a second process including one or more additional virtual-to-physical mapping entries (“A context unloading instruction stores information related to an outbound process being unloaded from the microprocessor 200 as part of a context switch.”, paragraph 0043; “A context unload instruction may perform the following actions as illustrated by method 300 in FIG. 3. … At 330 the instruction may, in response to detecting a touched field that indicates that a TLB entry was accessed by the outbound process, provide the virtual address in the TLB entry to the data store 250”, paragraph 0049; “A context loading instruction loads TLB information related to an inbound process being loaded into the microprocessor 200 as part of a context switch.”, paragraph 0042; “In one example, a context load instruction may perform the following actions as illustrated by method 400 in FIG. 4. At 410, the instruction may acquire at least a portion of a TLB entry from the data store 250 and may write the portion of the TLB entry into an entry in the TLB.”, paragraph 0052) in order to “facilitate mitigating some effects of cache and TLB misses related to process context switching in a multiprogramming, virtual memory computing system” (paragraph 0013). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang and Callister such that the backing store supports context switches between processes executed by a respective processing core by swapping, between the translation lookaside buffer and the backing store, a first translation table of a first process including the virtual-to-physical mapping entry with a second translation table of a second process including one or more additional virtual-to-physical mapping entries in order to “facilitate mitigating some effects of cache and TLB misses related to process context switching in a multiprogramming, virtual memory computing system” (id.).
In regards to claim 14, MIPS further teaches a backing store maintained in main memory, the backing store configured to maintain mappings between virtual memory addresses and physical memory addresses (“Systems that need to map more memory pages than will fit into the TLB can use an in-memory Page Table.”, page 16). Chang further teaches volatile main memory (“In the embodiment, the external memory 570 is, for example, a dynamic random access memory.”, paragraph 0020). MIPS in view of Chang fails to teach that the backing store is configured to maintain mappings to support context switches of processes executed by one or more respective processing cores. Callister teaches that the backing store is configured to maintain mappings to support context switches of processes executed by one or more respective processing cores (“Microprocessor 200 may also include a data store 250 that receives TLB information provided by the context unloading instructions and provides TLB information requested by the context loading instructions.”, paragraph 0045) in order to “facilitate mitigating some effects of cache and TLB misses related to process context switching in a multiprogramming, virtual memory computing system” (paragraph 0013). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang and Callister such that the backing store is configured to maintain mappings to support context switches of processes executed by one or more respective processing cores in order to “facilitate mitigating some effects of cache and TLB misses related to process context switching in a multiprogramming, virtual memory computing system” (id.).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over MIPS ("Translation Look aside Buffer TLB") in view of Chang et al. (US 2016/0342526) and Willis et al. (US 2002/0144079).
In regards to claim 9, MIPS in view of Chang teaches claim 7. MIPS in view of Chang fails to teach that the backing store supports virtualization of the mapping across processes executed by respective processing cores of a plurality of processing cores. Willis teaches that the backing store supports virtualization of the mapping across processes executed by respective processing cores of a plurality of processing cores (“For example, if a processor initiates a TLB request to look up a virtual address translation and the sharing indication corresponding to the retrieved TLB entry indicates a set of logical processes that does not include one associated with the processor initiating the TLB request, then the physical address data and other TLB data may be recovered from page tables in main memory. Control logic 704 may include a mechanism for recovering such data, or may invoke a mechanism such as a page walker to access page tables in memory and compute physical addresses. If the newly constructed virtual address translation matches the retrieved TLB entry, the requesting process may be added to the set of logical processes sharing the retrieved TLB entry.”, paragraph 0050; “Similarly a sharing indication corresponding to virtual address translation entry 719 indicates a shared status of S and a set of logical processes of 1111, indicating that entry 719 may be shared and used to translate virtual addresses for all four processors 710-780.”, paragraph 0047; See also figure 7a) because “it may be more efficient to physically share a resource among multiple processors while preserving the logical appearance of multiple single processors” (paragraph 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang and Willis such that the backing store supports virtualization of the mapping across processes executed by respective processing cores of a plurality of processing cores because “it may be more efficient to physically share a resource among multiple processors while preserving the logical appearance of multiple single processors” (id.).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over MIPS ("Translation Look aside Buffer TLB") in view of Chang et al. (US 2016/0342526), Callister et al. (US 2007/0067602), and Willis et al. (US 2002/0144079).
In regards to claim 16, MIPS in view of Chang and Callister teaches claim 14. MIPS in view of Chang and Callister fails to teach that the backing store supports the context switches of processes by supporting virtualization of the mapping across the processes executed by the one or more respective processing cores. Willis teaches that the backing store supports the context switches of processes by supporting virtualization of the mapping across the processes executed by the one or more respective processing cores (“For example, if a processor initiates a TLB request to look up a virtual address translation and the sharing indication corresponding to the retrieved TLB entry indicates a set of logical processes that does not include one associated with the processor initiating the TLB request, then the physical address data and other TLB data may be recovered from page tables in main memory. Control logic 704 may include a mechanism for recovering such data, or may invoke a mechanism such as a page walker to access page tables in memory and compute physical addresses. If the newly constructed virtual address translation matches the retrieved TLB entry, the requesting process may be added to the set of logical processes sharing the retrieved TLB entry.”, paragraph 0050; “Similarly a sharing indication corresponding to virtual address translation entry 719 indicates a shared status of S and a set of logical processes of 1111, indicating that entry 719 may be shared and used to translate virtual addresses for all four processors 710-780.”, paragraph 0047; See also figure 7a) because “it may be more efficient to physically share a resource among multiple processors while preserving the logical appearance of multiple single processors” (paragraph 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang and Willis such that the backing store supports the context switches of processes by supporting virtualization of the mapping across the processes executed by the one or more respective processing cores because “it may be more efficient to physically share a resource among multiple processors while preserving the logical appearance of multiple single processors” (id.).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over MIPS ("Translation Look aside Buffer TLB") in view of Chang et al. (US 2016/0342526) and O’Connor et al. (US 2006/0224857).
In regards to claim 24, MIPS in view of Chang teaches claim 1. MIPS in view of Chang fails to teach that the translation lookaside buffer is an instruction managed translation lookaside buffer that is separate from a hardware managed translation lookaside buffer included in the memory management unit, the instruction managed translation lookaside buffer and the hardware managed translation lookaside buffer searched in parallel in response to receiving a memory instruction that identifies the virtual memory address. O’Connor teaches that the translation lookaside buffer is an instruction managed translation lookaside buffer (software managed translation lookaside buffer 125, figure 1) that is separate from a hardware managed translation lookaside buffer (hardware managed translation lookaside buffer 130, figure 1) included in the memory management unit (memory management unit 110, figure 1), the instruction managed translation lookaside buffer and the hardware managed translation lookaside buffer searched in parallel in response to receiving a memory instruction that identifies the virtual memory address (“When a request for translation is passed to the TLBs 125 and 130, both TLBs may be consulted in parallel or sequentially.”, paragraph 0021) such that “the software's job of locking translations may be made simpler, in some embodiments, because it has a more flexible translation lookaside buffer to manage without having to be concerned about interaction with the hardware managed translation lookaside buffer” (paragraph 0023). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang and O’Connor such that the translation lookaside buffer is an instruction managed translation lookaside buffer that is separate from a hardware managed translation lookaside buffer included in the memory management unit, the instruction managed translation lookaside buffer and the hardware managed translation lookaside buffer searched in parallel in response to receiving a memory instruction that identifies the virtual memory address such that “the software's job of locking translations may be made simpler, in some embodiments, because it has a more flexible translation lookaside buffer to manage without having to be concerned about interaction with the hardware managed translation lookaside buffer” (id.).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over MIPS ("Translation Look aside Buffer TLB") in view of Chang et al. (US 2016/0342526) and Smith et al. (US 2018/0246816).
In regards to claim 25, MIPS in view of Chang teaches claim 1. MIPS in view of Chang fails to teach that the translation lookaside buffer is implemented as a circular buffer in which the address mappings are allocated and deallocated in order. Smith teaches that the translation lookaside buffer is implemented as a circular buffer in which the address mappings are allocated and deallocated in order (“More specifically, because any particular stream 212 explicitly instructs the TLB 210 regarding what translations are required, the simplest replacement policy—the replacement policy in which the TLB 210 treats entries 402 assigned to a stream 212 as a circular buffer—is sufficient. Treating the entries 402 as a circular buffer means that the TLB 210 writes entries in a contiguous fashion and, when the last entry 402 is written in a particular translation memory 218, the TLB 210 ‘wraps around’ to the first such memory.”, paragraph 0031) because it is the simplest replacement policy (id.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine MIPS with Chang and Smith such that the translation lookaside buffer is implemented as a circular buffer in which the address mappings are allocated and deallocated in order because it is the simplest replacement policy (id.).
Response to Arguments
Applicant's arguments filed 26 December 2025 with respect to claims 1, 11, and 18 have been fully considered but they are not persuasive. The Examiner recognizes that Chang does not teach a mapping instruction and that MIPS does not teach a scratchpad memory. However, in both instances, the other reference does teach those elements. Thus, one of ordinary skill in the art could combine MIPS’ teaching of a mapping instruction with Chang’s teaching of a mapping that maps a virtual memory address to a physical memory address of the scratchpad memory to teach the limitation in question.
Chang’s use of redirector 530 does not obviate the rejection. Rather, the redirector basically functions as a switch to route requests to either the scratchpad memory or the cache. The redirector can use the physical address to make this routing determination. Chang teaches “To be specific, since the scratchpad memory 540 has its own address space, the physical addresses of the scratchpad memory 540 are not overlapped with the physical addresses of the external memory 570. If the page P is moved to the scratchpad memory 540, and the page Q is moved to the external memory 570, then the page table is modified to reflect the physical address changes of the pages P and Q.” (paragraph 0035) The redirector does not place a physical address at a scratchpad. As shown in the previous quote, there are dedicated physical addresses for the scratchpad. Furthermore, the processor determines which pages are stored in the scratchpad (“Then, the processing unit 510 executes a data movement interrupt handler 503 to move the data corresponding to the physical address 522 to the scratchpad memory 540.”, paragraph 0029).
Applicant’s arguments filed 26 December 2025 with respect to claims 3 and 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hammond (US 5,940,872) teaches hardware and software managed TLBs.
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 14 January 2026