DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to an application filed on 09/28/2023.
Claims 1-20 are pending for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of copending Application No. 18/476,738. Although the claims at issue are not identical, they are not patentably distinct from each other because these are merely an obvious variation. In addition, the dependent claims 2-14 are rejected because of their dependency on independent claim 1. See the comparison table below for detailed analysis of independent claim 1.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application SN 18/476,723
Copending Application SN 18/476,738
Claim 1, A slew rate controllable system for powering an electric machine, comprising:
a plurality of power switches operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the electric machine, the power switches operable between an opened state and a closed state to facilitate generating the AC output; and
a gate drive system operable for controlling a slew rate associated with transitioning the power switches between the opened and closed states, the gate drive system including a plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches, the gate drive circuits including a plurality of resistors combinations available connectable to the gate terminal of the associated one of the power switches, wherein a selected resistor combination of the resistor combinations sets the slew rate for the switch associated therewith.
Claim 1, A slew rate controllable system for powering an electric machine, comprising:
a plurality of power transistors operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the electric machine, the power transistors operable between an opened state and a closed state to facilitate generating the AC output; and
a gate drive system operable for controlling a slew rate associated with transitioning the power transistors between the opened and closed states, the gate drive system including a plurality of gate drive circuits individually connected to a gate terminal of a corresponding one of the power transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Alam et al. (US 10,505,538 B1 and Alam hereinafter) in view of Fukushima et al. (US 2019/0238129 A1 and Fukushima hereinafter).
As to Claim 1, 15 and 18, Alam in its teachings as shown in Fig.1-10 disclose a system (10) /a method and an inverter module (24) for powering/controlling an electrical machine (26 and see also Col.5, Line 10-26), comprising:
a plurality of power switches (34, 134) operable for converting a direct current (22) input into an alternating current (via inverter module 24) output suitable for electrically powering the electric machine (26), the power switches (34,134) operable between an opened state and a closed state to facilitate generating the AC output (see Col.5, Line 35-37 and Col.6, Line 57-62); and
a gate drive system (50, 55) operable for controlling the power switches between the opened and closed states, the gate drive system (50, 55) including a plurality of gate drive circuits (30) individually connected to a gate terminal of an associated one of the power switches (34 or 134), the gate drive circuits including a plurality of resistors (Rg1, Rg2) combinations available connectable to the gate terminal of the associated one of the power switches (34 or 134) (see also Col.7, Line 22-Col.8, Line 10)
Although the microcontroller 50 uses the circuit measurements to calculate/select corresponding switching control values and Gate resistor identities, and to transmit, as part of the output signals (11), binary on/off switching control signals and a Gate resistor selection signal (13) to the switching circuits/gate driver system 55 (see also Col.7, Line 15-20), it doesn’t explicitly disclose a gate drive system operable for controlling:
a slew rate associated with transitioning the power switches between the opened and closed states and wherein a selected resistor combination of the resistor combinations sets the slew rate for the switch associated therewith
Nonetheless, Fukushima in its teachings as shown in Fig.1-10 disclose a gate driver circuit (DRV1) includes a pull-up circuit (PU1) and a pull-down circuit (PD1) that share an output node (external terminal (T3)), where a signal (DI1 (DI2)) input to the pull-up circuit (PU1) and a signal (DI3) input to the pull-down circuit (PD1) are selected in a complementary manner, and the output node outputs an output signal in which rising time and falling time of the signals (DI1 (DI2) and DI3) are adjusted in accordance with on-off operation of the signals, in which the rising time is adjusted by transistors (M1 and M2) and a resistor (R1), while the falling time is adjusted by transistors (M3, M4 and M5) and a resistor (R2) (see [Abstract], [0025], [0029] and [0039])
Therefore, it would have been an obvious modification before the effective filing date of the instant application for a gate driver system to be operable for controlling a slew rate associated with transitioning the power switches between the opened and closed state as thought by Fukushima within the teachings of Alam in order to provide a driver circuit that can change slew rate (see [0008]). In addition, a gate drive system controls a switch's slew rate (switching speed) using selectable resistors to balance energy efficiency (fast switching) against EMI reduction and component stress (slow switching) and selecting specific resistors in the driver circuit modifies the gate charging current, enabling tailored, efficient power management.
As to Claim 2, Alam in view of Fukushima disclose the slew rate controllable system according to claim 1, wherein: the gate drive system (50, 55) includes a gate controller operable for determining the selected resistor combination for each power switch to optimize the slew rate (see Alam Col.11, Line 3-17).
As to Claim 3, Alam in view of Fukushima disclose the slew rate controllable system according to claim 2, wherein: the gate drive system includes a gate driver (30) operable for providing the gate drive circuits with a control signal suitable for implementing the selected resistor combination and controlling the power switches to generate the AC output (see Alam Col.11, Line 3-17).
As to Claim 4, Alam in view of Fukushima disclose the slew rate controllable system according to claim 3, wherein: the control signals (11) are operable for directing the gate drive circuits to control a gate-source voltage between the gate terminal and a source terminal of the switch associated therewith, the Vgs controlling the power switches between the opened and closed states (see Alam Col.7, Line 22-43).
As to Claim 5, 17 and 20, Alam in view of Fukushima disclose the slew rate controllable system according to claim 4, the method according to claim 16 and the power inverter module according to claim 19, wherein: a quantity of the resistors for each of the gate drive circuits equals K (HR1, HR2 and LR1,LR2), with a K/2 quantity of the resistors corresponding with upper resistors (HR1, HR2) and a K/2 quantity of the resistors corresponding with lower resistors (LR1,LR2), the upper resistors connecting in series with the lower resistors, with the gate terminal associated therewith connecting between each of the upper and lower resistors (see Fukushima Fig.3 and [0039]-[0040]).
As to Claim 16, Alam in view of Fukushima disclose the method according to claim 15, further comprising: determining the selected slew rate as a function of one or more of a DC voltage of a DC source providing the DC input, a temperature of a DC link capacitor connected to the DC input, a current of the AC output and a junction temperature, a maximum discharge time, a drain-source voltage, or a voltage threshold of one or more of the power switches (see Alam: Col.9, Line 63- Col.10, Line 27 and also Fukushima: [0039]).
As to Claim 19, Alam in view of Fukushima disclose the power inverter module according to claim 18, wherein: the gate drive system (50,55) generates pulse width modulated (PWM) signals for controlling a plurality of gate switches of the gate drive circuits (30) to control the slew rate and the AC output, the PWM signals operable between a high voltage and a low voltage, the high voltage transitioning the gate switch in receipt thereof to the opened state and the low voltage transitioning the gate switch in receipt thereof to the closed state (see Alam: Col.9, Line 63- Col.10, Line 27 and also Fukushima: [0039]).
Allowable Subject Matter
Claims 6-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In view of the limitations the closest prior art including the prior works of the assignee/inventor does not explicitly describe or reasonably suggest or render obvious in combination with all the given limitations the slew rate controllable system according to claim 5, wherein: the resistors for each of the gate drive circuits are arranged into a K/2 quantity of branches, with each branch including one of the upper resistors and one of the lower resistors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (US 2019/0157993 A1: Provides a BLDC motor for a vehicle. The electric motor includes a stator, a rotor, and a plurality of independent bridge drivers. The motor may include two bridge drivers, and each may be a B6 bridge driver. Each bridge driver supplies a portion of current to the electric motor. There may be a phase shift between the two bridge drivers and the bridge drivers may be operable to decrease a ripple current of the current provided to the electric motor. Optionally, each bridge driver delivers current at a slew rate that is different from each other independent bridge driver – see [0004]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL T AGARED whose telephone number is (571)270-1981. The examiner can normally be reached 8-5 (Mon- Thur).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eduardo Colon-Santana can be reached at 5712722060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GABRIEL AGARED/Primary Examiner, Art Unit 2846
Prosecution Insights