DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhira (US 20240204776) in view of Morris (US 9869722) and further in view of Somayajula et al. (US 20230194593).
Claim 1; Mitsuhira disclose a plurality of power transistors (M1, M2) operable for converting a direct current (VDD) input into an alternating current (AC) output suitable for electrically powering the electric machine (301), the power transistors operable between an opened state and a closed state to facilitate generating the AC output; and a gate drive system (101) operable for controlling a slew rate associated with transitioning the power transistors between the opened and closed states, the gate drive system including a plurality of gate drive circuits (40H, 50H, 40L, 50L) individually connected to a gate terminal of a corresponding one of the power transistors (M1, M2).
However, Mitsuhira does not disclose a DC link capacitor connected in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors.
Morris teaches a controller that operates on one or more sensed and/or computed values for producing control signals to drive the switches. The sensed and computed values may further include one or more diode junction-case temperatures 202, filter capacitor temperatures 204, filter capacitor voltages 206, DC bus capacitor temperatures 208, DC bus capacitor voltages 210, fan speed value 212, air temperature 213, and power module base plate temperature 215.
Moreover, Somayajula et al. teach various parameters or values of the system, such as the control system of FIG. 1, are acquired. In one example, the values are the DC-link capacitor voltage Vdc, the three-phase voltages Va, Vb, Vc, the three-phase currents Ia, Ib, Ic, and the junction temperatures of the switching devices. Such values are used to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Mitsuhira to include a DC link capacitor, as taught by Morris and Somayajula et al. to smooth the input voltage and connect it in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors as taught by Morris or Somayajula et al. in order to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Claim 2; Mitsuhira disclose the control signals optimize the slew rate and controlling the power switches to generate the AC output (para [0086], [0089], [0092)).
Claim 3; Mitsuhira, e.g. figures 2 and 3.
Claim 15; Mitsuhira disclose a plurality of power switches (M1, M2) operable for converting a direct current (VDD) input into an alternating current (AC) output suitable for electrically powering the traction motor (301), the power switches operable between an opened state and a closed state to facilitate generating the AC outputs; and a gate drive system (101) operable for controlling a slew rate associated with transitioning the power switches between the opened and closed states (para [0086], [0089], [0092]), the gate drive system including a plurality of gate drive circuits (e.g. 40H, 50H, 40L, 50L) individually connected to a gate terminal of a corresponding one of the power switches (M1, M2), the gate drive circuits being operable for controlling a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power switch associated therewith, the Vgs controlling the power switches between the opened and closed states (e.g. figures 2 and 3).
However, Mitsuhira does not disclose a DC link capacitor connected in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors.
Morris teaches a controller that operates on one or more sensed and/or computed values for producing control signals to drive the switches. The sensed and computed values may further include one or more diode junction-case temperatures 202, filter capacitor temperatures 204, filter capacitor voltages 206, DC bus capacitor temperatures 208, DC bus capacitor voltages 210, fan speed value 212, air temperature 213, and power module base plate temperature 215.
Moreover, Somayajula et al. teach various parameters or values of the system, such as the control system of FIG. 1, are acquired. In one example, the values are the DC-link capacitor voltage Vdc, the three-phase voltages Va, Vb, Vc, the three-phase currents Ia, Ib, Ic, and the junction temperatures of the switching devices. Such values are used to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Mitsuhira to include a DC link capacitor, as taught by Morris and Somayajula et al. to smooth the input voltage and connect it in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors as taught by Morris or Somayajula et al. in order to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Claim 17; Mitsuhira, e.g. figures 2 and 3.
Claim(s) 1-3 and 7-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukushima et al. (US 20190238129) in view of Morris and further in view of Somayajula et al.
Claim 1; Fukushima et al. disclose a plurality of power transistors (PN1, PN2) operable for converting a direct current (Vin) input into an alternating current (AC at load RL; para [0003]) output suitable for electrically powering the electric machine (RL), the power transistors operable between an opened state and a closed state to facilitate generating the AC output; and a gate drive system (30) operable for controlling a slew rate (e.g. para. [0008]) associated with transitioning the power transistors between the opened and closed states, the gate drive system including a plurality of gate drive circuits (e.g. HDRV1, LDRV1) individually connected to a gate terminal of a corresponding one of the power transistors (PN1, PN2).
However, Fukushima et al. do not disclose a DC link capacitor connected in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors.
Morris teaches a controller that operates on one or more sensed and/or computed values for producing control signals to drive the switches. The sensed and computed values may further include one or more diode junction-case temperatures 202, filter capacitor temperatures 204, filter capacitor voltages 206, DC bus capacitor temperatures 208, DC bus capacitor voltages 210, fan speed value 212, air temperature 213, and power module base plate temperature 215.
Moreover, Somayajula et al. teach various parameters or values of the system, such as the control system of FIG. 1, are acquired. In one example, the values are the DC-link capacitor voltage Vdc, the three-phase voltages Va, Vb, Vc, the three-phase currents Ia, Ib, Ic, and the junction temperatures of the switching devices. Such values are used to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Fukushima et al. to include a DC link capacitor, as taught by Morris and Somayajula et al. to smooth the input voltage and connect it in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors as taught by Morris or Somayajula et al. in order to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Claim 2; Fukushima et al.: HDLY1, HDLY2, LDLY1, LDLY2, etc.
Claim 3; Fukushima et al.: e.g. PN1, VDS, and PN2, VDS; HG2 and LG2.
Claim 7; Fukushima et al. disclose the gate drive circuits include an upper drive switch (HM2), an upper resistor (HR1), a lower resistor (HR2) and a lower switch (HM5), the upper resistor and the lower resistor connecting in series between the upper drive switch (HM2) and the lower driver switch (HM5), with the gate terminal (HG1) associated therewith connecting between a lower side of the upper resistor (HR1) and an upper side of the lower resistor (HR2).
Claim 8; Fukushima et al. disclose the gate drive system includes an upper voltage source (Vboot/Vreg) and a lower voltage (gnd) source for each of the gate drive circuits, with the upper voltage source connected to the upper switch (e.g. HM2/LM2) and the lower voltage source connected to the lower switch (e.g. HM5, LM5) associated therewith.
Claim 9; Fukushima et al.: e.g. gate voltages (HG1, LG1) at gate terminals (T3, T5).
Claim 10; Fukushima et al.: e.g. [0008], [0025], [0026], [0029], [0030], etc.
Claims 11 and 12; Fukushima et al.: e.g. [0061]-[0063], etc.
Claim 13; Fukushima et al. disclose the gate drive circuits includes an upper voltage source (e.g. VBoot), a lower voltage source (gnd), an upper switch (HM2), a lower switch (HM5) and an upper resistor (HR1), the upper switch (HM2) connecting in series with the upper voltage source (VBoot) and to an upper side of the upper resistor (HR1), the lower switching (HM5) connecting in series with the lower voltage source (gnd) and a lower side of the upper resistor (HR1, thru HR2), the gate terminal (T3) associated therewith connecting to the lower side of the upper resistor (HR1).
Claim 14; Fukushima et al. disclose the gate drive circuits includes an upper voltage source (VBoot), a lower voltage source (gnd), an upper switch (HM2), a lower switch (HM5) and a lower resistor (HR2), the upper switch (HM2) connecting in series with the upper voltage source (VBoot) and to an upper side of the lower resistor (HR2), the lower switch (HMS5) connecting in series with the lower voltage source (gnd) and a lower side of the lower resistor (HR2), the gate terminal (e.g. T3) associated therewith connecting to the upper side of the lower resistor (HR2).
Claim 15; Fukushima et al. a plurality of power switches (PN1, PN2) operable for converting a direct current (Vin) input into an alternating current (AC) output suitable for electrically powering the traction motor (RL), the power switches operable between an opened state and a closed state to facilitate generating the AC outputs; and a gate drive system (30) operable for controlling a slew rate associated with transitioning the power switches between the opened and closed states ([0008], [0025], [0026], [0029], [0030], etc.), the gate drive system including a plurality of gate drive circuits (e.g. HDRV1, LDRV1) individually connected to a gate terminal (e.g. T3, T5) of a corresponding one of the power switches (PN1, PN2), the gate drive circuits being operable for controlling a gate-source voltage (Vgs) between a gate terminal and a source terminal of the power switch associated therewith, the Vgs (e.g. Vt_PN1, Vt_PN2) controlling the power switches between the opened and closed states (e.g. figures 4, 5, 7 and 8).
However, Fukushima et al. do not disclose a DC link capacitor connected in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors.
Morris teaches a controller that operates on one or more sensed and/or computed values for producing control signals to drive the switches. The sensed and computed values may further include one or more diode junction-case temperatures 202, filter capacitor temperatures 204, filter capacitor voltages 206, DC bus capacitor temperatures 208, DC bus capacitor voltages 210, fan speed value 212, air temperature 213, and power module base plate temperature 215.
Moreover, Somayajula et al. teach various parameters or values of the system, such as the control system of FIG. 1, are acquired. In one example, the values are the DC-link capacitor voltage Vdc, the three-phase voltages Va, Vb, Vc, the three-phase currents Ia, Ib, Ic, and the junction temperatures of the switching devices. Such values are used to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Fukushima et al. to include a DC link capacitor, as taught by Morris and Somayajula et al. to smooth the input voltage and connect it in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors as taught by Morris or Somayajula et al. in order to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Claim 16; Fukushima et al. disclose the gate drive circuits include an upper voltage source (Vboot), a lower voltage source (gnd), an upper switch (HM2), an upper resistor (HR1) and a lower resistor (HR2), the upper switch (HM2) connecting in series with the upper voltage source (Vboot), the upper resistor (HR1), the lower resistor (HR2), and the lower voltage source (gnd thru HMS5), with the gate terminal (T3) associated therewith connected between a lower side of the upper resistor (HR1) and an upper side of the lower resistor (HR2).
Claim 17; Fukushima et al.: e.g. [0008], [0025], [0026], [0029], [0030], etc.
Claim 18; Fukushima et al.: Vds; e.g. Vt_PN1 or Vt_PN2.
Claim(s) 1, 2, 4-6, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zoels et al. (US 20130328596) in view of Morris and further in view of Somayajula et al..
Claim 1; Zoels et al. disclose a plurality of power transistors (110) operable for converting a direct current (VDC) input into an alternating current (A, B, C) output suitable for electrically powering the electric machine (130), the power transistors operable between an opened state and a closed state to facilitate generating the AC output; and a gate drive system (fig. 2, 5, 8) operable for controlling a slew rate (e.g. para. [0046], [0053]-[0056]) associated with transitioning the power transistors between the opened and closed states, the gate drive system including a plurality of gate drive circuits (e.g. fig. 2: 402) individually connected to a gate terminal (e.g. 326) of a corresponding one of the power transistors (e.g. 224).
However, Zoels et al. do not disclose a DC link capacitor connected in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors.
Morris teaches a controller that operates on one or more sensed and/or computed values for producing control signals to drive the switches. The sensed and computed values may further include one or more diode junction-case temperatures 202, filter capacitor temperatures 204, filter capacitor voltages 206, DC bus capacitor temperatures 208, DC bus capacitor voltages 210, fan speed value 212, air temperature 213, and power module base plate temperature 215.
Moreover, Somayajula et al. teach various parameters or values of the system, such as the control system of FIG. 1, are acquired. In one example, the values are the DC-link capacitor voltage Vdc, the three-phase voltages Va, Vb, Vc, the three-phase currents Ia, Ib, Ic, and the junction temperatures of the switching devices. Such values are used to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Zoels et al. to include a DC link capacitor, as taught by Morris and Somayajula et al. to smooth the input voltage and connect it in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors as taught by Morris or Somayajula et al. in order to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Claim 2; Zoels et al. disclosed in para. [0046], [0053]-[0056].
Claim 4; Zoels et al.: e.g. gate current lge, fig. 5. para. [0029], [0047], [0049].
Claim 5; Zoels et al.: DC link capacitor 108.
Claim 6; e.g. Vds (drain source voltage)
Claims 19 and 20; Zoels et al. discloses a plurality of power switches (110) operable for converting a direct current (VDC) input into an alternating current (AC) output suitable for electrically powering the traction motor (130), the power switches operable between an opened state and a closed state to facilitate generating the AC outputs; and a gate drive system (fig. 2, 5, 8) operable for controlling a slew rate (e.g. para. [0046], [0053]-[0056]) associated with transitioning the power switches between the opened and closed states, the gate drive system including a plurality of gate drive circuits (fig. 2) individually connected to a gate terminal of a corresponding one of the power switches, the gate drive circuits being operable for controlling a gate current (Ige) to a gate terminal (326) of the power switch associated therewith, the Ige controlling the power switches between the opened and closed states.
However, Zoels et al. do not disclose a DC link capacitor connected in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors.
Morris teaches a controller that operates on one or more sensed and/or computed values for producing control signals to drive the switches. The sensed and computed values may further include one or more diode junction-case temperatures 202, filter capacitor temperatures 204, filter capacitor voltages 206, DC bus capacitor temperatures 208, DC bus capacitor voltages 210, fan speed value 212, air temperature 213, and power module base plate temperature 215.
Moreover, Somayajula et al. teach various parameters or values of the system, such as the control system of FIG. 1, are acquired. In one example, the values are the DC-link capacitor voltage Vdc, the three-phase voltages Va, Vb, Vc, the three-phase currents Ia, Ib, Ic, and the junction temperatures of the switching devices. Such values are used to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Zoels et al. to include a DC link capacitor, as taught by Morris and Somayajula et al. to smooth the input voltage and connect it in parallel to a DC source providing the DC input, wherein: the plurality of gate drive circuits is operable to provide the plurality of gate terminals of the plurality of power transistors with a plurality of control signals: and the plurality of controls signals are generated as a function of a temperature of the DC link capacitor and a junction temperature of the corresponding one of the plurality of power transistors as taught by Morris or Somayajula et al. in order to provide the remaining useful of the transistors or the state of degradation for the components may be calculated.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GARY L LAXTON/ Primary Examiner, Art Unit 2838 11/18/2025
Prosecution Insights