Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1) and Buffle et al. (US 20220393038 A1).
Regarding claim 1, Cheng et al. (‘347) disclose a method of manufacturing a semiconductor device, the method comprising: forming a deep trench (paragraph 7, Fig. 3) in a substrate (8); forming a shallow trench adjacent (70B, Fig. 10) to the deep trench (trenches in area A1, Fig. 3); forming a logic gate insulating layer (80) adjacent to the shallow trench; forming a logic gate electrode (82) on the logic gate insulating layer (Fig. 10); filling a first conductive layer (60) into the deep trench (Fig. 6); and forming a source region and a drain region (34) adjacent to the logic gate electrode (80) (Fig. 10).
Cheng does not disclose performing an ion implantation process to form a lower electrode along with the deep trench; forming a dielectric layer on the lower electrode; filling a first conductive layer into the deep trench; performing a planarization process on the first conductive layer to form an upper electrode in the deep trench such that a trench capacitor is formed in the deep trench, wherein the logic gate electrode is made of a same material as the upper electrode.
However, Cheng et al (‘922) disclose performing an ion implantation process to form a lower electrode (106) along with the deep trench (paragraph 41); forming a dielectric layer on the lower electrode (paragraph 76, “a base capacitor dielectric layer overlying the lower capacitor electrode”);
Neither Cheng et al. (‘347) nor Cheng et al (‘922) disclose the filling a first conductive layer into the deep trench; performing a planarization process on the first conductive layer to form an upper electrode in the deep trench such that a trench capacitor is formed in the deep trench, wherein the logic gate electrode is made of a same material as the upper electrode.
Buffle et al. disclose performing a planarization process on the first conductive layer (506) to form an upper electrode (106) in the deep trench such that a trench capacitor is formed in the deep trench (Fig. 2);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. (‘347) in view of Buffle et al. such that the planarization process happens on the first conductive layer. Doing so would remove excess material deposited during filing, ensuring a flat and uniform surface for subsequent manufacturing steps.
However, neither Cheng et al. (‘347), Cheng et al. (‘922), nor Buffle et al. disclose the logic gate electrode is made of a same material as the upper electrode.
On the other hand, Cheng (‘347) disclose the gate electrode is made of doped polycrystalline Si (paragraph 58) and Buffle et al. disclose the top electrode layer (106) is made of polysilicon (paragraph 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. (‘347) and Cheng et al. (‘922) with Buffle et al. such that the logic gate electrode and top electrode layer are the same material, such as polysilicon. Doing so would streamline manufacturing processes, ensure compatibility with CMOS technology, and reduce costs.
Regarding claim 2, Cheng et al. (‘347) does not disclose wherein the forming of the deep trench in the substrate comprises: forming a deep trench hard mask pattern on the substrate; and performing an etching process on the substrate to form the deep trench with the deep trench hard mask pattern.
However, Cheng (‘922) disclose forming a trench hard mask pattern on the substrate; and performing an etching process on the substrate to form the trench with the trench hard mask pattern (paragraph 40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. in view of Cheng (‘922) such that a trench hard mask pattern is formed on the substrate by etching. Doing so would provide superior durability and etching selectivity over traditional photoresists, allowing for the creation of deep trenches.
Regarding claim 5, neither Cheng et al. (‘347) nor Cheng et al. (‘922) does not disclose performing a high temperature annealing process on the planarized first conductive layer or the upper electrode.
However, Buffle et al. disclose a 600–900-degree Celsius range annealing process for the top electrode layer (106) (paragraph 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. in view of Buffle et al. such that a high temperature annealing process is on the first planarized first conductive layer. Doing so would stabilize the electrical, physical, and structure properties after deposition and CMP.
Claims 3, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1) and Buffle et al. (US 20220393038 A1) as applied to claim 1 above, in further view of Lin (US 20160020267 A1).
Regarding claim 3, Cheng (‘347), Cheng (’922), and Buffle et al. are discussed above. None of these references disclose forming a first dielectric layer in the deep trench; and forming a second dielectric layer on the first dielectric layer, and wherein the first dielectric layer comprises a first material that is different from a second material of the second dielectric layer.
However, Lin discloses a first dielectric (600) formed in the deep trench, forming a second dielectric layer (800) on the first dielectric layer (Fig. 8), and wherein the first dielectric material can be different from the second dielectric material, such as HfO, Al2O3, and ZrO (paragraph 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above in view of Lin such that the dielectric layers are on top of each other and made of different materials. Doing so would optimize performance, increase capacitance density, and manage voltage.
Regarding claim 6, Cheng (‘347), Cheng (’922), and Buffle et al. are discussed above. None of these references disclose performing a first chemical mechanical planarization (CMP) process on the first conductive layer to form a planarized first conductive layer; and performing a second CMP process to remove the dielectric layer exposed by the first CMP.
However, Lin discloses performing CMP on conductive and dielectric layers (paragraph 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above in view of Lin such that CMP is performed to form a planarized conductive layer and remove the dielectric layer. Doing so would achieve a perfectly flat and uniform surface at the nanometer level.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1) and Buffle et al. (US 20220393038 A1) as applied to claim 1 above, in further view of Kim et al. (US 20070052013 A1) and Kamiya et al. (US 20050253202 A1).
Regarding claim 4, Cheng (‘347), Cheng (’922), and Buffle et al. are discussed above. None of these references disclose forming thermal oxide layers on the upper electrode and the logic gate electrode; and forming spacers on sidewalls of the upper electrode and the logic gate electrode.
However, Kim et al. disclose forming spacers (32) on side walls of the gate electrode (30g) and the first and second upper electrodes (30’, 30”) (paragraph 50, Fig. 5B). Kim et al. also discloses the dielectric layer can be thermal oxide layer (paragraph 20).
Kamiya et al. disclose a silicon oxide film is formed by thermal oxidation on the surfaces of the gate electrodes (7, 8) so as to cover the surfaces (paragraph 29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng (‘347), Cheng (’922), and Buffle et al. in view of Kim et al. and Kimya et al. such that the thermal oxide layer is on the surface of the electrodes and spacers are formed on the side walls of the electrodes. Doing so would provide electrical isolation, high resistivity, and structural integrity.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1) and Buffle et al. (US 20220393038 A1) as applied to claim 1 above, in further view of Wu (US 20040046200 A1).
Regarding claim 7, Cheng (‘347), Cheng (’922), and Buffle et al. are discussed above. None of these references disclose performing a gap-fill process on the shallow trench with a thick insulating layer; and performing a third CMP process on the thick insulating layer.
However, Wu discloses depositing a thick-oxide film (304) to fill up each gap formed by shallow trenches and then planarizing it using CMP (paragraph 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above in view of Wu such that the gaps are filled with an insulating material and then CMP is performed. Doing so would enable electrical isolation and planarize the fill for subsequent steps.
Claims 8-9, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1), Buffle et al. (US 20220393038 A1), Wu (US 20040046200 A1), Sinitsky et al. (US 20060172504 A1), and Kim et al. (US 20070052013 A1).
Regarding claim 8, Cheng et al. disclose a method of manufacturing a semiconductor device, the method comprising: providing a first region (eDRAM area) and a second region (Logic area) in a semiconductor substrate (8) (Fig. 1); forming a deep trench hard mask pattern in the second region (paragraph 32); forming a deep trench (deep trench in A1, Fig. 3) in the second region with the deep trench hard mask pattern; forming a logic gate insulating layer (80) adjacent to the shallow trench; and forming a source region and a drain region (34) around the logic gate electrode (80).
Cheng et al. does not disclose wherein the first conductive layer is a same material as the second conductive layer.
On the other hand, Cheng (‘347) disclose the gate electrode is made of doped polycrystalline Si (paragraph 58) and Buffle et al. disclose the top electrode layer (106) is made of polysilicon (paragraph 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al with Cheng (‘347) such that the conductive layers are made of polysilicon. Doing so would offer excellent compatibility with silicon/oxide, allows for fine tuning via doping, and better uniformity.
Cheng et al does not disclose performing a first planarization process on the first conductive layer to form an upper electrode in the deep trench.
However, Buffle et al. disclose performing a planarization process on the first conductive layer (506) to form an upper electrode (106) in the deep trench such that a trench capacitor is formed in the deep trench (Fig. 2).
Cheng does not disclose filling the shallow trench with a thick insulating layer or performing a second planarization process on the thick insulating layer to form a planarized thick insulating layer in the shallow trench.
However, Wu discloses depositing a thick-oxide film (304) to fill up each gap formed by shallow trenches and then planarizing it using CMP (paragraph 22).
Cheng et al. does not disclose forming a lower electrode along with the deep trench or forming a dielectric layer on the lower electrode.
However, Cheng et al. (‘922) disclose forming a lower capacitor electrode and a base dielectric layer overlying the lower capacitor electrode and lining the trench (paragraph 76)
None of the prior references disclose forming a shallow trench hard mask pattern in the first region or forming a shallow trench in the first region with the shallow trench hard mask pattern.
However, Sinitsky et al. disclose forming a shallow trench hard mask pattern (420, paragraph 58, Fig. 4A) and forming a shallow trench (441) with the shallow trench hard mask layer (paragraph 58, Fig. 4A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above references in view of Sinitsky et al. such that the shallow trench hard mask pattern is formed and a shallow trench is formed with the hard mask layer. Doing so would define where trenches are etched into the silicon, preventing current league and isolating devices.
None of the prior references disclose forming a second conductive layer on the logic gate insulating layer or performing a patterning process on the second conductive layer to form a logic gate electrode in the first region.
However, Kim et al. disclose a conductive layer (30) is formed the substrate having gate dielectric layer (25) (paragraph 48). Kim et al. also discloses the conductive layer (30) is patterned, thereby forming gate electrodes (30g).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Kim et al. such that the conductive layer is formed over the insulating layer and patterned to form logic gate electrodes. Doing so would enable the creation of precise structures that regulate current flow.
Regarding claim 9, Cheng et al. does not disclose the forming of the lower electrode comprises performing an ion implantation process along with the deep trench.
However, Cheng et al (‘977) disclose performing an ion implantation process to form a lower electrode (106) along with the deep trench (paragraph 41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. according to Cheng e al (‘977) such that the ion implantation process forms the lower electrode along with the deep trench. Doing so would increase capacitance density, improve performance, and create the necessary conductive layer for a 3D capacitor structure.
Regarding claim 12, Cheng et al. does not disclose performing a high temperature annealing process on the planarized first conductive layer or the upper electrode.
However, Buffle et al. disclose a 600–900-degree Celsius range annealing process for the top electrode layer (106) (paragraph 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. in view of Buffle et al. such that a high temperature annealing process is on the first planarized first conductive layer. Doing so would stabilize the electrical, physical, and structure properties after deposition and CMP.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1), Buffle et al. (US 20220393038 A1), Wu (US 20040046200 A1), Sinitsky et al. (US 20060172504 A1), and Kim et al. (US 20070052013 A1) as applied to claim 8 above, in further view of Kamiya et al. (US 20050253202 A1).
Regarding claim 10, none of the prior references disclose forming a thermal oxide layer on each surface of the logic gate electrode and the upper electrode.
However, Kamiya et al. disclose a silicon oxide film is formed by thermal oxidation on the surfaces of the gate electrodes (7, 8) so as to cover the surfaces (paragraph 29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Kamiya et al. such that the thermal oxide layer is on the surface of the logic gate electrodes and the upper electrode. Doing so would provide electrical isolation and high resistivity.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1), Buffle et al. (US 20220393038 A1), Wu (US 20040046200 A1), Sinitsky et al. (US 20060172504 A1), and Kim et al. (US 20070052013 A1) as applied to claim 8 above, in further view of Lin (US 20160020267 A1).
Regarding claim 11, none of the prior references disclose performing a first chemical mechanical planarization (CMP) process on the first conductive layer to form a planarized first conductive layer; and performing a second CMP process to remove the dielectric layer exposed by the first CMP.
However, Lin discloses performing CMP on conductive and dielectric layers (paragraph 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Lin such that CMP is performed to form a planarized conductive layer and remove the dielectric layer. Doing so would achieve a perfectly flat and uniform surface at the nanometer level.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1), Buffle et al. (US 20220393038 A1), Wu (US 20040046200 A1), Kim et al. (US 20070052013 A1), Lin (US 20160020267 A1) and Tsai et al. (US 20210074806 A1).
Regarding claim 13, Cheng et al. disclose a method of manufacturing a semiconductor device, the method comprising: providing a first region (eDRAM) and a second region (Logic area) in a substrate (8) (Fig. 1); forming a deep trench in the second region (deep trench in A1, Fig. 3); forming a shallow trench (70B, Fig. 9) adjacent to the deep trench (deep trench in eDRAM area, Fig. 5); and forming source and drain regions (34) adjacent to the logic gate electrode (80).
Cheng et al. does not disclose forming a lower electrode along with the deep trench or forming a dielectric layer on the lower electrode.
However, Cheng et al. (‘922) disclose forming a lower capacitor electrode and a base dielectric layer overlying the lower capacitor electrode and lining the trench (paragraph 76).
Cheng et al. does not disclose performing a planarization process on the first conductive layer to form an upper electrode in the deep trench such that a trench capacitor is formed in the deep trench.
However, Buffle et al. disclose performing a planarization process on the first conductive layer (506) to form an upper electrode (106) in the deep trench such that a trench capacitor is formed in the deep trench (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. in view of Buffle et al. such that the planarization process happens on the first conductive layer. Doing so would remove excess material deposited during filing, ensuring a flat and uniform surface for subsequent manufacturing steps.
Cheng et al. does not disclose filling the shallow trench with a thick insulating layer to form a shallow trench isolation.
However, Wu discloses depositing a thick-oxide film (304) to fill up each gap formed by shallow trenches and then planarizing it using CMP (paragraph 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Wu such that the gaps are filled with an insulating material and then CMP is performed. Doing so would enable electrical isolation and planarize the fill for subsequent steps.
Cheng et al does not disclose performing a patterning process on the second conductive layer to form a logic gate electrode in the first region, and forming a second conductive layer on the first and second gate insulating layers.
However, Kim et al. discloses the conductive layer (30) is patterned, thereby forming gate electrodes (30g), and a conductive layer (30) on the insulating layer (25) (paragraph 48, Fig. 4B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. with Kim et al. such that the conductive layer is patterned to form gate electrodes, and the conductive layer is on the gate insulating layer. Doing so would increase capacitor area.
Cheng et al. does not disclose filling a first conductive layer into the deep trench.
However, Lin discloses a first conductive layer (110) is formed in the trench (106) (Fig.1A, paragraph 22)
Cheng et al. does not disclose forming a first gate insulating layer on the substrate in the first region, and forming a second gate insulating layer on the upper electrode in the second region.
However, Tsai et al. disclose an insulating layer 150 on the substrate (102) and an insulating layer on the upper electrode (136) (Fig. 7B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. according to Tsai et al. such that an insulating layer is on the substrate and the upper electrode. Doing so would provide electrical isolation and minimize parasitic capacitance.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 20090176347 A1) in view of Cheng et al. (‘922) (US 20200066922 A1), Buffle et al. (US 20220393038 A1), Wu (US 20040046200 A1), Kim et al. (US 20070052013 A1), Lin (US 20160020267 A1) and Tsai et al. (US 20210074806 A1) as applied to claim 13 above, in further view of Lee (US 20080006866 A1).
Regarding claim 14, none of the prior references disclose the dielectric layer comprises a first insulating layer, a second insulating layer, and a third insulating layer, and wherein the first and third insulating layers are formed of a same material, and the second insulating layer is formed of a material different from that of the first and third insulating layers.
However, Lee discloses a dielectric layer (181) comprising of a first dielectric layer (181), second dielectric layer (141), and a third dielectric layer (182). The first layer may be of an oxide layer, and the second layer may be of a nitride layer (paragraph 34, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Lee such that the second insulating layer is formed of a material different from that of the first and third insulating layers, and the layers are insulating. Doing so would maximize capacitance density while minimizing electrical leakage and ensuring high reliability.
Regarding claim 15, Cheng et al. discloses a dielectric material of Al2O2 and Cheng et al (‘922) disclose a dielectric layer can be made of silicon nitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng et al. with Cheng et al. (‘922) such that the dielectric layers are made of Al2O2 or Silicon Nitride. Doing so would enable high dielectric values, high reliability, and excellent conformal coverage in deep trenches.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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