Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments/remarks, filed on 04/24/2026, are acknowledged. Amended claim 1 is acknowledged. Claims 1-8 and 10 remain pending and have been examined.
Response to Arguments
3. Applicant’s arguments, see pg. 8,lines 3-8, with respect to the rejection of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground of rejection is made in view of Decker et al. (US 2002/0154231 A1). See claim 1 rejection below.
Further, it is to be noted that the prior arts of reference relate to a similar background of technical features. As such, for example, when it comes to mitigating noises that are common in charge-coupled devices or CMOS image sensors, correlated double sampling (CDS) is implemented so to reduce or suppress noise; wherein the noise can be a fixed pattern noise and or the noise can also be a flicker noise. In either case, correlated double sampling helps in mitigating these types of noise by means of double sampling two electrical/signal values and subtracting one from the other. As such, Dobromir (Correlated Multiple Sampling Techniques for Sensor Signal Conditioning; only referred to as evidence for the implementation of CDS in noise mitigation) teaches (Pg. 1, lines 1-19) CDS as being used to effectively cancel offset and low frequency (flicker) noise. Therefore, the rational to combine the prior art references in accordance with Otaka, Kawamura, Peizerat, and Elhachimi is proper in that these references in combination teach modules and components which are effectively and actively used in the industry of image sensors.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Otaka
(US 2018/0198997 A1), in view of Kawamura (US 2018/0315785 A1) and Peizerat et al.
(US 2013/0048832 A1; further referred to as Peizerat) and further view of Decker et al. (US 2002/0154231 A1; further referred to as Decker) Elhachimi et al., (US 2015/0103209 A1; further referred to as Elhachimi).
6. Regarding claim 1, a light detecting device, comprising:
a first substrate (…Otaka in [0090] teaches a first substrate (upper substrate);
wherein pixel array 230 is formed on the first substrate, Fig. 3-4…) including:
a photodiode (…wherein [0060] teaches photodiode PD 21, Fig. 3…);
a transfer transistor (…wherein [0060] teaches transfer transistor TG1-1, Fig. 3…);
a reset transistor (…wherein [0060] teaches reset transistor RST1-TR, Fig. 3…);
a first amplification transistor (…wherein [0060] teaches source-follower transistor
SF1-TR, Fig. 3…); and
a first wiring layer (…wherein [0090] teaches a wiring layer between the pixel array
230 and a holding array 240…);
a second substrate (…wherein [0090] teaches a stacked structure of an imaging
device that may be made up of a second substrate (lower substrate, Fig. 3…) including:
a first switch transistor (…wherein Otaka in [0071] teaches sampling transistor SHR
1-TR that may be viewed as a first switch transistor, Fig. 3…);
a first capacitor configured to store a first signal photoelectrically converted in a first
exposure period (...wherein [0071] also teaches a holding capacitor CR 21 that may be
viewed as a first capacitor, Fig. 3; Otaka further teaches, in [0118-0119], that at t3 SHR1-
Tr becomes conductive and a corresponding signal is eventually held in signal holding
capacitor CR 21…);
a second amplification transistor (…wherein [0078] teaches transistor SF3 R-Tr that
may be viewed as a second amplification transistor, Fig. 3…);
a second selection transistor (…wherein [0078] teaches selection transistor SEL 2 R-
Tr which may be viewed as a second selection transistor, Fig. 3…);
a second switch transistor (…wherein [0072] teaches sampling transistor SHS1-Tr
that may be viewed as a second switch transistor, Fig. 3…);
a second capacitor configured to store a second signal photoelectrically converted in
a second exposure period (…wherein [0071] teaches signal holding capacitor CS 21 that may be viewed as a second capacitor, Fig. 3; Otaka further teaches [0121-0123] wherein at t5 SHS1-Tr becomes conductive and a corresponding signal is eventually held in signal holding capacitor CS 21…);
a third amplification transistor (…wherein [0075] teaches SF2S-TR that may be
viewed as a third amplification transistor, Fig. 3…);
a third selection transistor (…wherein [0075] teaches SEL1S-Tr that may be viewed
as a third selection transistor, Fig. 3…); and
a second wiring layer (…wherein it would be an obvious implementation of
providing a second wiring layer in view of Otaka that a second layer and its relative
components would require a wiring layer for further connectivity between a second layer
and following circuits (as such a horizontal scanning circuit; as one depicted in Fig. 2…);
the first substrate is electrically connected to the second substrate via each of a first
wiring of the first wiring layer and a second wiring of the second wiring layer (…wherein [0090]
teaches a stacked structure of an upper and lower substrate may be separated by a metal
wiring layer…), and
the first capacitor and the second capacitor are in the second wiring layer (…wherein
CR 21 and CS 21 are part of holding array 240 (element 212 in Fig. 3), as specified in
[0071]…).
Though Otaka teaches a first transfer transistor, Otaka does not teach an additional
selection transistor on a first substrate (…however, Kawamura teaches a solid state imaging device to include a semiconductor substrate 12 which includes all the above limited elements as taught by Otaka and a first selection transistor 28 in [0058], Fig. 2…).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that the teaching of Kawamura, regarding a
selection transistor, could have been incorporated in the teaching of Otaka, thus to keep the photoelectric conversion components in a substrate apart from other circuits that may involve a holding circuit or a logic circuit…).
Further, though Otaka teaches the provision of a differential signal to a column readout
circuit in [0055], Otaka does not further teach:
a third substrate including:
a comparator, wherein the first wiring layer faces the second wiring layer (…however, Peizerat, in [0010], teaches an imaging device of a three dimensional architecture including a third substrate on which digital electronic is formed for processing signals (wherein a comparator may be viewed as a digital electronic circuit for processing signals).
Wherein Peizerat teaches a digital electronic circuit for processing signals, Decker further teaches an image sensor of multiple readout lines so to perform correlated double-sampling to include CDS circuits, as taught in [0063].
Therein Decker teaches:
a differential comparator configured to output a signal corresponding to a difference between a first signal charge in the first exposure period and a second signal charge in the second exposure period (…wherein Decker, in [0065] in accordance with Fig. 7, teaches what is viewed as a differential comparator, in which signals [Phi]1 and [Phi]2 are active in a first and second time period, wherein a resulting differential voltage between conductors 502a and 502b during the second time period has an amplitude equal to the difference between the amplitude of voltage TCRL0 during the first time period and the amplitude of voltage TCRL0 during the second time period.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a third layer substrate could have been
implemented, as taught by Peizerat in the teaching of Otaka, thus to modulate a pixel array into an additional third substrate containing the differential amplifier as taught by Decker, thus to focus separate substrates to one dedicated function, thereby also having the ability to produce smaller substrates that may be stacked and which may require less space within a device of implementation…).
Otaka, also, does not further teach:
a length of the first exposure period is same as a length of the second exposure period (…however, Elhachimi, in [0022], teaches an image sensor of an electronic rolling shutter
type; wherein [0025] teaches method of compensating for flicker wherein two successive frames of images are taken with an offset between two integration intervals.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that in a rolling shutter mode of the imaging device, as taught by Otaka (see [0101]), an additional feature of flicker compensation for images taken with an image sensor in a rolling shutter mode, as taught by Elhachimi, could be implemented thus to produce flicker compensated images in the device as taught by Otaka…).
7. Regarding claim 2, Otaka in view of Kawamura and Peizerat and further view of
Decker and Elhachimi teaches the light detecting device according to claim 1 (see claim 1 above), wherein:
the first substrate further includes a floating diffusion (…wherein Otaka teaches
floating diffusion FD 21 in [0064], Fig. 3…),
the second substrate further includes a constant current source (…wherein [0066]
teaches a constant current source arranged in the signal holding part 212…).
Otaka does not further disclose a third switch on the first substrate.
Nevertheless the inclusion of a third switch/transistor in a photoelectric conversion
circuit relative to a photodiode and a detected charge and an initial storing of the charge is
common. As evidenced by Kawamura, [0060] teaches transfer transistor 24 (Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a switch transistor as taught by Kawamura
could have easily been implemented in the teaching of Otaka thus to have the ability to time the
transfer of a voltage stored in a capacitor at a particular chosen time within the functions of a
photoelectric conversion circuit.
8. Regarding claim 3, Otaka in view of Kawamura and Peizerat and further view of
Decker and Elhachimi teaches the light detecting device according to claim 2 (see claim 2 above). However, Otaka does not further teach wherein:
the first substrate further includes a third capacitor that is electrically connected to the
floating diffusion via the third switch transistor.
However, Kawamura in [0060] teaches a memory section (capacitor) 23 which is a
charge holding section connected to FD 25 via transfer resistor 24.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a capacitor, to temporarily hold photo detected
charges, as taught by Kawamura could have been implemented in the teachings of Otaka’s
disclosure, thus to provide better stability for the photo detected charge in the process of
conducting it to further reading and holding circuits.
9. Regarding claim 4, Otaka in view of Kawamura and further view of Decker and Peizerat teaches the light detecting device according to claim 1 (see claim 1 above), wherein:
the first substrate further includes a floating diffusion (…wherein Otaka teaches
floating diffusion FD 21 in [0064], Fig. 3…),
the transfer transistor is connected between the photodiode and the floating diffusion
(…wherein TG1-Tr is connected between PD 21 and FD 21, Fig. 3…),
the floating diffusion is connected to the reset transistor (…wherein FD21 is connected
to RST1-Tr, Fig. 3…), and
the first amplification transistor includes:
a gate electrode that is connected to the floating diffusion (…wherein the gate SF1-Tr
is connected to FD21, Fig. 3…), and
a source that is connected to the first wiring layer via the first selection transistor (…wherein as depicted in Fig. 3, the source of SF1-Tr is electrically connected to the
second substrate via the die-to-die vias, as taught in [0109], Fig. 3…).
10. Regarding claim 5, Otaka in view of Kawamura and Peizerat and further view of
Decker and Elhachimi teaches the light detecting device according to claim 1 (see claim 1 above), wherein:
the first capacitor is connected to the first switch transistor (…wherein as depicted in
Fig. 3, CR 21 is connected to SHR1-Tr (Otaka)…),
the second amplification transistor includes: a gate electrode that is connected to the
first capacitor (…wherein SF3R-Tr is connected to CR 21, Fig. 3…), and
a source that is connected to the second selection transistor (…wherein the source of SF3R-Tr is connected to SEL2R-Tr, Fig. 3…),
the second capacitor is connected to the second switch transistor (…wherein CS 21 is
connected to SHS1-Tr, Fig. 3…), and
the third amplification transistor includes: a gate electrode that is connected to the
second capacitor (…wherein SF2S-Tr is connected to CS 21, Fig. 3…), and
a source that is connected to the third selection transistor (…wherein the source of SF2S-Tr is connected to SEL1S-Tr, Fig. 3…).
11. Regarding claim 6, Otaka in view of Kawamura and Peizerat and further view of
Decker and Elhachimi teaches the light detecting device according to claim 1 (see claim 1 above), wherein:
the first switch transistor is configured to:
receive a first output of the first amplification transistor (…wherein Otaka teaches
SHR1-Tr receives the output of SF1-Tr, Fig. 3…); and
store the received first output in the first capacitor (…wherein CR 21 stores the output
of SF1-Tr via SHR1-Tr, Fig. 3…),
the second amplification transistor is configured to:
amplify the stored first output (…SF3R-Tr amplifies the output of CR 21, Fig. 3); and
output, via the second selection transistor, the amplified first output (…wherein SEL2R-
Tr outputs, via SF3R-Tr an amplified output, Fig. 3…),
the second switch transistor is configured to:
receive a second output of the first amplification transistor (…wherein SHS1-Tr
receives the output of SF1-Tr, Fig. 3…); and
store the received second output in the second capacitor (…wherein CS21 stores the
output of SHS1-Tr, Fig. 3…), and
the third amplification transistor is configured to:
amplify the stored second output (…wherein SF2S-Tr amplifies the output of storing
capacitor CS21, Fig. 3…); and
output, via the third selection transistor, the amplified second output (…wherein SEL1S-
Tr outputs the amplified output of SF2S-Tr, Fig. 3…).
12. Regarding claim 7, Otaka in view of Kawamura and Peizerat and further view of
Decker and Elhachimi teaches the light detecting device according to claim 1 (see claim 1 above), wherein:
the first wiring of the first wiring layer is in contact with the second wiring of the second
wiring layer (…wherein Otaka in [0109] teaches a junction, die-to-die vias; Fig. 3…).
13. Regarding claim 8, Otaka in view of Kawamura and Peizerat and further view of
Decker and Elhachimi teaches the light detecting device according to claim 1 (see claim 1 above), wherein:
the first capacitor is configured to store a reset level signal (…wherein Otaka, in [0081]
teaches that CR 21 stores a reset signal…), and
the second capacitor is configured to store a signal level signal (…wherein Otaka, in
[0081], teaches that CS 21 stores a readout signal…).
14. Regarding claim 10, Otaka in view of Kawamura and Peizerat and further view of
Decker and Elhachimi teaches the light detecting device according to claim 1 (see claim 1 above), wherein:
the first wiring of the first wiring layer is connected to one of the first capacitor or the
second capacitor via the second wiring of the second wiring layer (…wherein as evidenced in
Fig. 3, Otaka shows either CR 21 or CS 21 (lower substrate) being connected to the first
layer through corresponding transistors via the die-to-die connection point, Fig. 3…).
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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