Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US PGPub 2020/0135270, hereafter “Lee,” in view of Thompson et al., US PGPub 2016/0268000, hereafter “Thompson,” further in view of Buxton et al., US PGPub 2022/0300199, hereafter “Buxton.”
With respect to claim 1, Lee teaches a solid state drive (SSD) comprising:
a controller in the SSD (pars. 39-40 and fig. 1, memory controller 200 in SSD 50);
a write buffer in the SSD configured to store write data received from a host (par. 60 and fig. 1, write buffer 210); and
a non-volatile storage device in the SSD comprising a non-volatile memory (NVM) (par. 44 and fig. 1, the memory device 100, which may be a nonvolatile memory such as a NAND flash), a first data buffer, and a second data buffer (pars. 48-49 and fig. 1, the page buffer group 123, which includes a plurality of page buffers for storing the received data),
wherein the controller is configured to:
transfer the write data received from the host from the write buffer to the first data buffer and the second data buffer (par. 131, the page buffers store a plurality of data chunks received from the write buffer);
Lee fails to teach determining the particular write method of programming the non-volatile memory from the data buffers in response to a power failure.
Thompson teaches:
determine whether a power failure occurs (par. 33);
in response to determining that a power failure does not occur, cause the write data stored in at least one of the first data buffer (fig. 2A, write buffer 122) or the second data buffer (fig. 2A, system metadata 124) of the non-volatile storage device to be programmed to the NVM of the non-volatile storage device in a first mode (pars. 32-33, in normal operating mode, data is written from write buffer 122 to the flash memory array in MLC mode); and
in response to determining that the power failure occurs, cause the write data stored in at least one of the first data buffer or the second data buffer of the non-volatile storage device to be programmed to the NVM in a second mode different from the first mode (par. 35, in power fail saving mode, a modified MLC page write operation is performed for data in the write buffer 122).
Thompson doesn’t teach that the write data stored in the first data buffer or second data buffer is data transferred from a write buffer.
Buxton teaches write data transferred from the write buffer and stored in at least one of the first data buffer and the second data buffer (pars. 42-43, data from the internal controller buffer (write buffer) is stored in the program data buffers and private buffers), and therefore Thompson and Buxton combine to teach causing the write data transferred from the write buffer and stored in at least one of the first data buffer or the second data buffer of the non-volatile storage device to be programmed to the NVM in the first or second mode, as claimed.
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Thompson before him before the earliest effective filing date, to modify the flash memory of Lee with the flash memory of Thompson, in order to use a modified MLC page write operation mode in the event of a power failure, in order to eliminate the need to write an entire erase block, which supports saving essential volatile data during the holdup times, as taught by Thompson in pars. 35-36. Further, it would have been obvious also having the teachings of Buxton before him before the earliest effective filing date, to modify the flash memory of Lee and Thompson with the flash memory of Buxton, in order to incorporate a write buffer in the controller, as it allows it to retain the original data payload until the data payload is written to the NAND array, as taught by Buxton in par. 42.
With respect to claim 2, Lee, Thompson and Buxton teach the limitations of the parent claim. Thompson further teaches the SSD of claim 1, wherein the first mode is at least one of single-level cell (SLC) mode, multi-level cell (MLC) mode, triple-level cell (TLC) mode, or quad-level cell (QLC) mode (par. 32, MLC mode).
With respect to claim 3, Lee, Thompson and Buxton teach the limitations of the parent claim. Buxton further teaches the SSD system of claim 1, wherein the second mode is a pseudo single-level cell (pSLC) mode (pars. 52-53, in the event of a power failure, the data is written as pSLC).
With respect to claim 4, Lee, Thompson and Buxton teach the limitations of the parent claim. Lee further teaches the SSD of claim 1, wherein the controller comprises the write buffer (par. 60 and fig. 1, write buffer 210 in controller 200).
With respect to claim 5, Lee, Thompson and Buxton teach the limitations of the parent claim. Buxton further teaches the SSD of claim 1, wherein the non-volatile storage device comprises a plurality of sub-systems each comprising a respective NVM (par. 31, memory array 142 of NAND planes 143), the first data buffer comprises one or more program data buffers in each of the plurality of sub-systems (par. 41, program buffers 210), and the second data buffer comprises one or more additional buffers in each of the plurality of sub-systems (par. 41, private buffers 220).
With respect to claim 6, Lee, Thompson and Buxton teach the limitations of the parent claim. Lee further teaches the SSD of claim 5, wherein the controller is configured to:
transfer write data received from the host from the write buffer to the one or more program data buffers and the one or more additional data buffers of a first sub-system of the plurality of sub-systems (par. 131, the first plurality of data chunks received from the write buffer are stored in the plurality of page buffers (one or more program data buffers), and the subsequent data received from write buffer are stored in the remaining page buffers (one or more additional data buffers));
Thompson teaches:
in response to determining that the power failure does not occur, configure the first sub-system to program, to the NVM of the first sub-system in the first mode, write data received from the host stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first sub-system of the plurality of sub-systems (pars. 32-33, in normal operating mode, data is written from write buffer 122 to the flash memory array in MLC mode); and
in response to determining that the power failure occurs, configure the first sub-system to program, to the NVM of the first sub-system in the second mode, write data received from the host stored in in at least one of the one or more program data buffers or the one or more additional data buffers of the first sub- system (par. 35, in power fail saving mode, a modified MLC page write operation is performed for data in the write buffer 122).
With respect to claim 7, Lee, Thompson and Buxton teach the limitations of the parent claim. Lee further teaches the SSD of claim 1, wherein the controller is configured to:
in response to transferring the write data received from the host from the write buffer to the first data buffer and the second data buffer, delete the write data received from the host from the write buffer (pars. 142-143, data is deleted from the write buffer after it has been programmed to the page buffer group).
With respect to claim 8, Lee, Thompson and Buxton teach the limitations of the parent claim. Thompson further teaches the SSD of claim 1, wherein in response to determining that the power failure occurs, the device is configured to:
stop the programming in the first mode, and then start programming the write data received from the host stored in at least one of the first data buffer or the second data buffer to the NVM in the second mode (pars. 35-36, after detection of a power failure, the mode is switch from MLC mode as described in pars. 32-33, to the modified MLC mode).
With respect to claim 9, Lee, Thompson and Buxton teach the limitations of the parent claim. Thompson further teaches the SSD of claim 1, wherein in response to determining that the power failure occurs, the controller is configured to program write data received from the host stored in the write buffer to the NVM in the second mode, while programming the data stored in at least one of the first data buffer or the second data buffer to the NVM in the second mode (pars. 35-37 and fig. 2B, following a power failure, data is written from write data buffer 122 to flash memory in modified MLC mode). Thompson doesn’t specify that the write from the write buffer to the NVM is in the second mode.
With respect to claim 10, Lee, Thompson and Buxton teach the limitations of the parent claim. Lee further teaches the SSD of claim 1, wherein the controller is a solid state drive (SSD) controller system-on-chip (SoC) (pars. 40-41).
Claims 11-20 are a method that corresponds to system claims 1-10 and are rejected using similar logic.
Response to Arguments
Applicant's arguments filed 09/14/2026 have been fully considered but they are not persuasive. Applicant argues on pages 7-8 that Thompson fails to teach causing the write data transferred from the write buffer and stored in at least one of the first data buffer or the second data buffer…to be programmed to the NVM of the non-volatile storage device…” Thompson does not in fact teach transferring data from a write buffer to it’s first data buffer or second data buffer. Buxton is cited to teach transferring data from a write buffer to a first data buffer or second data buffer, so Buxton and Thompson combine to teach this limitation. Applicant argues on pages 8-9 that Thompson fails to teach the limitations of claim 5 and 15, These arguments are moot, as Buxton is now cited to the limitations of dependent claim 5 and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights