Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-12 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US PGPub 2020/0135270, hereafter “Lee,” in view of Thompson et al., US PGPub 2016/0268000, hereafter “Thompson.”
With respect to claim 1, Lee teaches a solid state drive (SSD) comprising:
a controller in the SSD (pars. 39-40 and fig. 1, memory controller 200 in SSD 50);
a write buffer in the SSD configured to store write data received from a host (par. 60 and fig. 1, write buffer 210); and
a non-volatile storage device in the SSD comprising a non-volatile memory (NVM) (par. 44 and fig. 1, the memory device 100, which may be a nonvolatile memory such as a NAND flash), a first data buffer, and a second data buffer (pars. 48-49 and fig. 1, the page buffer group 123, which includes a plurality of page buffers for storing the received data),
wherein the controller is configured to:
transfer the write data received from the host from the write buffer to the first data buffer and the second data buffer (par. 131, the page buffers store a plurality of data chunks received from the write buffer);
Lee fails to teach determining the particular write method of programming the non-volatile memory from the data buffers in response to a power failure.
Thompson teaches:
determine whether a power failure occurs (par. 33);
in response to determining that a power failure does not occur, configure the non-volatile device (fig. 2, Solid State Drive 200) to program the write data received from the host stored in at least one of the first data buffer (fig. 2A, write buffer 122) or the second data buffer (fig. 2A, system metadata 124) to the NVM in a first mode (pars. 32-33, in normal operating mode, data is written from write buffer 122 to the flash memory array in MLC mode); and
in response to determining that the power failure occurs, configure the non-volatile storage device to program the write data received from the host stored in at least one of the first data buffer or the second data buffer to the NVM in a second mode different from the first mode (par. 35, in power fail saving mode, a modified MLC page write operation is performed for data in the write buffer 122).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee and Thompson before him before the earliest effective filing date, to modify the flash memory of Lee with the flash memory of Thompson, in order to use a modified MLC page write operation mode in the event of a power failure, in order to eliminate the need to write an entire erase block, which supports saving essential volatile data during the holdup times, as taught by Thompson in pars. 35-36.
With respect to claim 2, Lee and Thompson teach the limitations of the parent claim. Thompson further teaches the SSD of claim 1, wherein the first mode is at least one of single-level cell (SLC) mode, multi-level cell (MLC) mode, triple-level cell (TLC) mode, or quad-level cell (QLC) mode (par. 32, MLC mode).
With respect to claim 4, Lee and Thompson teach the limitations of the parent claim. Lee further teaches the SSD of claim 1, wherein the controller comprises the write buffer (par. 60 and fig. 1, write buffer 210 in controller 200).
With respect to claim 5, Lee and Thompson teach the limitations of the parent claim. Thompson further teaches the SSD of claim 1, wherein the non-volatile storage device comprises a plurality of sub-systems each comprising a respective NVM (par. 42, there is more than one non-volatile memory 294, as there is a “separate non-volatile memory 294” referenced), the first data buffer comprises one or more program data buffers in each of the plurality of sub-systems (pars. 32-33 and fig. 2B, the write buffer 122 may be considered a program data buffer as it stores write data to be written to flash), and the second data buffer comprises one or more additional buffers in each of the plurality of sub-systems (par. 37 and fig. 2B, the system metadata 124 stored in DRAM is separate from the buffer 122, and thus may be considered an additional buffer).
With respect to claim 6, Lee and Thompson teach the limitations of the parent claim. Lee further teaches the SSD of claim 5, wherein the controller is configured to:
transfer write data received from the host from the write buffer to the one or more program data buffers and the one or more additional data buffers of a first sub-system of the plurality of sub-systems (par. 131, the first plurality of data chunks received from the write buffer are stored in the plurality of page buffers (one or more program data buffers), and the subsequent data received from write buffer are stored in the remaining page buffers (one or more additional data buffers));
Thompson teaches:
in response to determining that the power failure does not occur, configure the first sub-system to program, to the NVM of the first sub-system in the first mode, write data received from the host stored in at least one of the one or more program data buffers or the one or more additional data buffers of the first sub-system of the plurality of sub-systems (pars. 32-33, in normal operating mode, data is written from write buffer 122 to the flash memory array in MLC mode); and
in response to determining that the power failure occurs, configure the first sub-system to program, to the NVM of the first sub-system in the second mode, write data received from the host stored in in at least one of the one or more program data buffers or the one or more additional data buffers of the first sub- system (par. 35, in power fail saving mode, a modified MLC page write operation is performed for data in the write buffer 122).
With respect to claim 7, Lee and Thompson teach the limitations of the parent claim. Lee further teaches the SSD of claim 1, wherein the controller is configured to:
in response to transferring the write data received from the host from the write buffer to the first data buffer and the second data buffer, delete the write data received from the host from the write buffer (pars. 142-143, data is deleted from the write buffer after it has been programmed to the page buffer group).
With respect to claim 8, Lee and Thompson teach the limitations of the parent claim. Thompson further teaches the SSD of claim 1, wherein in response to determining that the power failure occurs, the device is configured to:
stop the programming in the first mode, and then start programming the write data received from the host stored in at least one of the first data buffer or the second data buffer to the NVM in the second mode (pars. 35-36, after detection of a power failure, the mode is switch from MLC mode as described in pars. 32-33, to the modified MLC mode).
With respect to claim 9, Lee and Thompson teach the limitations of the parent claim. Thompson further teaches the SSD of claim 1, wherein in response to determining that the power failure occurs, the controller is configured to program write data received from the host stored in the write buffer to the NVM in the second mode, while programming the data stored in at least one of the first data buffer or the second data buffer to the NVM in the second mode (pars. 35-37 and fig. 2B, following a power failure, data is written from write data buffer 122 to flash memory in modified MLC mode). Thompson doesn’t specify that the write from the write buffer to the NVM is in the second mode.
With respect to claim 10, Lee and Thompson teach the limitations of the parent claim. Lee further teaches the SSD of claim 1, wherein the controller is a solid state drive (SSD) controller system-on-chip (SoC) (pars. 40-41).
Claims 11-12 and 14-20 are a method that corresponds to system claims 1-10 and are rejected using similar logic.
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Thompson as applied to claims 1 and 11 above, and further in view of Buxton et al., US PGPub 2022/0300199, hereafter “Buxton.”
With respect to claim 3, Lee and Thompson teach the limitations of the parent claim, but Thompson teaches that the write data received from the host is written to the NVM in a modified MLC mode, not a pseudo SLC mode as required by claim 3. Buxton teaches the SSD system of claim 1, wherein the second mode is a pseudo single-level cell (pSLC) mode (pars. 52-53, in the event of a power failure, the data is written as pSLC).
It would have been obvious to one of ordinary skill in the art, having the teachings of Lee, Thompson and Buxton before him before the earliest effective filing date, to modify the SSD of Lee and Thompson with the SSD of Buxton, in order to implement pSLC in the event of power loss, as when a power failure event occurs, the SSD has a very limited amount of time to salvage any data payload, as taught by Buxton in pars. 52-53.
Claim 13 is a method that corresponds to system claim 3 and is rejected using similar logic.
Response to Arguments
Applicant's arguments filed 01/30/2026 have been fully considered but they are not persuasive. Firstly, the rejections under 35 USC 112 as being indefinite are withdrawn, due to the claim amendments. Applicant’s arguments on pages 7-8 are directed towards Thompson allegedly failing to teach that write data received from the host is stored to the NVM. In the prior office action, the examiner had, in fact, mapped the system data to the data that was written to the NVM in the second mode. Applicant is correct in stating that this is not write data received from the host. However, Thompson in the cited sections, teaches, in the event of a power failure, a writing mode that both A) writes system data to the NVM in pSLC mode, and B) writes data received from the host in a modified MLC mode. Applicant’s claim amendments necessitate the examiner to modify the rejection to clarify that the claimed second mode is the modified MLC mode, which is used to write the received host data to the NVM, thus teaching the claims as amended.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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