DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 and 9-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1, 9 and 10 recite a data processing method, a data processing apparatus, and a non-transitory device-readable storage media, respectively. Thus, each of the claims fall under one of the four statutory categories.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), the claim recites “determined by a row-column decomposition of pixel locations of the plurality of groups of data in an image”, “performing an extremum operation on the plurality of groups of data in parallel… to obtain a first group of intermediate results”, “concurrently comparing… data values… to generate an intermediate result of the first group of intermediate results”, and “determining an extreme value of the data set based on the first group of intermediate results”. Such limitations cover mathematical calculations, relationships, and/or formulas and mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). Therefore, the claim includes additional limitations that fall within the “mathematical concepts” and “mental processes” groupings of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The limitations “obtaining a plurality of groups of data from a data set… wherein each group of the plurality of groups of data comprises a respective portion of the data set”, “loading a first porting of the plurality of groups of data into a first set of channels of a first vector register of”, “loading a second portion of the plurality of groups of data into a second set of channels of a second vector register of the processing device… wherein each channel of the first set of channels and the second set of channels is configured to store a respective data value of a respective size”, “data values loaded into the respective channels of the corresponding pair of channels”, and “updating the first vector register with the intermediate result of the first group of intermediate results” are considered to be insignificant extra-step solution activity of data gathering (i.e., reading or loading data from memory) (MPEP 2106.05(g)) and does not integrate the abstract idea into a practical application (see MPEP 2106.05(g)). The claim additionally recites “a processing device”, “using a first vector instruction”, “using a second vector instruction”, “first set of channels is in one-to-one correspondence with the second set of channels of the processing device”, “each pair of channels comprising (i) a channel of the first set of channels and (ii) a corresponding channel of the second set of channels”, “using a condition selection instruction”, and “the first vector register”. However, the additional elements are recited at a high level of generality, i.e., generic instructions and generic hardware. Such elements amount to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). The claim additionally recites “the plurality of groups of data are obtained based on an offset”. However, the element is considered to be an insignificant extra-solution activity of calculating an address to fetch data from, which does not integrate the abstract idea into a practical application (see MPEP 2106.05(g)). Thus, the claim fails to integrate the judicial exception into a practical application.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to Step 2A Prong Two, the limitations do not amount to significantly more as data gathering has been deemed to be well-understood, conventional, and routine by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93), address calculation is deemed to be well-understood, conventional, and routine (see Steigerwalt, Col 1, lines 22-28) (see MPEP 2106.05(d)), and the additional elements in the claim amount to no more than mere instructions to apply the exception (see MPEP 2106.05(f)). Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 recites “perform a maximum operation”, “performing the extremum operation on the plurality of groups of data in parallel”, “performing a minimum operation the plurality of groups of data in parallel… to obtain a second group of intermediate results”, and “calculating a minimum value of the data set based on the second group of intermediate results.” Such limitations further cover mathematical calculations, relationships, and/or formulas. The claim additionally recites “the second vector instruction comprises an instruction” and “using a third vector instruction.” Such elements are recited at a high level of generality, i.e., generic instructions to indicate the execution of generic operations. Such elements amount to no more than mere instructions to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 recites “performing the minimum operation on the plurality of groups of data in parallel.” Such limitation further covers mathematical calculations, relationships, and/or formulas. The claim additionally recites “using the third vector instruction” and “after completing execution of the second instruction and before obtaining an execution result of the second instruction.” Such elements are recited at a high level of generality, i.e., generic instructions to indicate the execution of generic operations. Such elements amount to no more than mere instructions to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 recites “the first vector instruction and second vector instruction are instructions in a first looping code” and “the first vector instruction and the second vector instruction are alternately executed for a plurality of times during execution of the first looping code.” However, the additional elements are recited at a high level of generality, i.e., generic instructions to indicate the execution of generic operations. Such elements amount to no more than mere instructions to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 recites “a vector instruction for processing the data set comprises an instruction in a NEON instruction set or an SSE instruction set.” However, the additional limitation does no more than generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 recites “the data set comprises pixel data of an image data.” However, the additional limitation does no more than generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 recites “the offset is determined based on data consisting of column values representing the pixel locations of the plurality of groups of data in the image”. Such limitation further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 9 and 11-16 recite an apparatus similar to the method of claims 1-7, respectively. The only differences are that claim 9 includes the additional limitations “memory, configured to store instructions” and “processor, configured to execute instructions in the memory, wherein the processor comprises a first vector register and a second vector register, so as to perform operations”. Processor, memory, and vector registers are recited at a high level of generality, i.e., a generic system containing generic components to perform generic computer functions. Such element amounts to no more than mere instructions to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claims fail to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claims 10 and 17-20 recite a non-transitory device-readable storage media similar to the apparatus of claims 1-7, respectively. Claim 10 additionally recites “one or more non-transitory device-readable storage media storing instructions.” The element is recited at a high level of generality, i.e., generic components storing data, which amounts to no more than mere instructions to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claims fail to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stackoverflow (Find minimum and maximum value of an array using ARM NEON instructions, see Non-Final Action mailed June 9, 2025) in view of Graphics Mill (Accessing Pixel Data, See Non-Final Action mailed May 4, 2026).
NEON Programmer’s Guide (411 Pages, cited by Applicant on May 17 2024) and ARM Compiler toolchain Using the Assembler (2 pages, cited by Examiner on June 9 2025) and Using as (2 pages, cited by Examiner on June 9 2025) are cited as extrinsic evidence.
Regarding claim 1, Stackoverflow teaches a data processing method, comprising:
obtaining a plurality of groups of data from a data set using a first vector instruction (Jake 'Alquimista' LEE’s answer: Using vld1.8 to load 32 bytes into two registers, 16 bytes written into each vector register (see NEON Programmer’s Guide, p. 6-4). The vld1.8 instruction as the first vector instruction), wherein each group of the plurality of groups of data comprises a respective portion of the dataset (The vector registers comprise of a plurality of data up to 16 bytes each register, based on the format of the VLD instruction),
Performing an extremum operation on the plurality of groups of data in parallel using a second vector instruction to obtain a first group of intermediate results (Jake 'Alquimista' LEE’s answer: The user uses vmax.u8 on each register containing the plurality of groups of data to find the maximum value between qmax1 or qmax2 over q8-q15 and stores the group of intermediate results on qmax1 and qmax2 (see NEON Programmer’s Guide, p. C-48). The vmax instruction is a vector instruction, where vector instructions process data in parallel. The syntax indicates the qmax1/qmax2 register as the destination operand and the first source operand (see ARM Compiler toolchain Using the Assembler, p. 5-39, table 5-8). For example, “vmax.u8 qmax1, q8” is the same as “vmax.u8 qmax1, qmax1, q8.” Finding the max value using vmax.u8 as the extremum operation and vmax.u8 as the second vector instruction) wherein performing the extremum operation comprises:
loading a first portion of the plurality of groups of data into a first set of channels of a first vector register of a processing device (Jake 'Alquimista' LEE’s answer: The vector registers can be modified to hold different sized data elements depending on the loading instruction parameters. qmax1 loaded with the data elements of q8 as the first vector register. Each data element stored in a vector register is a channel where each register hold a set of channels. qmax1 with the set of channels as the first set of channels. The vector registers are ARM registers, therefore they come from an ARM processing device),
loading a second portion of the plurality of groups of data into a second set of channels of a second vector register of the processing device (Jake 'Alquimista' LEE’s answer: The vector registers can be modified to hold different sized data elements depending on the loading instruction parameters. q10 loaded with the data from pSrc as the second vector register. Each data element stored in a vector register is a channel where each register hold a set of channels. q10 with the set of channels as the second set of channels. The vector registers are ARM registers, therefore they come from an ARM processing device), wherein the first set of channels is in one-to-one correspondence with the second set of channels of the processing device (Jake 'Alquimista' LEE’s answer: The elements loaded into q8 is loaded using instruction vld1.u8, which indicates 8-bit data elements, then qmax1 is loaded with the data elements of q8. q10 is loaded the same way as q8, therefore the register’s data elements are aligned “one-to-one” of each other), wherein each channel of the first set of channels and the second set of channels is configured to store a respective data value of a respective size (Jake ‘Alquimista’ LEE’s answer: The prior load instructions vld1.8 is set to load each data element with a size of 8 bits per element. The data element stored in each position of each vector register as the respective data value and the size of the data element as the respective size), and
concurrently comparing, for each pair of channels comprising (i) a channel of the first set of channels and (ii) a corresponding channel of the second set of channels, data values loaded into the respective channels of the corresponding pair of channels using a condition selection instruction (Jake 'Alquimista' LEE’s answer: The instruction vmax.u8 compares each data element between each element starting with the first data element of each register. Therefore the comparisons occur between each pair of channels. The vmax.u8 instruction is a condition selection instruction since it compares the values between two registers to see which of the two have the largest value in a given channel (the condition) and selects the largest values between the two registers), to generate an intermediate result of the first group of intermediate results (Jake 'Alquimista' LEE’s answer: Once the vmax.u8 instruction is completed, the instruction will generate the intermediate result);
updating the first vector register with the intermediate result of the first group of intermediate results (Jake 'Alquimista' LEE’s answer: The intermediate results are stored in qmax1, updating qmax1); and
determining an extreme value of the data set based on the first group of intermediate results in the first vector register (Jake 'Alquimista' LEE’s answer: A maximum value is calculated using a mix of vmax.u8 between the intermediate results stored in qmax1 and qmax2. vpmax.u8 is used to find the max value by continuously comparing adjacent pairs in each vector (see NEON Programmer’s Guide, p. C-50), storing the results in dmaxa and eventually store the max value in r1. The maximum value as the extreme value. dmaxa and dmaxb (i.e., d2 and d3) are the lower bits and upper bits of qmax1 (i.e., q1), respectively (see NEON Programmer’s Guide, p. 1-12)).
Stackoverflow does not teach that the plurality of groups of data are obtained based on an offset determined by a row-column decomposition of pixel locations of the plurality of groups of data in an image.
Graphics Mill teaches to obtain data based on an offset determined by a row-column decomposition of pixel locations of an image (Low-Level Access, How to Access Pixels Directly: Pixel data of an image located on row “i" and column “j” (i.e., a pixel location) can be accessed by utilizing the “result” formula (i.e., using a row “i" and column “j” offset, which is a row-column decomposition. See specification [0034])).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Stackoverflow with the teachings of Graphics Mill to have fetched the groups of data based on an offset determined by a row-composition of pixel locations. One of ordinary skill would appreciate the flexibility of being able to fetch specific pixel data for processing if one of ordinary skill requires specific pixels to be processed/analyzed.
Regarding claim 2, Stackoverflow, in view of Graphics Mill, teaches the method according to claim 1, wherein the second vector instruction comprises an instruction that, once executed, causes to perform a maximum operation (Stackoverflow, Jake 'Alquimista' LEE’s answer: The maximum operation is finding the max value in a data set using the vector registers q8-q15 using the vmax.u8), and performing the extremum operation on the plurality of groups of data in parallel the method further comprises:
Performing a minimum operation on the plurality of groups of data in parallel using a third vector instruction to obtain a second group of intermediate results (Stackoverflow, Jake 'Alquimista' LEE’s answer: vmin.u8 is executed on vector registers q8-q15 and the second group of intermediate results are stored in qmin1 and qmin2 (see NEON Programmer’s Guide, p. C-48). The vmin instruction is a vector instruction, where vector instructions process data in parallel. The syntax indicates the qmin1/qmin2 register as the destination operand and the first source operand (see ARM Compiler toolchain Using the Assembler, p. 5-39, table 5-8). For example, “vmin.u8 qmin1, q8” is the same as “vmin.u8 qmin1, qmin1, q8.” vmin.u8 as the third vector instruction and performs the minimum operation); and
calculating a minimum value of the data set based on the second group of intermediate results (Stackoverflow, Jake 'Alquimista' LEE’s answer: A minimum value is calculated using a mix of vmin.u8 between the intermediate results qmin1 and qmin2. vpmin.u8 is used to find the minimum value by continuously comparing adjacent pairs in each vector (see NEON Programmer’s Guide, p. C-50), storing the results in dmina and eventually store the max value in r0. The maximum value as the extreme value. dmina and dminb (i.e., d0 and d1) are the lower bits and upper bits of qmin1 (i.e., q0), respectively (See NEON Programmer’s Guide, p. 1-12)).
Regarding claim 4, Stackoverflow, in view of Graphics Mill,, teaches the method according to claim 2, wherein the first vector instruction and the second vector instruction are instructions in a first looping code (Stackoverflow, Jake 'Alquimista' LEE’s answer: Label “1” is the loop and instructions vmax.u8 and vld1.8 are located within the loop. Once the processor reaches bpl (branch if positive or zero), to loop back to “1b” where “b” indicates a backward branch (see Using as, 5.3 Symbol Names, Local Labels)), and the first vector instruction and the second vector instruction are alternately executed for a plurality of times during execution of the first looping code (Stackoverflow, Jake 'Alquimista' LEE’s answer: vld1.8 executes 4 times before alternating to vmax.u8, which is executed 8 times in each loop that occurs).
Regarding claim 5, Stackoverflow, in view of Graphics Mill, teaches the method according to claim 1, wherein a vector instruction for processing the data set comprises an instruction in a NEON instruction set (Stackoverflow, Jake 'Alquimista' LEE’s answer: The vector instructions vmin.u8 and vmax.u8 are instructions from the NEON instruction set (see NEON Programmer’s Guide, p. C-48)).
Regarding claim 6, Stackoverflow, in view of Graphics Mill, teaches the method according to claim 1, wherein the data set comprises pixel data of an image data (Stackoverflow, Comment on Jake 'Alquimista' LEE’s answer by the asker of the question, Zoli: The user intended to use this answer to process pixel data of an image, where pixel data is associated to an image’s data).
Regarding claim 7, Stackoverflow, in view of Graphics Mill, teaches the method according to claim 6.
Stackoverflow, in view of Graphics Mill, does not explicitly teach that the offset is determined based on data consisting of column values representing the pixel locations of the plurality of groups of data in the image.
Graphics Mill also teaches data consisting of column values representing the pixel locations of an image (Low-Level Access, How Pixels Are Stored in Memory: Pixels of an image are stored linearly, meaning that the pixel data is stored row-by row in succession in memory. Therefore, when retrieving pixel data of an image, the data retrieved is column data (i.e., values) of a row, that data representing a pixel location of an image).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of Stackoverflow with the teachings of Graphics Mill to have the data consist of column values representing the pixel locations of an image. By having pixel data stored in that format, one of ordinary skill may be able to perform operations on rows of data without requiring complex calculation to be able to read each column value of each row. Furthermore, one of ordinary skill may be able to read the pixel data stored in memory during debugging processes without requiring special tools or assistance in reading the pixel data, which may be appreciated.
Claim(s) 3 and 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stackoverflow (Find minimum and maximum value of an array using ARM NEON instructions, see Non-Final Action mailed June 9, 2025) in view of Graphics Mill (Accessing Pixel Data, See Non-Final Action mailed May 4, 2026) and Anderson et al. (US 20190196790 A1).
NEON Programmer’s Guide (411 Pages, cited by Applicant on May 17 2024) and ARM Compiler toolchain Using the Assembler (2 pages, cited by Examiner on June 9 2025) and Using as (2 pages, cited by Examiner on June 9 2025) are cited as extrinsic evidence.
Regarding claim 3, Stackoverflow, in view of Graphics Mill, teaches the method according to claim 2, wherein performing the minimum operation on the plurality of groups of data in parallel using the third vector instruction (Stackoverflow, Jake 'Alquimista' LEE’s answer: The vmin.u8 instruction finds the minimum values between two vectors) comprises:
performing the minimum operation on the plurality of groups of data in parallel using the third vector instruction (Stackoverflow, Jake 'Alquimista' LEE’s answer: After the execution of the first instance of vmax.u8, vmin.u8 is executed afterwards).
However, Stackoverflow, in view of Graphics Mill, does not explicitly teach completing execution of the second vector instruction and before obtaining an execution result of the second instruction.
Here, Anderson teaches completing execution of a (Figs. 4A and 4B, [0083-0084]: The processor pipeline includes multiple stages, so an instruction executed would not be completed until it reaches at the end of the pipeline. Before the instruction is finished, a second instruction may be processed).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Stackoverflow, in view of Graphics Mill, with the teachings of Anderson to execute instructions in a pipelined architecture, where an instruction may be executed, but prior to receiving results of the instruction. Pipelining increases the throughput of instructions per a given time compared to a non-pipelined architecture. Additionally, it improves CPU utilization by having each critical section do some kind of work rather than being idle in a non-pipelined architecture.
Regarding claims 9, the claim is mostly rejected for the same reasons as claim 1.
Stackoverflow, in view of Graphics Mill, does not teach a data processing apparatus, comprising: memory, configured to store instructions and a processor, configured to execute instructions in the memory, wherein the processor comprises a first vector register and a second vector register.
Anderson does teach a data processing apparatus, comprising: memory, configured to store instructions ([0123]: Instructions may be stored in any of mediums listed in the paragraph) and a processor, configured to execute instructions in the memory (Fig 4B and [0090]: Core 490), wherein the processor comprises of vector registers (Fig. 3 and ]0078]: The processor supports a register architecture of 32 vector registers 310).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Stackoverflow, in view of Graphics Mill, with the teachings of Anderson to have stored the instructions in memory and to be processed by a processor. A processor is capable of executing various instructions based on the architecture of the processor. Additionally, any kind of non-transitory media can encode and store instructions so that the processor can fetch the instructions for later processing and execution, which plays a part in allowing data to be processed from functions and algorithms that one of ordinary skill would create.
Regarding claim 11, Stackoverflow, in view of Graphics Mill and Anderson, teaches the data processing apparatus according to claim 9, wherein the second vector instruction comprises an instruction that, once executed, causes to perform a maximum operation (Stackoverflow, Jake 'Alquimista' LEE’s answer: The maximum operation is finding the max value in a data set using the vector registers q8-q15 using vmax.u8), and performing the extremum operation on the plurality of groups of data further comprises:
performing a minimum operation on the plurality of groups of data in parallel using a third vector instruction to obtain a second group of intermediate results (Stackoverflow, Jake 'Alquimista' LEE’s answer: vmin.u8 is executed on vector registers q8-q15 and the second group of intermediate results are stored in qmin1 and qmin2 (see NEON Programmer’s Guide, p. C-48). The vmin instruction is a vector instruction, where vector instructions processes data in parallel. The syntax indicates the qmin1/qmin2 register as the destination operand and the first source operand (see ARM Compiler toolchain Using the Assembler, p. 5-39, table 5-8). For example, “vmin.u8 qmin1, q8” is the same as “vmin.u8 qmin1, qmin1, q8.” vmin.u8 as the third vector instruction and performs the minimum operation); and
calculating a minimum value of the data set based on the second group of intermediate results (Stackoverflow, Jake 'Alquimista' LEE’s answer: A minimum value is calculated using a mix of vmin.u8 between the intermediate results qmin1 and qmin2. vpmin.u8 is used to find the minimum value by continuously comparing adjacent pairs in each vector (see NEON Programmer’s Guide, p. C-50), storing the results in dmina and eventually store the max value in r0. The maximum value as the extreme value. dmina and dminb (i.e., d0 and d1) are the lower bits and upper bits of qmin1 (i.e., q0), respectively (See NEON Programmer’s Guide, p. 1-12)).
Regarding claim 12, Stackoverflow, in view of Graphics Mill and Anderson, teaches a data processing apparatus, which is similar to the method of claim 3, therefore the claim is rejected on the same premises
Regarding claim 13, Stackoverflow, in view of Graphics Mill and Anderson, teaches the data processing apparatus according to claim 11, wherein the first vector instruction and the second vector instruction are instructions in a first looping code (Stackoverflow, Jake 'Alquimista' LEE’s answer: Label “1” is the loop and instructions vmax.u8 and vld1.8 are located within the loop. Once the processor reaches bpl (branch if positive or zero), to loop back to “1b” where “b” indicates a backward branch (see Using as, 5.3 Symbol Names, Local Labels)), and the first vector instruction and the second vector instruction are alternately executed for a plurality of times during execution of the first looping code (Stackoverflow, Jake 'Alquimista' LEE’s answer: vld1.8 executes 4 times before alternating to vmax.u8, which is executed 8 times in each loop that occurs).
Regarding claim 14, Stackoverflow, in view of Graphics Mill and Anderson, teaches the data processing apparatus according to claim 9, wherein a vector instruction for processing the data set comprises an instruction in a NEON instruction set or an SSE instruction set (Stackoverflow, Jake 'Alquimista' LEE’s answer: The vector instructions vmin.u8 and vmax.u8 are instructions from the NEON instruction set (see NEON Programmer’s Guide, p. C-48)).
Regarding claim 15, Stackoverflow, in view of Graphics Mill and Anderson, teaches the data processing apparatus according to claim 9, wherein the data set comprises pixel data of an image data (Stackoverflow, Comment on Jake 'Alquimista' LEE’s answer by the asker of the question, Zoli: The user intended to use this answer to process pixel data of an image, where pixel data is associated to an image’s data).
Regarding claim 16, Stackoverflow, in view of Graphics Mill and Anderson, teaches the data processing apparatus according to claim 15.
Stackoverflow, in view of Graphics Mill and Anderson, does not explicitly teach that the offset is determined based on data consisting of column values representing the pixel locations of the plurality of groups of data in the image.
Graphics Mill also teaches data consisting of column values representing the pixel locations of an image (Low-Level Access, How Pixels Are Stored in Memory: Pixels of an image are stored linearly, meaning that the pixel data is stored row-by row in succession in memory. Therefore, when retrieving pixel data of an image, the data retrieved is column data (i.e., values) of a row, that data representing a pixel location of an image).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have further combined the teachings of Stackoverflow, in view of Anderson, with the teachings of Graphics Mill to have the data consist of column values representing the pixel locations of an image. By having pixel data stored in that format, one of ordinary skill may be able to perform operations on rows of data without requiring complex calculation to be able to read each column value of each row. Furthermore, one of ordinary skill may be able to read the pixel data stored in memory during debugging processes without requiring special tools or assistance in reading the pixel data, which may be appreciated.
Regarding claims 10 and 17-20, Stackoverflow, in view of Graphics Mill and Anderson, teaches a non-transitory device-readable storage media (see Anderson, [0124]) and recites a set of non-transitory device-readable storage claims, which are similar to the data processing apparatus of claims 9 and 11-14, respectively, and are therefore rejected on the same premises
Response to Arguments
Applicant's arguments, see page 9, fourth paragraph to page 13, paragraph 2, with respect to the rejection of claims 1-7 and 9-20 under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding arguments on page 10, paragraph 4 to page 11, paragraph 1, Applicant argues that claims 1, 9, and 10 are not directed to an abstract idea because the claims are tied to a physical architecture, resulting in limitation that cannot be performed in the human mind.
See MPEP 2106 regarding patent subject matter eligibility. Examiner respectfully disagrees with this argument. Each of the independent claims recite mental/mathematical limitations with respect to comparing and finding the minimum and maximum values (as stated in the 101 rejection analysis). The Applicant uses computer components, such as vector registers, as tools to perform the abstract idea, which doesn’t integrate the judicial exception into a practical application or provide an inventive concept (see 2106.05(f)(2), paragraphs 1-2). Therefore, Applicant’s remarks regarding that the claims do not recite an abstract idea is considered not persuasive.
Regarding arguments on page 11, paragraph 2 and page 11 paragraph 5 to page 12, paragraph 1, Applicant argues that the claims are integrated into a practical application by providing an improvement to the functioning of a computer.
Examiner respectfully disagrees with this argument. Examiner has addressed this argument in pages 24-25 of the Final Office Action mailed October 29, 2025 and pages 23-24 of the Non-Final Office Action mailed May 4, 2026. For the sake of brevity, Examiner will not re-address this argument.
Regarding arguments on page 11, paragraphs 3, Applicant argues that the limitation of obtaining “the plurality of groups of data… based on an offset” is a limitation that provides a concrete improvement to the functioning of the computer’s memory system, and therefore integrates the abstract idea into a practical application.
See MPEP 2106.05(d) regarding well-understood, routine, conventional activity and MPEP 2106.05(a) regarding improvements to the functioning of a computer. Examiner respectfully disagrees with this argument. The improvement that Applicant points to in which this limitation provides is not sufficient. Paragraph [0034] of Applicant’s specification states that “if eight data elements in column 1 to column 8 in row 2000 need to be acquired, an offset may be calculated from the first data element in row 2000, so that eight data elements in column 1 to column 8 in row 2000 may be quickly acquired. In addition, an amount of data that needs to be cached in a memory is greatly reduced, thereby improving memory locality during acquiring of image data.”, which sets forth the improvement in a conclusory manner. Furthermore, Examiner is unsure how there is a reduction in data to be cached and the specification fails to provide any explanation. Therefore, the limitation does not provide an improvement (See MPEP 2106.05(a), paragraph 3). Therefore, Applicant’s arguments regarding that the limitation recites an improvement is considered not persuasive.
Regarding arguments on page 11, paragraph 4, Applicant argues that the currently amended claim 1 recites “concurrently comparing… data values loaded into the respective channels of the corresponding pair of channels using a condition selection instruction”, which recites an improvement, and therefore integrates the abstract idea into a practical application.
See MPEP 2106.05(a) regarding improvements to the functioning of a computer. Examiner respectfully disagrees with this argument. The improvement that Applicant points to in which this limitation provides is not sufficient. Paragraph [0050] of Applicant’s specification states that “a condition selection instruction may be used for comparison, so that a problem of a CPU branch prediction failure may be avoided, helping improve the data processing speed”, which sets forth the improvement in a conclusory manner. Therefore, the limitation does not provide an improvement (See MPEP 2106.05(a), paragraph 3). Therefore, Applicant’s arguments regarding that the limitation recites an improvement is considered not persuasive.
The rejections of claims 1-7 and 9-20 under 35 U.S.C. 101 will be maintained.
Applicant's arguments, see page 12, paragraph 3 to page 13, paragraph 2, with respect to the rejection of claims 1-7 and 9-20 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Regarding arguments on page 12, paragraph 4 to page 13, paragraph 1, Applicant argues that Stackoverflow does not load a first portion of the data set into qmax1.
Examiner respectfully disagrees. The limitation does not restrict what occurs to the qmax1 register prior to loading a first portion of the plurality of groups of data into the qmax1 register. Therefore, even though there’s a prior initialization of “#0” into the qmax1 register, it later initializes with data of the plurality of groups of data within the loop (see page 2, first instance of vmax.u8), meeting the requirements of the limitation. Therefore, Applicant’s arguments regarding that Stackoverflow does not teach the particular limitation is considered not persuasive.
The rejections of claims 1-7 and 9-20 under 35 U.S.C. 103 will be maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
