DETAILED ACTION
This Office Action is in response to the application filed on 28 September 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 8, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Youn et al. (US 2011/0037158 A1; hereinafter Youn).
In regards to claim 1, Youn teaches, e.g. figs. 1, 14A-18, a semiconductor package comprising:
a package substrate (310) [0103];
a plurality of memory chips (CG1/CG2) [0102] stacked over the package substrate; and
a control chip (360) [0103] disposed over the package substrate to be spaced apart from the plurality of memory chips,
wherein the control chip includes:
a plurality of first chip enable signal control pads (some instances of (365)) [0105] connected to connected to transmitting chip enable signals to and from the plurality of memory chips ([0103-0105]: (360) controls (CG1/CG2) through the electrical connections of (365/370/308/wiring connections in or on 310/302/etc.));
a plurality of second chip enable signal control pads (other instances of (365)) [0105] transmitting the chip enable signals to and from an external electronic device external to the semiconductor package ([0103-0105]: connected to external devices through (370/308/wiring connections in or on 310/304/320));
a chip enable signal control circuit configured to control transmission paths of the chip enable signals between the plurality of first chip enable signal control pads and the plurality of second chip enable signal control pads ([0102-0103], [0106-0107]); and
a third chip enable signal control pad ((304) connected to (320)) [0111] receiving a path control signal from the external electronic device for controlling the chip enable signal control circuit [0111].
In regards to claim 6, Youn teaches, e.g. figs. 1, 14A-18, the limitations discussed above in addressing claim 1. Youn further teaches the limitations
wherein each of the plurality of memory chips includes a chip body (e.g. body portions of (330a/330b)) and includes chip enable pads ((335a/335b) connected to (340a/340b)) [0105] disposed on an upper surface of the chip body to transmit the chip enable signals to the package substrate [0105], and
wherein the package substrate includes:
a substrate body (body of (310)) [0103] having first (upper) and second (lower) surfaces that are on opposite sides of each other (fig. 14A);
a plurality of memory chip connecting fingers (626/630) disposed on the first surface of the substrate body and electrically connected to the chip enables pads of the plurality of memory chips [0053];
a plurality of first control chip connecting pads (some instances of (308)) [0104], a plurality of second control chip connecting pads (other instances of (308)) [0104], and a third control chip connecting pad that are disposed on the first surface of the substrate body and electrically connected to the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad, respectively ([0103-0105]: (360) controls (CG1/CG2) through the electrical connections of (365/370/308/wiring connections in or on 310/302/etc.)); and
a plurality of connecting lands (320) [0104] disposed on the second surface of the substrate body electrically connect with the external electronic device [0104].
In regards to claim 8, Youn teaches, e.g. figs. 1, 14A-18, the limitations discussed above in addressing claim 1. Youn further teaches the limitations
wherein each of the plurality of memory chips (CG1/CG2) [0102] includes a chip body and includes chip enable pads (135a/135b) [0070] disposed on a surface of the chip body to transmit the chip enable signals to the package substrate (e.g. figs. 6), and
wherein the package substrate includes:
a substrate body (e.g. the body of 310) having first (upper) and second (lower) surfaces that are on opposite sides of each other [0103];
a plurality of memory chip connecting fingers (626/630) [0053] disposed on the first surface of the substrate body and electrically connected to the chip enable pads of the plurality of memory chips [0053];
a plurality of first control chip connecting fingers (626/630), a plurality of second control chip connecting fingers, and a third control chip connecting finger which are disposed on the first surface of the substrate body and electrically connected to the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad, respectively [0053]; and
a plurality of connecting lands (320) [0104] disposed on the second surface of the substrate body to electrically connect with the external electronic device [0104].
In regards to claim 10, Youn teaches, e.g. figs. 1, 14A-18, the limitations discussed above in addressing claim 1. Youn further teaches the limitations wherein the plurality of memory chips are NAND flash memory chips [0101].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn as applied to claim 1 above, in view of Lee et al. (US 2012/0098569 A1; hereinafter Lee).
In regards to claim 2, Youn teaches the limitations discussed above in addressing claim 1. Youn appears to be silent as to, but does not preclude, the limitations wherein the chip enable signal control circuit includes: a plurality of input nodes electrically connected to the plurality of first chip enable signal control pads; a plurality of output nodes electrically connected to the plurality of second chip enable signal control pads; and a plurality of bypass nodes receiving the chip enable signals from the plurality of input nodes and transmitting the received chip enable signals to corresponding output nodes, among the plurality of output nodes, and wherein the corresponding output nodes are determined based on the path control signal input from the third chip enable signal control pad into the plurality of bypass nodes. Lee teaches the limitations wherein the chip enable signal control circuit includes:
a plurality of input nodes electrically connected to the plurality of first chip enable signal control pads ([0006], [0041], [0056]);
a plurality of output nodes electrically connected to the plurality of second chip enable signal control pads ([0006], [0041], [0056]); and
a plurality of bypass nodes receiving the chip enable signals from the plurality of input nodes and transmitting the received chip enable signals to corresponding output nodes, among the plurality of output nodes ([0006], [0041], [0056]), and
wherein the corresponding output nodes are determined based on the path control signal input from the third chip enable signal control pad into the plurality of bypass nodes ([0006], [0041], [0056]).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
In regards to claim 3, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 2. Lee further teaches the limitations
wherein at least one of the plurality of input nodes blocks the chip enable signal, input from a corresponding memory chip, among the plurality of memory chips, from being transmitted to the plurality of bypass nodes according to the path control signal ([0006], [0041], [0056]), and
wherein the plurality of bypass nodes receive the chip enable signals transmitted through the input nodes except for the at least one of the plurality of input nodes and assign the plurality of output nodes to which the received chip enable signals are output ([0006], [0041], [0056]).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
In regards to claim 4, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 3. Lee further teaches the limitations wherein the plurality of output nodes are consecutively and sequentially assigned from a highest priority node ([0006], [0041], [0056]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
In regards to claim 5, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 3. Lee further teaches the limitations wherein the plurality of second chip enable signal control pads receive the chip enable signals through the assigned output nodes and transmit the chip enable signals to the package substrate ([0006], [0041], [0056]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn as respectively applied to claims 6 and 8 above, in view of Kim (US 2017/0103965 A1; hereinafter Kim).
In regards to claim 7, Youn teaches the limitations discussed above in addressing claim 6. Youn further teaches, e.g. figs. 1, 14A-18, the limitations further comprising:
bonding wires electrically (340a/340b) [0105] connecting the chip enable pads of the plurality of memory chips to the plurality of memory chip connecting fingers (626/630) of the package substrate [0053];
first substrate interconnections (some instances of wiring connections in or on (310)) electrically connecting the plurality of memory chip connecting fingers to the plurality of first control chip connecting pads [0103-0105];
second substrate interconnections (other instances of wiring connections in or on (310)) electrically connecting the plurality of second control chip connecting pads to corresponding connecting lands, among the plurality of connecting lands [0103-0105]; and
a third substrate interconnection (yet other instances of wiring connections in or on (310)) electrically connecting the third control chip connecting pad to a corresponding connecting land [0103-0105].
Youn appears to be silent as to, but does not preclude, the limitations of connecting bumps electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting pads, the plurality of second control chip connecting pads, and the third control chip connecting pad, respectively. Kim teaches the limitations of connecting bumps electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting pads, the plurality of second control chip connecting pads, and the third control chip connecting pad, respectively [0054]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Kim to control device spacing to manage heat dissipation (Kim [0003], [0005]).
In regards to claim 9, Youn teaches the limitations discussed above in addressing claim 8. Youn further teaches, e.g. figs. 1, 14A-18, the limitations further comprising:
first bonding wires (340a/340b) [0105] electrically connecting the chip enable pads of the plurality of memory chips to the plurality of memory chip connecting fingers (626/630) of the package substrate [0053];
first substrate interconnections (some instances of wiring connections in or on (310)) electrically connecting the plurality of memory chip connecting fingers to the plurality of first control chip connecting fingers [0103-0105];
second substrate interconnections (other instances of wiring connections in or on (310)) electrically connecting the plurality of second control chip connecting fingers to corresponding connecting lands, among the plurality of connecting lands [0103-0105]; and
a third substrate interconnection (yet other instances of wiring connections in or on (310)) electrically connecting the third control chip connecting finger to a corresponding connecting land, among the plurality of connecting lands [0103-0105].
Youn appears to be silent as to, but does not preclude, the limitations of second bonding wires electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting fingers, the plurality of second control chip connecting fingers, and the third control chip connecting finger, respectively. Kim teaches the limitations of second bonding wires electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting fingers, the plurality of second control chip connecting fingers, and the third control chip connecting finger, respectively [0054]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Kim to control device spacing to manage heat dissipation (Kim [0003], [0005]).
Claim(s) 11-15, 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Youn, in view of Lee.
In regards to claim 11, Youn teaches, e.g. figs. 1, 14A-18, a semiconductor package comprising:
a package substrate (310) [0103] including a substrate body (body of (310)) [0103] having first (upper) and second (lower) surfaces that are on opposite sides of each other (fig. 14A);
a plurality of memory chips (CG1/CG2) [0102] stacked over the first surface of the substrate body; and
a control chip (360) [0103] disposed over the first surface of the substrate body and including a chip enable signal control circuit configured to control transmission paths of chip enable signals between the plurality of memory chips and an external electronic device outside the semiconductor package ([0102-0103], [0106-0107]).
Youn appears to be silent as to, but does not preclude, the limitations wherein the chip enable signal control circuit includes: a plurality of input nodes receiving the chip enable signals from the plurality of memory chips; a plurality of bypass nodes, based on a path control signal transmitted from the external electronic device, controlling the transmission paths of the chip enable signals received from the plurality of input nodes; and a plurality of output nodes outputting the chip enable signals transmitted to the package substrate by the plurality of bypass nodes through the controlled transmission path.
Lee teaches the limitations wherein the chip enable signal control circuit includes:
a plurality of input nodes receiving the chip enable signals from the plurality of memory chips ([0006], [0041], [0056]);
a plurality of bypass nodes, based on a path control signal transmitted from the external electronic device, controlling the transmission paths of the chip enable signals received from the plurality of input nodes ([0006], [0041], [0056]); and
a plurality of output nodes outputting the chip enable signals transmitted to the package substrate by the plurality of bypass nodes through the controlled transmission path ([0006], [0041], [0056]).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
In regards to claim 12, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 11. Lee further teaches the limitations
wherein at least one of the plurality of input nodes blocks the chip enable signal, input from a corresponding memory chip, among the plurality of memory chips, from being transmitted to the plurality of bypass nodes according to the path control signal ([0006], [0041], [0056]), and
wherein the plurality of bypass nodes receive the chip enable signals transmitted through the input nodes except for the at least one of the plurality of input nodes and assign the plurality of output nodes to which the received chip enable signals are output ([0006], [0041], [0056]).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
In regards to claim 13, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 11. Lee further teaches the limitations wherein the plurality of output nodes are consecutively and sequentially assigned from a highest priority node ([0006], [0041], [0056]). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
In regards to claim 14, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 11. Lee further teaches the limitations wherein the control chip includes:
a plurality of first chip enable signal control pads electrically connected to the plurality of input nodes and transmitting the chip enable signals to and from the plurality of memory chips ([0006], [0041], [0056]);
a plurality of second chip enable signal control pads electrically connected to the plurality of output nodes and transmitting the chip enable signals to and from the external electronic device ([0006], [0041], [0056]); and
a third chip enable signal control pad receiving the path control signal transmitted from the external electronic device ([0006], [0041], [0056]).
It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Youn with the aforementioned limitations taught by Lee to have a custom logic circuit (Lee [0006]).
In regards to claim 15, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 14. Youn further teaches, e.g. figs. 1, 14A-18, the limitations
wherein each of the plurality of memory chips (CG1/CG2) [0102] includes a chip body and includes chip enable pads (135a/135b) [0070] disposed on an upper surface of the chip body to transmit and receive the chip enable signals (e.g. figs. 6), and
wherein the package substrate includes:
a plurality of memory chip connecting fingers (626/630) [0053] disposed on the first surface (upper) of the substrate body and electrically connected to the chip enable pads of the plurality of memory chips [0053];
a plurality of first control chip connecting pads (some instances of (308)) [0104], a plurality of second control chip connecting pads (other instances of (308)) [0104], and a third control chip connecting pad which are disposed on the first surface of the substrate body and electrically connected to the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad, respectively ([0103-0105]: (360) controls (CG1/CG2) through the electrical connections of (365/370/308/wiring connections in or on 310/302/etc.)); and
a plurality of connecting lands (320) [0104] disposed on the second surface of the substrate body to electrically connect with the external electronic device [0104].
In regards to claim 17, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 14. Youn further teaches, e.g. figs. 1, 14A-18, the limitations
wherein each of the plurality of memory chips (CG1/CG2) [0102] includes a chip body, and chip enable pads (135a/135b) [0070] disposed on an upper surface of the chip body to transmit the chip enable signals (e.g. figs. 6), and
wherein the package substrate includes:
a substrate body (e.g. the body of 310) having first (upper) and second (lower) surfaces that are on opposite sides of each other [0103];
a plurality of memory chip connecting fingers (626/630) [0053] disposed on the first surface of the substrate body and electrically connected to the chip enable pads of the plurality of memory chips [0053];
a plurality of first control chip connecting fingers (626/630), a plurality of second control chip connecting fingers, and a third control chip connecting finger which are disposed on the first surface of the substrate body and electrically connected to the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad, respectively [0053]; and
a plurality of connecting lands (320) [0104] disposed on the second surface of the substrate body to electrically connect with the external electronic device [0104].
In regards to claim 19, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 11. Youn further teaches, e.g. figs. 1, 14A-18, the limitations wherein the plurality of memory chips are NAND flash memory chips [0101].
Claim(s) 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Youn and Lee as respectively applied to claims 15 and 17 above, and further in view of Kim.
In regards to claim 16, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 15. Youn further teaches, e.g. figs. 1, 14A-18, the limitations further comprising:
first bonding wires (340a/340b) [0105] electrically connecting the chip enable pads of the plurality of memory chips to the plurality of memory chip connecting fingers (626/630) of the package substrate [0053];
first substrate interconnections (some instances of wiring connections in or on (310)) electrically connecting the plurality of memory chip connecting fingers to the plurality of first control chip connecting pads [0103-0105];
second substrate interconnections (other instances of wiring connections in or on (310)) electrically connecting the plurality of second control chip connecting pads to corresponding connecting lands, among the plurality of connecting lands [0103-0105]; and
a third substrate interconnection (yet other instances of wiring connections in or on (310)) electrically connecting the third control chip connecting pad to a corresponding connecting land, among the plurality of connecting lands [0103-0105].
The combination of Youn and Lee appears to be silent as to, but does not preclude, the limitations of connecting bumps electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting pads, the plurality of second control chip connecting pads, and the third control chip connecting pad, respectively. Kim teaches the limitations of connecting bumps electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting pads, the plurality of second control chip connecting pads, and the third control chip connecting pad, respectively [0054]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Youn and Lee with the aforementioned limitations taught by Kim to control device spacing to manage heat dissipation (Kim [0003], [0005]).
In regards to claim 18, the combination of Youn and Lee teaches the limitations discussed above in addressing claim 17. Youn further teaches, e.g. figs. 1, 14A-18, the limitations further comprising:
first bonding wires (340a/340b) [0105] electrically connecting the chip enable pads of the plurality of memory chips to the plurality of memory chip connecting fingers (626/630) of the package substrate [0053];
first substrate interconnections (some instances of wiring connections in or on (310)) electrically connecting the plurality of memory chip connecting fingers to the plurality of first control chip connecting fingers [0103-0105];
second substrate interconnections (other instances of wiring connections in or on (310)) electrically connecting the plurality of second control chip connecting fingers to corresponding connecting lands, among the plurality of connecting lands [0103-0105];
a third substrate interconnection (yet other instances of wiring connections in or on (310)) electrically connecting the third control chip connecting finger to a corresponding connecting land, among the plurality of connecting lands [0103-0105].
The combination of Youn and Lee appears to be silent as to, but does not preclude, the limitations of second bonding wires electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting fingers, the plurality of second control chip connecting fingers, and the third control chip connecting finger, respectively. Kim teaches the limitations of second bonding wires electrically connecting the plurality of first chip enable signal control pads, the plurality of second chip enable signal control pads, and the third chip enable signal control pad to the plurality of first control chip connecting fingers, the plurality of second control chip connecting fingers, and the third control chip connecting finger, respectively [0054]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Youn and Lee with the aforementioned limitations taught by Kim to control device spacing to manage heat dissipation (Kim [0003], [0005]).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812