The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination
Allowable Subject Matter
Claim 7-8 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments, see pages 7-9, filed February 3, 2026, with respect to the rejection(s) of claim(s) 1, 11, and 18 under U.S.C. 102 have been fully considered and are not persuasive. Therefore, the rejection has been withdrawn maintained.
Applicant argue that the reference does not teach the switching from the first voltage rail to the second volage rail to maintain a context of the components, however that is not the case, the reference teaches the values of the register maintain an idle states of the components. While applicant may not like that, but that reads on the claim. Applicant only states on the claim maintaining a context of the components during power gating. Applicant would not to provide more information in the claim to differentiating the maintaining the context of the component to show that it is different from the reference. Anyway, to help with the prosecution of the application, examiner provides additional rejections below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
((a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srinivas (US Patent Application 2019026578).
As per claim 1, Srinivas teaches a device [device shown in figure 1] comprising:
a processing component [100, fig. 1] comprising a plurality of compute blocks [105, 107, fig. 1] and configured to operate at a first voltage rail [150, fig. 1] [0025, each subsystem CPUSS 105, GPUSS 107, and DSPSS 109 of SoC 100 is supplied power by a common voltage rail 150].
a control circuit [200, fig. 2] configured to, in response to power gating the processing component by power gating the first voltage rail to the processing component [0034, as pointed out the power manager is part of the switching circuit 200 that perform rail switching based on operating mode. For example, power management controller 240 is configured to control switches 230 for each portion 220 based on a current operating mode (e.g., active mode, retention mode, or power collapse mode) of associated computing cores to also operate the portion 220 in the current operating mode].
switch at least one of the plurality of compute blocks from the first voltage rail to a second voltage rail to maintain a context for the processing component with the at least one of the plurality of compute blocks [0027, 0039-0040, as pointed out response to a mode change of a core can switch from voltage rail and retain information to keep the values from lost. For example, In the retention mode, a computing core may be clock gated and the volatile memory associated with the computing core may be retained so as to keep the current values stored in the volatile memory without changing the values. In the power collapse mode, the volatile memory may be flushed (e.g., to a non-volatile storage). In retention/power collapse modes, a computing core may be powered by a different rail supplying a lower voltage (e.g., a retention voltage lower than VDD_MX and VDD_APC) (not shown), or not be powered. As well as, if CPUSS 105 is in nominal mode, APM controller 250 and MAS 260 are configured to switch switches 205 to couple power rail 210 to voltage rail 150. Further, if CPUSS 105 is in turbo mode, APM controller 250 and MAS 260 are configured to switch switches 205 to couple power rail 210 to voltage rail 141].
As per claim 11, Srinivas teaches, a system [100, fig. 1] comprising:
a first voltage rail [150, fig. 1].
a second voltage rail [141, fig. 1].
a processing component [105, fig. 1] comprising a plurality of compute blocks [110, 120, fig. 1] and configured to operate at the first voltage rail [150, fig. 1] 0025, each subsystem CPUSS 105, GPUSS 107, and DSPSS 109 of SoC 100 is supplied power by a common voltage rail 150].
a power gater [350, fig. 3] configured to couple the first voltage rail to the processing component [0051, 0046 as shown in figure 3, APM controller 350 is connected to rail 150 and control the switches that are connected to the rail. For example, the APM controller 350, plurality of MAS 360, MAS selector 365, re-sizer 367, and plurality of multiplexers 369 together may control the switching of switches 305].
a power multiplexer [369, fig. 3] coupled between the power gater and a compute block of the plurality of compute blocks and configured to switch the compute block between the first voltage rail and the second voltage rail [0058, the multiplexer is used to switch form one power rail to another power rail based on the signal selector. For example, any MAS 360 that receives the switching signal and is in the active state accordingly causes the switches 305 associated with the MAS 360 to switch and couple the corresponding power rail segment 310 of the corresponding portion 320 to either the voltage rail 141 or the voltage rail 150 based on the current active state of the CPUSS 105].
a control circuit [200, fig. 2] configured to, in response to power gating the processing component by power gating the first voltage rail to the processing component, switch the compute block from the first voltage rail to the second voltage rail using the power multiplexer to maintain a context for the processing component with the compute block [0027, 0039-0040, as pointed out response to a mode change of a core can switch from voltage rail and retain information to keep the values from lost. For example, In the retention mode, a computing core may be clock gated and the volatile memory associated with the computing core may be retained so as to keep the current values stored in the volatile memory without changing the values. In the power collapse mode, the volatile memory may be flushed (e.g., to a non-volatile storage). In retention/power collapse modes, a computing core may be powered by a different rail supplying a lower voltage (e.g., a retention voltage lower than VDD_MX and VDD_APC) (not shown), or not be powered. As well as, if CPUSS 105 is in nominal mode, APM controller 250 and MAS 260 are configured to switch switches 205 to couple power rail 210 to voltage rail 150. Further, if CPUSS 105 is in turbo mode, APM controller 250 and MAS 260 are configured to switch switches 205 to couple power rail 210 to voltage rail 141].
As per claim 3, Srinivas teaches the at least one of the plurality of compute blocks from the first voltage rail to the second voltage rail allows the at least one of the plurality of compute blocks to remain powered on while the processing component is power gated [0027, as pointed out during power gating, the computing core can be powered by a low power voltage rail as shown to keep power to it. For example, in retention/power collapse modes, a computing core may be powered by a different rail supplying a lower voltage (e.g., a retention voltage lower than VDD_MX and VDD_APC) (not shown), or not be powered].
As per claim 3, Srinivas teaches switching the at least one of the plurality of compute blocks from the first voltage rail to the second voltage rail allows the at least one of the plurality of compute blocks to remain powered on while the processing component is power gated [0027, as pointed out during power gating, the computing core can be powered by a low power voltage rail as shown to keep power to it. For example, in retention/power collapse modes, a computing core may be powered by a different rail supplying a lower voltage (e.g., a retention voltage lower than VDD_MX and VDD_APC) (not shown), or not be powered].
As per claim 4, Srinivas teaches power gating the processing component corresponds to entering a low power state [0035, as pointed out, if a memory, such as cache 130, is associated only with a given computing core and that computing core is put in a low power mode (e.g., retention mode or power collapse mode), each portion 220 of the memory may also be placed in the low power mode].
As per claim 5, Srinivas teaches at least one of the plurality of compute blocks corresponds to a microcontroller having one or more registers storing one or more values for a register context and power gating the processing component includes low power entry operations for the plurality of compute blocks [0002, 0031, as shown in figure 1, each CPU has cache or register. In this case, the cache is used to stored associated data with the CPU or core is put in low power mode].
As per claim 6, Srinivas least one of the plurality of compute blocks from the first voltage rail to the second voltage rail provides power to the microcontroller while the processing component is power gated such that the low power entry operations do not include a register context save operation for the microcontroller [0066, depending on the mode of operation, the memory always keep its value as pointed out].
As per claim 9, Srinivas teaches at least one of the plurality of compute blocks corresponds to a memory device [0021, memory used as subsystems or for the subsystems].
As per claim 10, Srinivas teaches the processing component corresponds to a graphics engine having the memory device [0023-0024, as shown in figure 1, the subsystems include GPU’s with memory].
As per claim 20, Srinivas teaches exiting the low power state for the processing component [0026-0027, active or nominal mode, CPU work on the first frequency].
in response to exiting the low power state, switching the compute block from the second voltage rail to the first voltage rail [0027, based on the power signal, the computing block can change voltage rail to accommodate different power modes].
As per claims 11-14 and 16-19, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 11-14 and 16-19 are also anticipated by Srinivas for the same reasons set forth in the rejected claims above.
To help with the prosecution of this application, additional rejection is given below for claim 1.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cao (US Patent Application 20170060224).
As per claim 1, Cao teaches a device [200, fig. 2] comprising:
a processing component [205, fig. 2] a plurality of compute blocks [215, 220, fig. 2] and configured to operate at a first voltage rail [Island MX Operational, fig. 2] [0015-0016, as pointed out the SOC include multiple subsystems that operate in different power rails. For example, for example one sub system can be coupled to one of the rails].
a control circuit [260, fig. 2] configured to, in response to power gating the processing component by power gating the first voltage rail to the processing component [0018, as pointed out, a power management integrated circuit (PMIC) 260 includes a switch-mode power supply 295 for powering sleep-mode MX power rail 270].
switch at least one of the plurality of compute blocks from the first voltage rail to maintain a context for the processing component with the at least one of the plurality of compute blocks [0016-0018, as pointed out if the system is in sleep mode, then the power manger simply switch the subsystem to the low power rail which provide the subsystem enough power to retain their states].
Claims 1-6, 9-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Subramaniam (US Patent Application 20090001814).
As per claim 1, Subramaniam teaches a device [device shown on, fig. 2] comprising:
a processing component [22, fig. 2] a plurality of compute blocks [24A to 24N, fig. 2] and configured to operate at a first voltage rail [0030-0032, as pointed out from the listed paragraphs and shown in figure 2, each logic circuit is connected to the power gating module via a rail that can activate specific logic circuit].
a control circuit [26, fig. 2] configured to, in response to power gating the processing component by power gating the first voltage rail to the processing component, switch at least one of the plurality of compute blocks from the first voltage rail to maintain a context for the processing component with the at least one of the plurality of compute blocks [0033, 0050, as pointed out form the listed paragraphs and shown in figure 2, response to a switch then specific logic circuit can be connected and disconnected to the power rail. As pointed out and shown in figure 5B, the register includes status bit that maintains a value to check if a logic circuit is in active mode or inactive mode. Circuit 26 in relationship with the switching is viewed as a multiplexing circuit that routes or connect each computing block to specific rail].
As per claim 2, Subramaniam teaches the control circuit corresponds to a power multiplexer coupled to the at least one of the plurality of compute blocks and configured to switch the at least one of the plurality of compute blocks between the first voltage rail and the second voltage rail [0031-0033, as pointed out circuit 26 include switches that connect to the logic circuit where, Power gating module 26 selectively couples and decouples logic circuits 24 to power source 28. Power gating module 26 may perform this coupling and decoupling on an independent basis for each of logic circuits 24A-24N. For example, power gating module 26 may couple and decouple logic circuit 24A to and from power source 28 independently of coupling].
As per claim 3, Subramaniam teaches switching the at least one of the plurality of compute blocks from the first voltage rail to the second voltage rail allows the at least one of the plurality of compute blocks to remain powered on while the processing component is power gated [0046, as pointed out and shown in figure 1, one of the block is always on or operate in always on domain: Profiles 50B and 52B illustrate power dissipation profiles for DMA-P 16A. In this example, DMA-P 16A operates at an active power level 46 at all times during frame time. Since DMA-P 16A always remains on, power is not gated to DMA-P 16A in this example].
As per claim 4, Subramaniam teaches power gating the processing component corresponds to entering a low power state [0049, fig. 5A, as pointed out assert a sleep signal to transition to sleep mode].
As per claim 5, Subramaniam teaches the at least one of the plurality of compute blocks corresponds to a microcontroller having one or more registers storing one or more values for a register context and power gating the processing component includes low power entry operations for the plurality of compute blocks [0041, fig. 1, shown one of the block may have a register that record status of the blocks].
As per claim 6, Subramaniam teaches switching the at least one of the plurality of compute blocks from the first voltage rail to the second voltage rail provides power to the microcontroller while the processing component is power gated such that the low power entry operations do not include a register context save operation for the microcontroller [0046, 0050, the block include one that is always one, which may not need status save register].
As per claim 9, Subramaniam teaches he at least one of the plurality of compute blocks corresponds to a memory device [0025, fig. 1, one of the block can be memory].
As per claim 10, Subramaniam teaches the processing component corresponds to a graphics engine having the memory device [0028, fig. 1, one of the block can be graphical processing circuit].
As per claims 11-14 and 16-20, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 11-14 and 16-20 are also anticipated by Subramaniam for the same reasons set forth in the rejected claims above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176