DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on 09/29/2025 with respect to claims 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 9-10, 12-13, 15-17 and 19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen (US Publication No. 20130258533).
Regarding claim 1, Chen discloses (see for example fig. 2, para. [0027]- [0060]) an integrated circuit (200) comprising: a first transistor (205) connected between a power supply terminal (VDD) and a reference terminal (GND), the first transistor (205) having a first control terminal (G1) at a gate (G1) of the first transistor (205); a second transistor (204) connected between the power supply terminal (VDD) and the first control terminal (G1), the second transistor (204) having a second control terminal (G2); a third transistor (214) connected between the first control terminal (G1) and the reference terminal (GND), the third transistor (214) having a third control terminal (G3); and an RC circuit (206, 208) including a resistor (206) and a capacitor (208) connected to the second control terminal (G2) and configured to turn on (i.e., circuit operations; see for example para. [0035]) the first transistor (205) responsive to a rise time (i.e., sub-circuit delays; see for example para. [0032]) of voltage of the power supply terminal (VDD) being less than a predetermined threshold (i.e., the threshold voltages; see for example para. [0030]).
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Regarding claim 2, Chen discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200); wherein the resistor (206) is connected to the power supply terminal (VDD) and the second control terminal (G2) and the capacitor (208) is connected between the second control terminal (G2) and the reference terminal (GND).
Regarding claim 4, Chen discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200); wherein the resistor (206) is a first resistor (206); and further comprising a fourth transistor (202) and a second resistor (i.e., 212; MN212 acting as a resistor due to dynamic resistor MP203; see para. [0033]), in which: the fourth transistor (202) is coupled between the power supply terminal (VDD) and the second resistor (212), the fourth transistor (202) having a fourth control terminal (G4) connected to the second control terminal (G2); and the second resistor (i.e., 212; MN212 acting as a resistor due to dynamic resistor MP203; see para. [0033]) is coupled between the fourth transistor (202) and the reference terminal (GND).
Regarding claim 9, Chen discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200); wherein the RC circuit (206, 208) is configured to produce a control voltage (i.e., controlling sub-circuit; see for example para. [0027]) indicative of an electrostatic discharge event (i.e., ESD event; see for example para. [0027]) at the power supply terminal (VDD).
Regarding claim 10, Chen discloses (see for example fig. 2, para. [0027]- [0060]) a method (200) comprising: forming a first transistor (205), a second transistor (204), a third transistor (214), a resistor (206), and a capacitor (208) over or extending into a semiconductor substrate (200), the first transistor (205) having a first control terminal (G1) at a gate (G1) of the first transistor (205), the second transistor (204) having a second control terminal (G2), and the third transistor (214) having a third control terminal (G3); and forming one (200) or more interconnect layers (200) and in the interconnect layers (200): connecting the first transistor (205) to a power supply terminal (VDD) and to a reference terminal (GND); connecting the second transistor (204) to the power supply terminal (VDD) and to the first control terminal (G1); connecting the third transistor (214) to the first control terminal (G1) and to the reference terminal (GND); connecting the resistor (206) between the power supply terminal (VDD) and the second control terminal (G2); and connecting capacitor (208) between the second control terminal (G2) and the reference terminal (GND).
Regarding claim 12, Chen discloses (see for example fig. 2, para. [0027]- [0060]), the method (200); wherein: the resistor (206) is a first resistor (206); and the method (200) includes: providing a second resistor (i.e., 212; MN212 acting as a resistor due to dynamic resistor MP203; see para. [0033]) over or extending into the semiconductor substrate (200); and in the interconnect layers (200): connecting the second resistor (i.e., 212; MN212 acting as a resistor due to dynamic resistor MP203; see para. [0033]) between the third control terminal (G3) and the reference terminal (GND).
Regarding claim 13, Chen discloses (see for example fig. 2, para. [0027]- [0060]), the method (200); further comprising: providing a fourth transistor (202) and a fifth transistor (215) over or extending into the semiconductor substrate (200), the fourth transistor (202) having a fourth control terminal (G4) and the fifth transistor (215) having a fifth control terminal (G5); and in the interconnect layers (200): connecting the fourth transistor (202) between the power supply terminal (VDD) and the third control terminal (G3); and connecting the fifth control terminal (G5) to the third control terminal (G3).
Regarding claim 15, Chen discloses (see for example fig. 2, para. [0027]- [0060]), the method (200); wherein the resistor (206) and the capacitor (208) are connected to form an RC circuit (206, 208) configured to produce a control voltage (i.e., controlling sub-circuit; see for example para. [0027]) indicative of an electrostatic discharge event (i.e., ESD event; see for example para. [0027]) at the power supply terminal (VDD).
Regarding claim 16, Chen discloses (see for example fig. 2, para. [0027]- [0060]), an integrated circuit (200) comprising: a core circuit (200) coupled between a power supply terminal (VDD) and a reference terminal (GND); an electro-static discharge (ESD) (i.e., ESD event; see for example para. [0027]) protection circuit (200) coupled between the power supply terminal (VDD) and the reference terminal (GND), the ESD protection circuit (200) including: an ESD protection transistor (205) connected between the power supply terminal (VDD) and the reference terminal (GND), the ESD protection transistor (205) having a control terminal (G1) at a gate (G1) of the ESD protection transistor (205); a first pull-down stage (pull-down stages; see for example para. [0027]) having a first transistor (213) and a first resistor (206) connected in series at a first node (220) between the power supply terminal (VDD) and the reference terminal (GND), the first node (220) connected to the control terminal (G1) of the ESD protection transistor (205); and a second pull-down stage (pull-down stages; see for example para. [0027]) having a second transistor (202) and a second resistor (i.e., 212; MN212 acting as a resistor due to dynamic resistor MP203; see para. [0033]) connected in series at a second node (225) between the power supply terminal (VDD) and the reference terminal (GND), the second node (225) connected to the control terminal (G1) of the ESD protection transistor (205).
Regarding claim 17, Chen discloses (see for example fig. 2, para. [0027]- [0060]), the integrated circuit (200); wherein the ESD protection circuit (200) includes a capacitor (208) coupled between the first resistor (206) and the reference terminal (GND).
Regarding claim 19, Chen discloses (see for example fig. 2, para. [0027]- [0060]), the integrated circuit (200); wherein: the first pull-down stage (pull-down stages; see for example para. [0027]) includes a third transistor (215) having a third control terminal (G5), in which: the third transistor (215) is connected between the reference terminal (GND) and the control terminal (G1) of the ESD protection transistor (205); and a control terminal (G5) of the third transistor (215) is connected to the second node (225); and the second pull-down stage (pull-down stages; see for example para. [0027]) includes a fourth transistor (214) having a fourth control terminal (G3), in which: the fourth transistor (214) is connected between the reference terminal (GND) and the second node (225).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Publication No. 20130258533) in view of Gee et al (US Patent No. 8199447).
Regarding claims 3, 11 and 18, Chen discloses (see for example fig. 2, para. [0027]- [0060]) an (ESD) integrated circuit (200).
Chen does not explicitly disclose the capacitor includes a reverse-biased Zener diode nor the capacitor is implemented by a Zener diode nor a Zener diode coupled between the first resistor and the reference terminal.
Gee discloses a semiconductor device that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode (see figure 3, Col. 4 line 12- Col. 5 line 41), wherein the capacitor (380) includes a reverse-biased Zener diode (38), and the ESD protection circuit includes a Zener diode (36, 37, 38, 39) coupled between the first resistor (54) and the reference terminal (301, see figure 5, Col. 5 line 56- Col. 6 line 13).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the internal and/or external capacitances that are implemented as Zener diodes in Chen, as taught by Gee, as it provides the advantage of substantially shunting noises in the circuit(s).
Claims 5-7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Publication No. 20130258533) in view of Fehle et al (US Patent No. 8059375).
Regarding claim 5, Chen discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200); further comprising: a fifth transistor (215), the fifth transistor (215) including a fifth control terminal (G5) coupled to the second control terminal (G2), in which: the fifth transistor (215) is coupled between the power supply terminal (VDD); and is coupled between the fifth transistor (215) and the reference terminal (GND).
Chen does not explicitly disclose a third resistor nor the third resistor is coupled between the fifth transistor and the reference terminal.
Fehle discloses a circuit arrangement and method for the protection of a circuit against electrostatic discharges (see figure 2, Col. 6 line 40- Col. 8 line 56), wherein the third resistor (R6) is coupled between the fifth transistor (18) and the reference terminal (2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the resistor in Chen, as taught by Fehle, as it provides the advantage of protecting the transistor from excessive current.
Regarding claim 6, Chen in view of Fehle, and the teachings of Chen as modified by Fehle have been discussed above.
Chen further discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200); further comprising a sixth transistor (213) coupled between the fifth transistor (215) and the reference terminal (GND), the sixth transistor (213) having a sixth control terminal (G6) coupled to the second resistor (i.e., 212; MN212 acting as a resistor due to dynamic resistor MP203; see para. [0033]).
Regarding claim 7, Chen in view of Fehle, and the teachings of Chen as modified by Fehle have been discussed above.
Chen further discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200).
Fehle furthermore discloses (see figure 2, Col. 6 line 40- Col. 8 line 56); wherein the third control terminal (20) is coupled to the fifth transistor (18) and the third resistor (R6).
Regarding claim 14, Chen in view of Fehle, and the teachings of Chen as modified by Fehle have been discussed above.
Chen further discloses (see for example fig. 2, para. [0027]- [0060]) the method (200); further comprising: providing a sixth transistor (213) over or extending into the semiconductor substrate (200), the sixth transistor (213) having a sixth control terminal (G6); and providing over or extending into the semiconductor substrate (200); and in the interconnect layers (200): connecting the sixth transistor (213) between the power supply terminal (VDD) and the fifth control terminal (G5); and connecting the second resistor (i.e., 212; MN212 acting as a resistor due to dynamic resistor MP203; see para. [0033]) between the fifth control terminal (G5) and the reference terminal (GND).
Fehle furthermore discloses (see figure 2, Col. 6 line 40- Col. 8 line 56); and providing a third resistor (R6) over or extending into the semiconductor substrate (3).
Regarding claim 20, Chen in view of Fehle, and the teachings of Chen as modified by Fehle have been discussed above.
Chen further discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200); wherein the ESD protection circuit (200) includes: a third pull-down stage (pull-down stages; see for example para. [0027]) including a fifth transistor (204) and connected in series at a third node (230) between the power supply terminal (VDD) and the reference terminal (GND), the third node (230) connected to a control terminal (G3) of the fourth transistor (214).
Fehle furthermore discloses (see figure 2, Col. 6 line 40- Col. 8 line 56); and a third resistor (R6) connected in series at a third node (20) between the power supply terminal (1) and the reference terminal (2).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US Publication No. 20130258533) in view of Tseng (US Publication No. 20070183104).
Regarding claim 8, Chen discloses (see for example fig. 2, para. [0027]- [0060]) the integrated circuit (200); wherein the first transistor (205) is an n-type extended-drain field effect transistor (FET) (i.e., NMOS), and the second (204) is a p-type FET (i.e., PMOS).
Chen does not explicitly disclose the third transistor is a p-type FET.
Tseng discloses (see for example fig. 6, para. [0035]); an ESD protection device comprising a first switch, a second switch, a discharge unit, and a detection unit; wherein the third transistor (55) is a p-type FET (i.e., PMOS).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the PMOS device in Chen, as taught by Tseng, as it provides the advantage of optimizing the circuit design towards minimizing the power loss in low-power/battery-operated circuits.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838