DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Applicant’s Amendments and Remarks file don 12/2/2025. Claims 1, 3, 7, 11, 13, and 20 have been amended. Claims 1-20 are present for examination.
The objections to the drawings have been withdrawn in view of the amendments.
The objections to the specification have been withdrawn in view of the amendments.
The previous objections to claims 1, 3, 4, 7, 11, 13, and 20 have been withdrawn in view of the amendments. However, claim 14 still has issues and is objected again. Claims 1, 1, and 20 are objected in view of the amendments. Details could be found in the following relevant sections.
Response to Arguments
Applicant's arguments filed 12/2/2025 with respect to the 35 USC 101 rejections of claims 2, 6, 12, and 16 have been fully considered but they are not persuasive.
Applicant submits: Claim 2 includes all of the features that are recited in claim 1, and merely specifies the case wherein M is a specific value of four and the texture processing operation is a bilinear filtering operation (which uses the four texture data elements). It is therefore clear that claim 2 relates to a straightforward narrowing of scope compared to claim 1 (and does not, e.g. alter the technical nature of the claim, or introduce any abstract concept). … Since claim 2 … necessarily includes all limitations of its (non-abstract) independent claims and merely specifies a particular numeric value, it is clear that it remains directed to patent-eligible subject matter, not an abstract idea. (See Remarks filed on 12/2/2025, p. 11, paras. 4-6.)
The examiner respectfully disagrees. Merely because claim 2 depends from an eligible claim does not automatically render claim 2 to be eligible. The examiner follows MPEP provisions in rejecting claim 2 under 35 USC 101.
MPEP 2106.04 II.A provides: “Step 2A is a two-prong inquiry, in which examiners determine in Prong One whether a claim recites a judicial exception, and if so, then determine in Prong Two if the recited judicial exception is integrated into a practical application of that exception. Together, these prongs represent the first part of the Alice/Mayo test, which determines whether a claim is directed to a judicial exception.”
Original Claim 1 does not recites abstract ideas, therefore it is not subject to 35 USC 101 rejection. However, as Applicant points out, claim 2 depends from claim 1, and further specifies the case wherein M is a specific value of four and the texture processing operation is a bilinear filtering operation (which uses the four texture data elements).
In fact, claim 2 recites “wherein M = 4 and the texture processing operation is a bilinear filtering operation”. “M=4” is mathematical concept and “bilinear filtering operation” is a mathematical algorithm. Therefore, according to the flowchart provided in MPEP 2106 (reproduced below), the answer to Prong One in Revised Step 2A is “YES” because the claim 2 recites abstract idea of mathematical concept. Accordingly, the answer “YES” prompts analysis for Prong Two: “Does The Claim Recite Additional Elements That Integrate The Judicial Exception Into A Practical Application?” and Step 2B. Because Applicant does not provide arguments with respect to the examiner’s analysis regarding Prong Two and Step 2B, the examiner maintains the 35 USC 101 rejections of claims 2, 6, 12, and 16.
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Applicant’s arguments with respect to claim(s) 1 with respect 35 USC 102 rejection in view of US Patent Publication No. 20200143580 A1 to Seiler have been fully considered but they are not persuasive.
Applicant submits: “Seiler therefore does not disclose, e.g., an array of texture data element wherein ‘each of the texture data elements of the array of texture data elements belongs to one of M sets of texture data elements, each of the M sets of texture of texture data elements having a respective set of positions in the array of texture data elements’ such that the method comprises ‘providing M texture data elements as inputs for a texture processing operation from the array of texture data elements, each of the M texture data elements being selected from the texture data elements of a respective different set of texture data elements of the M sets of texture data elements by a respective multiplexer tree, each multiplexer tree taking as its inputs all of the respective texture data elements belonging to a respective set of texture data elements’, as required by the independent claims.” (See Remarks filed on 12/2/2025, p. 14, 3rd para., emphasis original.)
The examiner respectfully disagrees. Seiler discloses an array of texture data element wherein ‘each of the texture data elements of the array of texture data elements belongs to one of M sets of texture data elements (Seiler, FIG. 11B, showing Quad Buffer Block A 1102, having M (M=4) sets of texture data elements corresponding to texel buffer blocks 1121, 1122, 1123, and 1124), each of the M sets of texture of texture data elements having a respective set of positions in the array of texture data elements’ (Seiler, FIG. 11B, showing each set of texture data elements having a respective set of positions in the quad buffer block A 1102 as the array of texture data elements) such that the method comprises ‘providing M texture data elements as inputs for a texture processing operation from the array of texture data elements (Seiler, FIG. 11B, showing Texture Buffer Block (0,0) 1121 having M (M=4) texture data elements as inputs for a texture processing operation from the Quad Buffer Block A 1102), each of the M texture data elements being selected from the texture data elements of a respective different set of texture data elements of the M sets of texture data elements by a respective multiplexer tree, each multiplexer tree taking as its inputs all of the respective texture data elements belonging to a respective set of texture data elements’ (Seiler, FIG. 11B, showing Mux 1125A, Mux 1225B, Mux 1125C, Mux 1125D, Mux 1125E, Mux 1125F, Mux 1225G, and Mux 1125H, as multiplexer trees, each multiplexer tree can select one texture data elements of a respective different set of texture data elements of the M sets of texture data elements, each taking as its inputs all of the respective texture data elements belonging to a respective set of texture data elements (each taking its inputs all of the respective texture data elements belonging to a respective set of texture data elements 1121, 1122, 1123, and 1124).
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Applicant further submits: “Seiler describes a very different type of method to that of the present invention, which requires storing (and selecting) texels at different memory levels. Given that the multi-level memory arrangement is fundamental to the teaching of Seiler, there is certainly nothing in Seiler could or would prompt the skilled person to make the extensive modifications to the system of Seiler that would be necessary to arrive at the present invention.” (See Remarks filed on 12/2/2025, p. 14, 4th para.)
The examiner respectfully disagrees. As discussed above, Seiler teaches the limitations of claim 1. Even if Seiler teaches a multi-level memory arrangement, claim 1 does not distinguish the memory arrangement different than Seiler. In fact, claim 1 does not mention that the memory arrangement for the current invention cannot be multi-level. Because Seiler teaches the limitations of claim 1, its memory arrangement is irrelevant and thus Applicant’s arguments is not persuasive.
Claim Objections
Claims 1, 11, and 20 are objected to because of the following informalities: “the M sets of texture of texture data elements” should be “the M sets of texture data elements”.
Claim 14 is objected to because of the following informalities: “the texture data array” in line 4 should be “the array of texture data elements”.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 2, 6, 12, and 16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Regarding claim 2, it depends from claim 1 with additional limitation “wherein M=4 and the texture processing operation is a bilinear filtering operation.”
MPEP 2106 III provides a flowchart for the subject matter eligibility test for product and processes. The claim analysis following the flowchart is as follows:
Step 1: Is the claim to a process, machine, manufacture or composition of matter?
Yes. It recites a method, which is a process.
Step 2A, Prong One: Does the claim recite an abstract idea, law of nature, or nature phenomenon?
Yes.
Limitations “wherein M=4 and the texture processing operation is a bilinear filtering operation” are mathematical concepts being expressly recited in the claim.
Step 2A, Prong Two: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Claim 1 recites a graphics processor, texture data array, and providing texture data elements as inputs for a texture processing operation. Graphics processor is a common component in a generic computer, providing texture data elements as inputs for a texture processing operation is mere data gathering and thus insignificant extra solution. The texture processing operation is further limited in claim 2 as bilinear filtering operation, which is mathematical calculation.
Therefore, this judicial exception is not integrated into a practical application because generic computer components and insignificant extra solution cannot integrate an abstract idea into a practical application.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above, the additional elements recited in claim 1 and 2 are generic computer components and insignificant extra solution, which are NOT sufficient to amount to significantly more than the judicial exception.
Claim 12 recites similar limitations discussed above with respect to claim 2, and another additional limitation recited in claim 11 is “texture processing circuit”. However, the “texture processing circuit” is recited in such a high level without enough details to make it a special machine other than generic computer component.
Therefore, the additional elements recited in claim 11 and 12 are generic computer components and insignificant extra solution, which are NOT sufficient to amount to significantly more than the judicial exception.
Regarding claim 6, it depends from claim 1 with additional limitation “wherein the texture processing operation comprises multiplying the M texture data elements with respective weights, and the method further comprises: prior to performing the texture processing operation using the M texture data elements, reordering the weights based on the order of the M selected texture data elements.”
MPEP 2106 III provides a flowchart for the subject matter eligibility test for product and processes. The claim analysis following the flowchart is as follows:
Step 1: Is the claim to a process, machine, manufacture or composition of matter?
Yes. It recites a method, which is a process.
Step 2A, Prong One: Does the claim recite an abstract idea, law of nature, or nature phenomenon?
Yes.
Limitations “multiplying the M texture data elements with respective weights” is mathematical calculations and “prior to performing the texture processing operation using the M texture data elements, reordering the weights based on the order of the M selected texture data elements” is mathematical relationship (organizing information through mathematical correlations) being expressly recited in the claim.
Step 2A, Prong Two: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Claim 1 recites a graphics processor, texture data array, and providing texture data elements as inputs for a texture processing operation. Graphics processor is a common component in a generic computer, providing texture data elements as inputs for a texture processing operation is mere data gathering and thus insignificant extra solution. The texture processing operation is further limited in claim 2 as bilinear filtering operation, which is mathematical calculation.
Therefore, this judicial exception is not integrated into a practical application because generic computer components and insignificant extra solution cannot integrate an abstract idea into a practical application.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above, the additional elements recited in claim 1 and 6 are generic computer components and insignificant extra solution, which are NOT sufficient to amount to significantly more than the judicial exception.
Claim 16 recites similar limitations discussed above with respect to claim 6, and another additional limitation recited in claim 11 is “texture processing circuit”. However, the “texture processing circuit” is recited in such a high level without enough details to make it a special machine other than generic computer component.
Therefore, the additional elements recited in claim 11 and 16 are generic computer components and insignificant extra solution, which are NOT sufficient to amount to significantly more than the judicial exception.
Therefore, claims 2, 6, 12, and 16 are not eligible subject matter under 35 USC 101.
Note, the limitation “performing the texture processing operation using the M texture data elements” recited in the independent claims has NOT been interpreted as an abstract idea, and only claims 2, 6, 12, and 16 further limit the texture processing operation to expressly recite mathematical concept.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 11-14, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Publication No. 20200143580 A1 to Seiler.
Regarding claim 1, Seiler discloses a method of operating a graphics processor in which texture data elements are selected for performing texture processing operations, the texture data elements being arranged in an array of texture data elements, the texture data elements of the array of texture data elements having a respective position in the array of texture data elements (Seiler, para. [0106], disclosing a display engine including a control/controller block, transform blocks, pixel blocks, display blocks, para. [0112], disclosing the controller block may include a microcontroller, a texel memory, a memory controller, etc., para. [0113], disclosing the texel memory stores texels in 4x4 texel blocks, and the texels are needed for determining color components of every pixel associated with a tile, para. [0097], disclosing FIG. 8A showing an example of 4x4 texel array stored in a 32 bytes memory block with an interleaved pattern, the system may store a 2D texel array in a memory block with an interleaved swizzle pattern, FIG. 8A, showing the texels as texture data elements being arranged in an array of texture data elements having respective position in the texture data array, FIG. 8B, showing a 2x2 texel array 825, each of its 4 texels are in different positions in the 8x8 texel array 820 and at different quad buffer blocks A, B, C, D respectively, FIG. 8C, showing different texel buffer blocks storing different texels for different 2x2 texel arrays), wherein each of the texture data elements of the array of texture data elements belongs to one of M sets of texture data elements (Seiler, FIG. 11B, showing Quad Buffer Block A 1102, having M (M=4) sets of texture data elements corresponding to texel buffer blocks 1121, 1122, 1123, and 1124), each of the M sets of texture of texture data elements having a respective set of position in the array of texture data elements (Seiler, FIG. 11B, showing each set of texture data elements having a respective set of positions in the quad buffer block A 1102 as the array of texture data elements), wherein M is a positive integer (Seiler, FIG. 11B, showing four sets of texture data elements, indicating M=4, which is a positive integer), the method comprising:
providing M texture data elements as inputs for a texture processing operation from the array of texture data elements (Seiler, FIG. 11B, showing Texture Buffer Block (0,0) 1121 having M (M=4) texture data elements as inputs for a texture processing operation from the Quad Buffer Block A 1102, para. [0101], disclosing a quad buffer block include four texel buffer blocks, the texels stored in each quad buffer block may conceptually form a 4x4 texel array including four 2x2 texel arrays, each texel buffer block of a quad buffer block may include texels having same local (U,V) coordinates, FIG. 11B, showing the texel buffer blocks each having 4 (M) texels (texture data elements), each of the 4 texels being selected from a different set of texels having a different set of positions within the texture data array (e.g., texel buffer 1121 has 4 texels A1, A3, A9, and A11, when looking in FIGs. 8A-8B, each of A1, A3, A9, and A11 is from a different 2x2 texel array of the 8x8 texel array, and has a different set of positions within the texture data array, FIGs. 11A-11B, showing the texels in the texel buffer blocks are sent to sample filter blocks, para. [0125], disclosing the multiplexors may allow sample filter blocks to select texel buffer block to access so that I can bilinearly interpolate each sample in the corresponding texel region, indicating the operations performed by the multiplexors can correspond to a texture processing operation), each of the M texture data elements being selected from the texture data elements of a respective different set of texture data elements of the M sets of texture data elements by a respective multiplexer tree, each multiplexer tree taking as its inputs all of the respective texture data elements belonging to a respective set of texture data elements (Seiler, FIG. 11B, showing Mux 1125A, Mux 1225B, Mux 1125C, Mux 1125D, Mux 1125E, Mux 1125F, Mux 1225G, and Mux 1125H, as multiplexer trees, each multiplexer tree can select one texture data elements of a respective different set of texture data elements of the M sets of texture data elements, each taking as its inputs all of the respective texture data elements belonging to a respective set of texture data elements (each taking its inputs all of the respective texture data elements belonging to a respective set of texture data elements 1121, 1122, 1123, and 1124); and
performing the texture processing operation using the M texture data elements (Seiler, para. [0101], disclosing a quad buffer block include four texel buffer blocks, the texels stored in each quad buffer block may conceptually form a 4x4 texel array including four 2x2 texel arrays, each texel buffer block of a quad buffer block may include texels having same local (U,V) coordinates, FIG. 11B, showing the texel buffer blocks each having 4 (M) texels (texture data elements), each of the 4 texels being selected from a different set of texels having a different set of positions within the texture data array, FIGs. 11A-11B, showing the texels in the texel buffer blocks are sent to sample filter blocks, para. [0125], disclosing the multiplexors may allow sample filter blocks to select texel buffer block to access so that I can bilinearly interpolate each sample in the corresponding texel region, indicating the operations performed by the multiplexors can correspond to a texture processing operation performed using the texels as texture data elements in a selected texel buffer block).
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Regarding claim 2, Seiler discloses the method of claim 1, wherein M = 4 and the texture processing operation is a bilinear filtering operation (Seiler, para. [0101], disclosing a quad buffer block include four texel buffer blocks, the texels stored in each quad buffer block may conceptually form a 4x4 texel array including four 2x2 texel arrays, each texel buffer block of a quad buffer block may include texels having same local (U,V) coordinates, FIG. 11B, showing the texel buffer blocks each having 4 (M) texels (texture data elements), each of the 4 texels being selected from a different set of texels having a different set of positions within the texture data array, FIGs. 11A-11B, showing the texels in the texel buffer blocks are sent to sample filter blocks, para. [0125], disclosing the multiplexors may allow sample filter blocks to select texel buffer block to access so that I can bilinearly interpolate each sample in the corresponding texel region, indicating the operations performed by the multiplexors can correspond to a texture processing operation performed using the texels as texture data elements in a selected texel buffer block).
Regarding claim 3, Seiler discloses the method of claim 1, comprising providing M texture data elements as inputs for a texture processing operation for each of T threads in parallel, wherein T is a positive integer, to thereby provide M*T texture data elements for T different texture processing operations (Seiler, para. [0101], disclosing a quad buffer block include four texel buffer blocks, the texels stored in each quad buffer block may conceptually form a 4x4 texel array including four 2x2 texel arrays, each texel buffer block of a quad buffer block may include texels having same local (U,V) coordinates, FIG. 11B, showing the texel buffer blocks each having 4 (M) texels (texture data elements), each of the 4 texels being selected from a different set of texels having a different set of positions within the texture data array, FIGs. 11A-11B, showing the texels in the texel buffer blocks are sent to sample filter blocks, para. [0114], disclosing using multiple sample filter blocks to parallelly perform interpolation on different groups of texels, para. [0120], disclosing four groups of texels for four sampling positions may be sampled in parallel in the sample filter blocks respectively, para. [0125], disclosing the multiplexors may allow sample filter blocks to select texel buffer block to access so that I can bilinearly interpolate each sample in the corresponding texel region, para. [0133], disclosing the system may parallelly retrieve the 4x4 texel array from the texel memory using one read-out operation, indicating 4 sample groups can correspond to T=4 threads for texture processing operations, each sample group having M=4 texels, therefore providing 4(T)x4(M) texels (texture data elements) for T=4 different texture processing operations); and performing the T different texture processing operations using the M*T texture data elements (Seiler, para. [0120], disclosing four groups of texels for four sampling positions may be sampled in parallel in the sample filter blocks respectively, FIGs. 11A-B, showing 4 sampling filter blocks for 4 sampling operations, para. [0133]-[0134], disclosing parallelly retrieving the 4x4 texel array from texel memory and performing the bilinear interpolation for the sample points by four sample filter blocks); wherein the texture data elements of each different set of texture data elements having a different set of positions within the array of texture data elements are connected to N read ports in a texture data cache, wherein N is a positive integer (Seiler, para. [0103], disclosing FIGS. 8F-G illustrate an example 2×2 texel array which is selected from an 8×8 texel array stored in 16 independent texel buffer blocks and can be read from the texel buffer with reduced multiplexing operations, the four texels in the 2×2 texel array 827 may be determined as the texels needed for determining a pixel value and may be selected from the 4×4 texel array 826, the 2×2 texel array 827 may include D5, C6, B9, and A10 as marked by the shaded square. Since the texels are stored in the quad buffer blocks and texel buffer blocks in a pattern as descripted above, the four texels of D5, C6, B9, and A10 are stored in four quad buffer blocks of 1102, 1103, 1104, and 1105, respectively, para. [0104], disclosing FIG. 8G shows that the four texels D5, C6, B9, and A10 are stored in four texel buffer blocks of 1123D, 1124C, 1121B, and 1122A, respectively, any 2×2 texel array selected from the 4×4 texel array 826 may have its 4 texels being stored in four separate quad buffer blocks and four separate texel buffer blocks, para. [0105], disclosing the four 2×2 texel array may be extracted parallelly from the 4×4 texel array which may be accessed and retrieved parallelly (e.g., using one read operation) from the quad buffer blocks and texel buffer blocks, indicating each texel buffer block will have one read port, and each quad buffer block having 4 texel buffer blocks will have 4 read ports (M=4 texels connected to N=4 read ports in a quad buffer block in a texture data cache), and the method thereby comprises selecting M*T texture data elements from M*N read ports in the texture data cache (Seiler, para. [0103], disclosing FIGS. 8F-G illustrate an example 2×2 texel array which is selected from an 8×8 texel array stored in 16 independent texel buffer blocks and can be read from the texel buffer with reduced multiplexing operations, the four texels in the 2×2 texel array 827 may be determined as the texels needed for determining a pixel value and may be selected from the 4×4 texel array 826, the 2×2 texel array 827 may include D5, C6, B9, and A10 as marked by the shaded square. Since the texels are stored in the quad buffer blocks and texel buffer blocks in a pattern as descripted above, the four texels of D5, C6, B9, and A10 are stored in four quad buffer blocks of 1102, 1103, 1104, and 1105, respectively, para. [0104], disclosing FIG. 8G shows that the four texels D5, C6, B9, and A10 are stored in four texel buffer blocks of 1123D, 1124C, 1121B, and 1122A, respectively, any 2×2 texel array selected from the 4×4 texel array 826 may have its 4 texels being stored in four separate quad buffer blocks and four separate texel buffer blocks, para. [0105], disclosing the four 2×2 texel array may be extracted parallelly from the 4×4 texel array which may be accessed and retrieved parallelly (e.g., using one read operation) from the quad buffer blocks and texel buffer blocks, FIG. 11A, showing each quad buffer block as 4 outputs to be read from sample filter blocks, indicating each texel buffer block will have one read port, and each quad buffer block having 4 texel buffer blocks will have 4 read ports (M=4 texels connected to N=4 read ports in a quad buffer block in a texture data cache, and retrieving the 4x4 texels for the T=4 sample points in parallel will correspond to selecting M(=4)*T(=4) texture data elements from M(=4)*N(=4) read ports in the texture data cache).
Regarding claim 4, Seiler discloses the method of claim 1, wherein the array of texture data elements comprises a regular arrangement of groups of M texture data elements (Seiler, FIG. 8B, showing a 8x8 texel array 820 with regular arrangement of groups of M texture data elements (such as 2x2 texel array 825)), each group of M texture data elements having one texture data element from each respective one of the M sets of positions in the texture data array (Seiler, FIG. 8B, showing a 8x8 texel array 820 with regular arrangement of groups of M texture data elements (such as 2x2 texel array 825), each group of M(=4) texels (texture data elements) having one texel from each respective one of the M(=4) sets of positions in the texture data array)), optionally wherein each group of texture data elements comprises a 2x2 quad of texture data elements (Seiler, FIG. 8B, showing 2x2 texel array 825. Note, the term “optionally” has been interpreted as this limitation is not required).
Regarding claim 7, Seiler discloses the method of claim 1, wherein the step of providing M texture data elements as inputs for a texture processing operation from the array of texture data elements comprises: first selecting a plurality of adjacent texture data elements all having a particular position in the first set of positions within the texture data array (Seiler, FIG. 8F, 2x2 texel array 827 was selected that contains a plurality of adjacent texture data elements (4 texels) all having a particular position in the first set of positions within the texture data array of the 8x8 texel array 820 and/or 4x4 texel array 826; also, texel A10 is among the quad buffer block A, where the quad buffer block A has a plurality of adjacent texels (texture data elements) all having a particular position in the first set of positions within the texture data array (0,0)); and then selecting a texture data element having a particular sub-position within the plurality of adjacent texture data elements from the plurality of adjacent texture data elements (Seiler, FIG. 8F, 2x2 texel array 827 was selected that contains a plurality of adjacent texture data elements (4 texels) all having a particular position in the first set of positions within the texture data array of the 8x8 texel array 820 and/or 4x4 texel array 826, each texel in 2x2 texel array 827 is selected having a particular sub-position within 827; also, texel A10 is among the quad buffer block A, where the quad buffer block A has a plurality of adjacent texels (texture data elements) all having a particular position in the first set of positions within the texture data array (0,0), and texel A10 is selected from the quad buffer block A, where A10 has a particular sub-position within the quad buffer block A’s plurality of adjacent texture data elements).
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Regarding claim 11, it recites similar limitations of claim 1 but in a graphics processor form. The rationale of claim 1 rejection is applied to reject claim 11. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Regarding claim 12, it recites similar limitations of claim 2 but in a graphics processor form. The rationale of claim 2 rejection is applied to reject claim 12. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Regarding claim 13, it recites similar limitations of claim 3 but in a graphics processor form. The rationale of claim 3 rejection is applied to reject claim 13. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Regarding claim 14, it recites similar limitations of claim 4 but in a graphics processor form. The rationale of claim 4 rejection is applied to reject claim 14. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Regarding claim 17, it recites similar limitations of claim 7 but in a graphics processor form. The rationale of claim 7 rejection is applied to reject claim 17. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Regarding claim 20, it recites similar limitations of claim 1 but in a non-transitory computer readable storage medium form. The rationale of claim 1 rejection is applied to reject claim 20. In addition, Seiler discloses non-transitory computer readable storage medium (see Seiler, paras. [0025], [0033]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seiler in view of US Patent No. 7,167,183 B1 to Donovan et al.
Regarding claim 5, Seiler discloses the method of claim 1. However, Seiler does not expressly disclose prior to performing the texture processing operation using the M texture data elements, reordering the M texture data elements.
On the other hand, Donovan discloses prior to performing the texture processing operation using the M texture data elements, reordering the M texture data elements (col. 6, lines 54-64, disclosing reorganizing the read order of the texels based on their corresponding texture samples, such as texels for texture samples 310, 311, 312, 313, 314, 315, 316, 317 may be read in the following order: 310, 312, 311, 313, then 314, 316, 315, 317, col. 11, lines 43-47, disclosing recording the texels for texture samples as needed prior to processing them and outputting the filtered results to a shader unit).
Before the effective filing date of the claimed invention, it would have been obvious for a person skilled in the art to modify Seiler with Donovan. The suggestion/motivation would have been to significantly reduce the number of cache lines that are accessed, as suggested by Donovan (see Donovan, col. 7, lines 14-15).
Regarding claim 15, it recites similar limitations of claim 5 but in a graphics processor form. The rationale of claim 5 rejection is applied to reject claim 15. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seiler in view of US Patent Publication No. 20040085325 A1 to Wang et al.
Regarding claim 6, Seiler discloses the method claim 1, wherein the texture processing operation comprises multiplying the M texture data elements with respective weights (Seiler, para. [0122], disclosing providing filter weights to the sample filter blocks, para. [0128], disclosing the interpolator may receive from filter cache the texel data, and perform bilinear interpolation with 5x5 multipliers using weights provided by the sample stepper). However Seiler does not expressly disclose prior to performing the texture processing operation using the M texture data elements, reordering the weights based on the order of the M selected texture data elements.
On the other hand, Wang discloses prior to performing the texture processing operation using the M texture data elements, reordering the weights based on the order of the M selected texture data elements (Wang, para. [0015], disclosing a combined input texture matrix is generated, and the individual input texture matrices are staked in a prescribed order, a combined weight matrix is also generated by stacking the individual weight matrices in the same order as the input texture are stacked, then the systems of equations are defined based on the combined input texture matrix and the combined weight matrix, which will be solved to recover the actual texture, indicating stacking the individual weight matrices in the same order as the input texture are stacked can correspond to reordering the weights based on the order of the M selected texture data elements prior to recovering the actual texture as performing the texture processing operation).
Before the effective filing date of the claimed invention, it would have been obvious for a person skilled in the art to combine Seiler and Wang. The suggestion/motivation would have been to for reconstructing optimal texture maps from multiple views of a scene that can be incorporated with great advantage in the aforementioned texturing of 3D models, analysis by synthesis methods, super-resolution techniques, and view-dependent texture mapping, as suggested by Wang (see Wang, para. [0010]).
Regarding claim 16, it recites similar limitations of claim 6 but in a graphics processor form. The rationale of claim 6 rejection is applied to reject claim 16. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seiler in view of US Patent Publication No. 20150121052 A1 to Emma et al.
Regarding claim 8, Seiler discloses the method of claim 7. However, Seiler does not expressly disclose wherein the step of selecting a texture data element having a particular sub-position within the plurality of adjacent texture data elements from the plurality of adjacent texture data elements comprises bit shifting a data string containing the plurality of adjacent texture data elements in order to select the texture data element having a particular sub-position within the plurality of adjacent texture data elements.
On the other hand, Emma discloses bit shifting a data string containing the plurality of adjacent data elements in order to select the data element having a particular sub-position within the plurality of adjacent data elements (Emma, para. [0170], disclosing the data of the data array structure can be read out from the memory by shifting the bits to the left a certain number of positions to place the bits in proper order, such when the second row of the data array structure is read out, the data elements on bit lines BL0, BL1, BL2 and BL3 will be in the order of A24, A21, A22, and A23, and a right shift operation of 1 bit position will be applied to place the data elements in proper order, i.e., A21, A22, A23, and A24). Because Seiler discloses reading texel array data from memory, combining Seiler and Emma will allow the user of bit shifting the data string of texels (texture data elements) to select the texel having a particular sub-position within the plurality of adjacent texels, e.g., A21 from A24, A21, A22, and A23.
Before the effective filing date of the claimed invention, it would have been obvious for a person skilled in the art to combine Seiler with Emma. The suggestion/motivation would have been to place the read-out data elements from the memory in proper order, as suggested by Emma (see Emma, para. [0170]).
Regarding claim 18, it recites similar limitations of claim 8 but in a graphics processor form. The rationale of claim 8 rejection is applied to reject claim 18. In addition, Seiler discloses a graphics processor comprising a texture data element providing circuit and a texture processing circuit (Seiler, FIG. 9, showing a display engine including controller block with texel memory, memory controller, transform block, pixel block, and display block, FIG. 10, showing pixel block including filter block, FIG. 11A, showing filter block).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seiler in view of US Patent Publication No. 20210398241 A1 to Fetterman et al.
Regarding claim 10, Seiler discloses the method of claim 1, wherein a texture data element is provided as an input for the texture processing operation from texture data elements having a set of positions within the texture data array in a first processing cycle (Seiler, para. [0123], disclosing the 4x4 texel array from the texel buffer memories in one read operation).
However, Seiler does not expressly disclose prior to performing the texture processing operation, providing another texture data element as an input for the texture processing operation from the texture data elements having the set of positions within the texture data array in a second processing cycle; and performing the texture processing operation using the two texture data elements provided in the first and second processing cycles from the texture data elements having the set of positions within the texture data array.
On the other hand, Fetterman discloses prior to performing the texture processing operation, providing another texture data element as an input for the texture processing operation from the texture data elements having the set of positions within the texture data array in a second processing cycle (Fetterman, para. [0107], disclosing serializing the access to the texel data into multiple clock cycles, serializing the access indicating each texel is accessed at a time, therefore one texel is provided as input for a texture processing operation in one processing cycle, and another texel is provided in another processing cycle); and performing the texture processing operation using the two texture data elements provided in the first and second processing cycles from the texture data elements having the set of positions within the texture data array (Fetterman, para. [0107], disclosing collecting and deserializing the texel data until all the texel data needed to complete each individual request is accumulated, and texture instruction (texture filtering operation) is completed afterwards).
Before the effective filing date of the claimed invention, it would have been obvious for a person skilled in the art to modify Seiler with Fetterman. The suggestion/motivation would have been to accommodate certain access constraints on the memory cache within the data unit, as suggested by Fetterman (see Fetterman, para. [0107]).
Allowable Subject Matter
Claim(s) 9 and 19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, none of the prior art on the record discloses wherein the step of bit shifting the data string containing the plurality of adjacent texture data elements in order to select the texture data element having the particular sub-position within the plurality of adjacent texture data elements comprises shifting the texture data element having the particular sub-position into the lowest significant bits of the data string without modifying an upper number of bits in the data string.
Claim 19 recites similar limitations discussed above with respect to claim 9.
Therefore, claims 9 and 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HAIXIA DU/Primary Examiner, Art Unit 2611