Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 10651840 B2 and Qin hereinafter.) further in view of Aswell et al. (US 4451742 and Aswell hereinafter.).
Regarding claim 1, Qin discloses a circuit [fig. 1a and 3], comprising: an input supply voltage terminal [V_BUS]; an output control voltage terminal [ZN]; a detection circuit [110 of fig. 1a corresponding to 325 of fig. 3] coupled to the input supply voltage terminal and the output control voltage terminal [as shown]. Qin does not explicitly disclose the detection circuit including a back-up supply voltage input and configured to discharge the output control voltage terminal, responsive to a difference in potential between the back-up supply voltage input and the input supply voltage terminal exceeding a threshold voltage, then discharge the back-up supply voltage input.
However, Aswell discloses [fig. 1-5] the detection circuit [fig. 1] including a back-up supply voltage input [24] and configured to discharge the output control voltage terminal [PDR high], responsive to a difference in potential between the back-up supply voltage input and the input supply voltage terminal [Vcc] exceeding a threshold voltage [Vcc falling below 134 at 156], then discharge the back-up supply voltage input [col 7 lines 31-38, 24 providing voltage to circuit Vcc through 170, 162]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Qin to include the detection circuit including a back-up supply voltage input and configured to discharge the output control voltage terminal, responsive to a difference in potential between the back-up supply voltage input and the input supply voltage terminal exceeding a threshold voltage, then discharge the back-up supply voltage input as taught by Aswell to improve reliability of a power supplying circuit.
Regarding claim 6, Qin in view of Aswell discloses further comprising an output circuit [Qin, fig. 1a, sequential logic circuit 125] having its input coupled to the output control voltage terminal and configured to generate a reset signal based on a state of the output control voltage terminal [Qin, reset signal Zn output from 100 and into 125].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Qin in view of Aswell further in view of Chen at al. (CN 116665579 A and Chen hereinafter.).
Regarding claim 2, Qin in view of Aswell discloses wherein: a POR circuit coupled to the input supply voltage terminal [Aswell, as shown in fig. 5], having a POR circuit output coupled to the output control voltage terminal [Aswell, as shown in fig. 5], and comprising a reference voltage source [Qin, fig. 2a, voltage at node N1 biasing M3 and M4], a first transistor [Qin, M2] having a first current terminal, a second current terminal, and a control terminal, with the first current terminal of the first transistor coupled to the input supply voltage terminal [Qin, V_BUS] and the control terminal of the first transistor coupled to the reference voltage source [as shown], a resistor [Qin, R1] coupled between the second current terminal of the first transistor and the output control voltage terminal [as shown], and a capacitor coupled between the output control voltage terminal and a ground termina [Qin, fig. 3, capacitor C1]. Qin in view of Aswell does not explicitly disclose and the detection circuit comprises a second transistor having a first current terminal, a second current terminal, and a control terminal, with the control terminal of the second transistor coupled to the input supply voltage terminal, and the first current terminal of the second transistor coupled to the back-up supply voltage input, and a discharge circuit coupled to the second current terminal of the second transistor and to the output control voltage terminal.
However, Chen discloses the detection circuit [power supply with reset sub-circuit] comprises a second transistor [115] having a first current terminal, a second current terminal, and a control terminal, with the control terminal of the second transistor coupled to the input supply voltage terminal [control terminal coupled to 107 through 114], and the first current terminal of the second transistor coupled to the back-up supply voltage input [node between 111 and 114], and a discharge circuit [Chen, 116] coupled to the second current terminal of the second transistor and to the output control voltage terminal [Chen, 102]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Qin in view of Aswell to include the detection circuit comprises a second transistor having a first current terminal, a second current terminal, and a control terminal, with the control terminal of the second transistor coupled to the input supply voltage terminal, and the first current terminal of the second transistor coupled to the back-up supply voltage input, and a discharge circuit coupled to the second current terminal of the second transistor and to the output control voltage terminal as taught by Chen to improve power consumption of a circuit.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Qin in view of Aswell further in view of Zhang et al. (US 20230103263 A1 and Zhang hereinafter.).
Regarding claim 7, Qin in view of Aswell discloses all the features regarding claim 1 as indicated above. Qin in view of Aswell does not explicitly disclose a DC-to-DC power converter comprising the circuit of claim 1.
However, Zhang discloses a DC-to-DC power converter [dc-dc converter 100] comprising a power supply [116]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Qin in view of Aswell in to include a DC-to-DC power converter comprising a power supply as taught by Zhu to improve stability and noise performance in a circuit.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Qin further in view of Aswell.
Regarding claim 8, Zhang discloses a controller [fig. 1, controller 110], comprising: a pulse width modulation circuit [para. 15, control pulses] configured to determine a switching element duty cycle for a power converter based [102 and 104] on a comparison between a reference voltage and a feedback voltage representative of an output voltage of the power converter [112 accepting vref 118 and VOUT]; and a voltage monitoring circuit [power stage 204 of fig. 2 comprising 300 of fig. 3 and 210 corresponding to 314] comprising a reset block including a first transistor [302] coupled between an input supply voltage terminal [Vin] and a resistor [a first resistor of 210], with the resistor coupled between the first transistor and a control output [inverting input of 202]. Zhang does not explicitly disclose detection block including a second transistor and a discharge module, the second transistor having a control terminal coupled to the input supply voltage terminal, and the discharge module configured to discharge voltage at the control output, a supply block having a third transistor coupled to the input supply voltage terminal and to the second transistor, the discharge module further configured to discharge an output of the supply block; and an output circuit coupled to the control output and configured to provide an enable signal for the controller.
However, Qin discloses a detection block [110 of fig. 1a corresponding to 325 of fig. 3] including a second transistor [M8] and a discharge module [fig. 3, falling detector circuit 340 discharging C1], the second transistor having a control terminal coupled to the input supply voltage terminal [V_BUS], and the discharge module configured to discharge voltage at the control output [EN of 350]; a supply block having a third transistor [M10] coupled to the input supply voltage terminal and to the second transistor [as shown]. Qin discloses further an output circuit [C2] coupled to the control output and configured to provide an enable signal for the controller [C2 filtering and holding a charge onto EN of 350]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Zhang to include a brown-out detection block including a second transistor and a discharge module, the second transistor having a control terminal coupled to the input supply voltage terminal, and the discharge module configured to discharge voltage at the control output to a ground terminal, a supply block having a third transistor coupled to the input supply voltage terminal and to the second transistor, and an output circuit coupled to the control output and configured to provide an enable signal for the controller as taught by Qin to improve battery life and stability of a system by reducing power consumption during normal operation. Zhang in view of Qin does not explicitly disclose the discharge module further configured to discharge an output of the supply block.
However, Aswell discloses the discharge module further configured to discharge an output of the supply block [col 7 lines 31-38, 24 providing voltage to circuit Vcc through 170, 162]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Zhang in view of Qin to include the discharge module further configured to discharge an output of the supply block as taught by Aswell to improve reliability of a power supplying circuit.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Qin further in view of Aswell further in view of Ego et al. (US 20180107257 A1 and Ego hereinafter.) further in view of Aswell.
Regarding claim 9, Zhang in view of Qin further in view of Aswell discloses further wherein the resistor is a first resistor [given]. Zhang in view of Qin further in view of Aswell does not explicitly disclose the discharge module comprises a second resistor coupled to the second transistor.
However, Ego discloses the discharge module [fig. 4, reset signal generating circuit 120] comprises a second resistor [R1] coupled to the second transistor [M2]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Zhang in view of Qin further in view of Aswell to include the discharge module comprises a second resistor coupled to the second transistor as taught by Ego to improve power consumption and stability in a power-on reset circuit.
Regarding claim 10, Zhang in view of Qin further in view of Aswell further in view of Ego discloses further wherein the discharge module comprises a fourth transistor [M3] coupled to the control output [Ego, fig. 4, output circuit 124] and coupled to the second resistor [as shown].
Regarding claim 11, Zhang in view of Qin further in view of Aswell further in view of Ego discloses further comprising a fifth transistor [Ego, fig. 4, M1] coupled between the second resistor and a ground terminal [as shown].
Regarding claim 12, Zhang in view of Qin further in view of Aswell further in view of Ego discloses the claimed invention except for a threshold voltage of the fifth transistor is lower than a threshold voltage of the fourth transistor. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a threshold voltage of the fifth transistor is lower than a threshold voltage of the fourth transistor, since it has been held that discovering an optimum value of a result effective variable involves only routine Skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 13, Zhang in view of Qin further in view of Aswell further in view of Ego discloses further wherein the output circuit comprises a Schmitt trigger [Ego, fig. 4, 124 comprising Schmitt trigger 126] having a first terminal coupled to the control output [node N1] and a second terminal coupled to an output terminal [POR output].
Claims 14-15, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Blanco et al. (US 20220231611 A1 and Blanco hereinafter.) in view of Aswell.
Regarding claim 14, Blanco discloses a voltage monitoring circuit [fig. 1] comprising: a first block [fig. 2 and 4, FDD circuit 206] configured to assert a first control signal on a control output [para. 20, FDD having a first value], responsive to an input voltage on an input supply voltage terminal falling below a first threshold at a first rate [fig. 5B and 5C, showing 510 vs 515, para. 43-44]; a second block configured to assert a second control signal on the control output [para. 20, FDD having a second value], responsive to the input voltage on the input supply voltage terminal falling below a second threshold at a second rate faster than the first rate [para. 43-44, rate of 510 faster than 515 thereby changing FDD]; an output circuit coupled to the control output and configured to assert a reset signal based on the first or second control signal [fig. 2, 222 outputting an output signal based on FDD]. Blanco does not explicitly disclose a discharge module configured to discharge a voltage at the control output, then discharge an output of a supply block in response to sending the reset signal.
However, Aswell discloses a discharge module configured to discharge a voltage at the control output, then discharge an output of a supply block in response to sending the reset signal [col 7 lines 31-38, 24 providing voltage to circuit Vcc through 170, 162]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Blanco to include a discharge module configured to discharge a voltage at the control output, then discharge an output of a supply block in response to sending the reset signal as taught by Aswell to improve reliability of a power supplying circuit.
Regarding claim 15, Blanco in view of Aswell discloses further wherein the first block comprises a transistor coupled in series with a resistor [Blanco, resistor 420 in series with 418 or 416].
Regarding claim 17, Blanco in view of Aswell discloses further wherein the second block comprises a transistor having a gate terminal coupled to the input supply voltage terminal [Blanco, 418 all having gate terminal coupled to VOUT through 416 and therefor] and a first current terminal coupled to a discharge module [Blanco, fig. 4, 424 shorting VOUT to ground].
Regarding claim 18, Blanco in view of Aswell discloses further wherein the transistor is a first transistor, and the second block comprises a second transistor [Blanco, fig. 4, transistor 408] having a control terminal coupled to a reference source [Blanco, fig. 4, current source 402 through 406], a first current terminal coupled to the input supply voltage terminal [Blanco, VOUT], and a second current terminal coupled to a second current terminal of the first transistor [Blanco, through 416].
Regarding claim 20, Blanco in view of Aswell discloses further a voltage regulator [Blanco, fig. 1, para. 22], comprising: the voltage monitoring circuit of claim 14; a feedback circuit configured to provide a feedback voltage representative of an output voltage of the voltage regulator [fig. 3, feedback signal Vfb]; a first switching element [fig. 3, switch 354] coupled between the input supply voltage terminal and a switching terminal [unlabeled control terminal of 354]; a first driver [fig. 3, 350] coupled to a control terminal of the first switching element; a second switching element [314] coupled between the switching terminal and the ground rail terminal [given], such that the first and second switching elements are serially connected [354 and 314 coupled together through 322, 324, 326, 328] between the input supply voltage terminal and the ground rail terminal [given]; a second driver [302] coupled to a control terminal of the second switching element [through 314 intself]; a reference generator circuit [unlabeled circuitry providing Vref] configured to generate a reference voltage [Vref]; and a pulse width modulation circuit [circuitry providing Vfb and snooze] configured to determine a duty cycle [on/off timing] of the first switching element [350 controlling first switch] and the second switching element [314 controlled by snooze_z signal wherein snooze_z is inverted version os snooze] based on a comparison between the feedback voltage and the reference voltage [305 and 302 acting as comparators].
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Blanco in view of Aswell further in view of Zhu et al. (US 20060076977 A1 and Zhu hereinafter.).
Regarding claim 16, Blanco in view of Aswell discloses all the features regarding claim 14 as indicated above. Blanco in view of Aswell does not explicitly disclose further comprising a capacitor coupled between the control output and a ground rail terminal.
However, Zhu discloses further comprising a capacitor coupled between the control output and a ground rail terminal [fig. 5, resistor 512]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Blacno in view of Aswell to include a capacitor coupled between the control output and a ground rail terminal as taught by Zhu to improve stability and noise performance in a circuit.
Regarding claim 19, Blanco in view of Aswell discloses all the features regarding claim 18 as indicated above. Blanco in view of Aswell does not explicitly disclose wherein the second block comprises a capacitor coupled between the second current terminal of the first transistor and a ground rail terminal.
However, Zhu discloses wherein the second block comprises a capacitor coupled between the second current terminal of the first transistor and a ground rail terminal [fig. 5, resistor 512]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Blacno in view of Aswell to include a capacitor coupled between the control output and a ground rail terminal as taught by Zhu to improve stability and noise performance in a circuit.
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8 and 14 have been considered but are moot because the new ground of rejection. Regarding claims 1, prior art rejections based on Qin is maintained, and a new ground(s) of rejection is made in view of Aswell as set forth above. Regarding claims 8, prior art rejections based on Zhang in view of Qin is maintained, and a new ground(s) of rejection is made in view of Aswell as set forth above. Regarding claims 41, prior art rejections based on Blanco is maintained, and a new ground(s) of rejection is made in view of Aswell as set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/Examiner, Art Unit 2842
/METASEBIA T RETEBO/Primary Examiner, Art Unit 2842