DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendments, filed on 11/12/2025, have been received and made of record. In response to the most recent Office Action, dated 09/11/2025, claims 1-20 have been amended. Currently claims 1-20 are pending.
Response to Arguments
Applicant’s amendments, filed on 11/12/2025, have been entered and fully considered. In light of the amendments, the rejection(s) have been withdrawn. However, upon further consideration, a new ground(s) of rejection(s) have been made, and applicant's arguments are rendered moot.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/22/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Taban (US 10079541 B1).
Regarding claim 1, Taban teaches a voltage converter (Figure 6; Figure 3 shows more details of Components 20 and 30 seen in Figure 6), comprising: a converter stage comprising a direct current to direct current (DC-to-DC) voltage converter (Figure 6 Component 30; Figure 3 Component 30), wherein the converter stage receives a first DC voltage (Figure 3 Component Vdclink) and outputs a second DC voltage different than the first DC voltage (Figure 3 Component LV1); a boost pre-stage (Figure 3 Component 20) comprising a boosting circuit (Figure 3 Component L1+Q2+D2) and a capacitor (Figure 3 Component Cdclink), wherein the boost pre-stage receives a DC voltage from a battery (Figure 3 Component HV1) and outputs a boosted DC voltage to the converter stage as the first DC voltage (Figure 3 Component Vdclink), wherein the boosted DC voltage is greater than the DC voltage from the battery (Col. 7 Lines 4-11 highlights that Component 20 can be operated as a boost converter thus would boost the voltage from Component HV1); wherein the boosted DC voltage of the boost pre-stage acts as an input to the converter stage (Figure 3 Component Vdclink receives the boosted voltage and outputs it to Component 30 as an input), wherein the boost pre-stage is configured to provide fault resistant operation of the converter stage, based on the boosted DC voltage (Figure 6 Component 20 is controlled based on the boosted DC voltage sensed by Component 44), in the event of one or more fluctuations in an operating range of the DC voltage from the battery (Col. 7 Lines 4-11; Col. 8 Lines 46-58; Col. 9 Lines 43-58).
Regarding claim 2, Taban teaches all the limitations of claim 1. Taban further teaches wherein the boosting circuit comprise an inductor (Figure 3 Component L1), a diode (Figure 3 Component D2), and a switch (Figure 3 Component Q2), and wherein an output of the boosting circuit charges the capacitor and provides electrical power to the DC-to-DC voltage converter (Figure 6 Component Cdclink is charged by the output of Component 20).
Regarding claim 3, Taban teaches all the limitations of claim 2. Taban further teaches wherein discharge of the capacitor provides electrical power to the DC-to-DC voltage converter (Figure 6 Component Vdclink, which is the voltage at the DC link capacitor, is the input for Component 30).
Regarding claim 4, Taban teaches all the limitations of claim 2. Taban further teaches a controller configured to control operation of the switch to effect charging of the capacitor (Figure 6 Component 40).
Regarding claim 6, Taban teaches all the limitations of claim 1. Taban further teaches wherein the first DC voltage is greater than the second DC voltage (Col. 7 Lines 31-46 highlights that the second voltage is around 12V which is a lower voltage).
Regarding claim 7, Taban teaches all the limitations of claim 1. Taban further teaches wherein the first DC voltage is one of equal to or greater than 400 volts (Col. 3 Lines 5-8 highlights that the input voltage to the pre-regulator can be 480 or greater than 400 and when boosted by the preregular the first voltage would be greater than or equal to 400) and the second DC voltage is one of equal to or less than 12 volts (Col. 7 Lines 42-46; Col. 3 Lines 20-22).
Regarding claim 8, Taban teaches all the limitations of claim 1. Taban further teaches wherein the DC-to-DC voltage converter of the converter stage supplies electrical power from a high voltage battery (Figure 6 Component HV) to electrical loads on a low voltage network to power the electrical loads (Figure 6 Component LV and Rload).
Regarding claim 9, Taban teaches all the limitations of claim 1. Taban further teaches wherein the DC- to-DC voltage converter of the converter stage supplies electrical power from a high voltage battery (Figure 6 Component HV) to a low voltage battery to charge the low voltage battery (Figure 6 Component LV).
Regarding claim 10, Taban teaches all the limitations of claim 1. Taban further teaches a vehicle comprising the voltage converter according to claim 1 (Col. 1 Lines 10-14).
Regarding claim 11, Taban teaches a non-transitory computer readable storage medium having stored computer executable instructions for controlling (Col. 7 Lines 47-50; Figure 6 Components 40+50) a voltage converter (Figure 6; Figure 3 shows more details of Components 20 and 30 seen in Figure 6) comprising (i) a converter stage comprising a direct current to direct current (DC-to-DC) voltage converter (Figure 6 Component 30; Figure 3 Component 30) and (ii) a boost pre-stage (Figure 3 Component 20) comprising a boosting circuit (Figure 3 Component L1+Q2+D2) and a capacitor (Figure 3 Component Cdclink), wherein execution of the computer executable instructions causes the converter to: in response to receipt of a DC voltage from a battery (Figure 3 Component HV1), output a boosted DC voltage to the converter stage (Figure 3 Component Vdclink), wherein the boosted DC voltage is greater than the DC voltage from the battery (Col. 7 Lines 4-11 highlights that Component 20 can be operated as a boost converter thus would boost the voltage from Component HV1); and receive the boosted DC voltage at the converter stage as a first DC voltage (Figure 3 Component Vdclink receives the boosted voltage and outputs it to Component 30 as an input) and output from the converter stage a second DC voltage (Figure 3 Component LV1), wherein the second DC voltage is different than the first DC voltage (Figure 3 Component LV1 is a different voltage than Vdclink); wherein the boosted DC voltage of the boost pre-stage acts as an input to the converter stage (Figure 3 Component Vdclink receives the boosted voltage and outputs it to Component 30 as an input), wherein the boost pre-stage is configured to provide fault resistant continued operation of the converter stage (Figure 6 Component 20 is controlled based on the boosted DC voltage sensed by Component 44), based on the boosted DC voltage, in the event of one or more fluctuations in an operating range of the DC voltage from the battery (Col. 7 Lines 4-11; Col. 8 Lines 46-58; Col. 9 Lines 43-58).
Regarding claim 12, Taban teaches all the limitations of claim 11. Taban further teaches wherein the boosting circuit comprises an inductor (Figure 3 Component L1), a diode (Figure 3 Component D2), and a switch (Figure 3 Component Q2), and wherein an output of the boosting circuit charges the capacitor and provides electrical power to the DC-to-DC voltage converter (Figure 6 Component Cdclink is charged by the output of Component 20).
Regarding claim 13, Taban teaches all the limitations of claim 12. Taban further teaches wherein discharge of the capacitor provides electrical power to the DC- to-DC voltage converter (Figure 6 Component Vdclink, which is the voltage at the DC link capacitor, is the input for Component 30).
Regarding claim 14, Taban teaches all the limitations of claim 12. Taban further teaches wherein the voltage converter further comprises a controller, and wherein execution of the computer executable instructions causes the controller to operate the switch to effect charging of the capacitor (Figure 6 Components 40+50).
Regarding claim 16, Taban teaches all the limitations of claim 11. Taban further teaches wherein the first DC voltage is greater than the second DC voltage (Col. 7 Lines 31-46 highlights that the second voltage is around 12V which is a lower voltage).
Regarding claim 17, Taban teaches all the limitations of claim 11. Taban further teaches wherein the first DC voltage is one of greater than or equal to 400 volts (Col. 3 Lines 5-8 highlights that the input voltage to the pre-regulator can be 480 or greater than 400 and when boosted by the preregular the first voltage would be greater than or equal to 400) and the second DC voltage one of is less than or equal to 12 volts (Col. 7 Lines 42-46; Col. 3 Lines 20-22).
Regarding claim 18, Taban teaches all the limitations of claim 11. Taban further teaches wherein the DC-to-DC voltage converter of the converter stage supplies electrical power from a high voltage battery (Figure 6 Component HV) to electrical loads on a low voltage network to power the electrical loads (Figure 6 Component LV and Rload).
Regarding claim 19, Taban teaches all the limitations of claim 11. Taban further teaches wherein the DC-to-DC voltage converter of the converter stage supplies electrical power from a high voltage battery (Figure 6 Component HV) to a low voltage battery to charge the low voltage battery (Figure 6 Component LV).
Regarding claim 20, Taban teaches all the limitations of claim 11. Taban further teaches a vehicle comprising the non-transitory computer readable storage medium according to claim 11 (Col. 1 Lines 10-14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Taban (US 10079541 B1) in view of Park (US 11351881 B1).
Regarding claim 5, Taban teaches all the limitations of claim 1. Taban does not teach a DC link capacitor connected in parallel with a primary side of the DC-to-DC voltage converter of the converter stage.
Park teaches a power converter (Figure 4), comprising: a capacitor (Figure 4 Component Cdc); a DC-DC converter (Figure 4 Components 44+45+46+48); and a DC link capacitor connected in prallel with a primary side of the DC-DC converter (Figure 4 Component C1).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Taban to incorporate a DC link capacitor in parallel with the primary side as taught by Park. The benefit of this design is that it will help enhance voltage stability by being in parallel with the capacitor taught by Taban.
Regarding claim 15, Taban teaches all the limitations of claim 11. Taban does not teach wherein the voltage converter further comprises a DC link capacitor connected in parallel with a primary side of the DC-to-DC voltage converter of the converter stage.
Park teaches a power converter (Figure 4), comprising: a capacitor (Figure 4 Component Cdc); a DC-DC converter (Figure 4 Components 44+45+46+48); and a DC link capacitor connected in prallel with a primary side of the DC-DC converter (Figure 4 Component C1).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Taban to incorporate a DC link capacitor in parallel with the primary side as taught by Park. The benefit of this design is that it will help enhance voltage stability by being in parallel with the capacitor taught by Taban.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Shahzeb K Ahmad/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
Prosecution Insights