Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-28 are pending in the application under prosecution and have been examined. Claims 3, 5-7 and 9-20 have been canceled by applicant’s amendment. Claims 21-28 have been added.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 8, 21, 24-25, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over US 20230067307 (NATARAJAN et al) in view of US 20230125798 (FISHWICK et al).
With respect to claims 1, 21, and 25, NATARAJAN teaches apparatus comprising: processing circuitry coupled to a memory having memory portions [system comprising: a plurality of memory processors coupled to a plurality of memory devices of a memory system, the memory system subdivided into a plurality of memory addressable regions (Par. 000041-0043)]; the processing circuitry to: perform memory address hashing for the memory portions to generate memory address mapping [the processor to perform a hash of the particular address with resulting address hash used to map the particular address, resulting in allocation request identifying address region which) [Par. 0041-0043; Par. 0099-0100]; [the processor configured to issue memory requests using fetch address in a hashing algorithm, to perform a hash of the particular address with resulting hash value used to map the particular address to reallocate a portion of a cache memory circuit, that is currently in use, to a directly-addressable address region) [Par. 0041-0043; Par. 0099-0106; Par. 0075-0076].
NATARAJAN suggests generate one or more memory address hashes, wherein a memory address hash includes a mapping of one or more active memory portions of the memory portions to one or more memory addresses and output the memory address hash (hashing of the particular address with resulting hash value used to map the particular address to reallocate a portion of a cache memory circuit, that is currently in use to a directly-addressable address region) [Par. 0041-0043; Par. 0099-0106; Par. 0075-0076].
TAO, using the disclosure of NATARAJAN, completes the claimed invention suggesting HASH module: receiving the source MAC address or CPU configuration MAC address input by the MAC address obtaining module, performing HASH operation, obtaining the HASH mapping address indicating the source MAC address or the CPU configuration MAC address in the SRAM module storing position, and outputting to the SRAM storage module; receiving the target MAC address input by the MAC address obtaining module; performing HASH operation to obtain the HASH mapping address indicating the storage position of the target MAC address in the SRAM module, and outputting to the SRAM storage module [See Contents of the Invention, Pages 4-6].
Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing date of the instant application to combine the feature performing a hash of the particular address with resulting hash value used to map the particular address to reallocate a portion of a cache memory circuit, as taught by NATARAJAN, with the system and method for exchanging chip address storage, taught by TAO, because the combination would provide providing a fast parallel exchange of chip address storage and for the addresses divided into multiple parallel to realize a high performance mechanism that reduces power consumption for each portion of the memory, as taught by TAO.
With respect to claims 8, 24, and 28, NATARAJAN and TAO teach the apparatus, wherein the one or more processors include one or more graphics processing units (NATARAJAN’s Fig. 11; Par. 0151; Par. 0103].
Allowable Subject Matter
Claims 2, 4, 22-23, and 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190044859 A1 (CHANG et al) teaching Network Computing Device For Managing Growth Of Exact Match Hash Table, Has Controller For Configuring Bucket Threshold Value As Function Of Hash Size Of Hash Table And Mapping Generated Virtual Bucket Address To Physical Bucket Address
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached at (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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