DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The amendment filed on 03 February, 2026 has been fully considered and entered.
Response to Arguments
Applicant's arguments with respect to claims 1, 10, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the claim objections:
Applicant's arguments filed 03 February, 2026 have been fully considered but they are not persuasive.
Applicant argues that each claim is consistent in its use of “plugs” and “vias”, without intermixing the terms within a single claim, and that the scope of each claim is readily ascertainable when read in light of the specification, and therefore no defect has been identified that would warrant correction as a matter of claim clarity or definiteness.
Examiner disagrees. The use of multiple terms to refer to the same element presents a confusing variety of terms, especially given that “plugs” are primarily used throughout the specification to describe elements 316 and 320, while vias are primarily used throughout the specification to refer to vias 1928b and 2110. Examiner notes that this is in addition to the obscuring nature of the hatch marks in the drawings, although some of the drawings were improved by the amendments submitted on 03 February, 2026. In combination, these problems obscure the invention as a whole. According to the MPEP, “The use of a confusing variety of terms for the same thing should not be permitted.” (See MPEP Section 608.01(o)). Therefore, the claim objection is maintained.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the plurality of plugs collectively forming a perforated sheet of thermally conductive material and the electrically isolated sections formed by junctions including p-type regions and n-type regions must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17, 21, 23, and 26 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 17: The originally filed disclosure does not provide support for “wherein the means for conducting heat is not electrically coupled to any power supply node or ground node or to any active component of the PIC die.”
Regarding claim 21: The originally filed disclosure does not provide support for “wherein the plurality of plugs are not electrically coupled to a power supply node of the photonic integrated circuit die, wherein the plurality of plugs are not electrically coupled to a ground node of the photonic integrated circuit die.”
Regarding claim 23: The originally filed disclosure does not provide support for “wherein, for individual contact pads of the plurality of contact pads, the distal ends of the plurality of vias are not electrically coupled to any power supply node or ground node”.
Regarding claim 26: The originally filed disclosure does not provide support for “the plurality of plugs collectively form a perforated sheet of thermally conductive material, the perforated sheet including a plurality of openings that reduce mechanical stress in the photonic integrated circuit die.”
Claims 5, 14, 22, and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 5 and 14: Claims 5 and 14 recite wherein, for individual contact pads of the plurality of contact pads, the plurality of plugs/vias are arranged in a plurality of concentric rings. It is unclear whether this requires one individual contact pad to have at least one plug/via in one ring and another plug/via in a different concentric ring, or whether it means that the plurality of plugs/vias are required to be part of an arrangement that comprises a plurality of concentric rings, wherein the plurality of plugs/vias for an individual contact pad can be located in just one of the rings. For the purpose of examination, the claim is understood to only require that the plurality of plugs/vias be part of an arrangement comprising a plurality of concentric rings.
Regarding claim 22: Claim 22 defines “a plurality of plugs”, and depends on claim 1, which also defines “a plurality of plugs”. It is unclear whether these are referring to the same plurality of plugs, a subset of the previously claimed plurality of plugs, or an additional plurality of plugs. For the purpose of examination, any of these interpretations is considered to read on the claim.
Regarding claim 26: Claim 26 is unclear because it is unclear how “a plurality of plugs” can collectively form a perforated sheet of thermally conductive material, the perforated sheet including a plurality of openings. Are the plurality of plugs the plurality of openings? Or are the plurality of plugs joined together into one sheet? If they are the openings, the plurality of openings cannot be claimed as separate elements. Alternatively, if they are joined together into one sheet, it is not clear how it is reasonable to call them “a plurality of plugs” since, as best understood by the examiner, they would become indistinguishable parts of a singular object. Since the scope of the claim is unclear, examiner looked to the specification and drawings for clarity but found that a plurality of plugs forming a perforated sheet is not described or illustrated in the disclosure. As a result, a meaningful formulation of art rejections cannot be done at this time. See MPEP 2173.06 II, 2nd paragraph:
… where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art. … a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
Therefore, claim 26 has not been further considered with respect to prior art. This is not an indication of allowable subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 17, 21, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iida et al. (US 2019/0004342; hereinafter Iida).
Regarding claim 1: Iida discloses A photonic integrated circuit (PIC) die (Figs. 12-13 and 17) comprising: a substrate layer (Fig. 13, substrate SB); a first dielectric layer adjacent the substrate layer (Fig. 13, BOX layer); a waveguide layer (Fig. 13, waveguide layer comprising IL1 and IL2) adjacent the first dielectric layer, wherein one or more waveguides are defined in the waveguide layer (Fig. 13, the waveguide layer as defined above contains one or more waveguides CR1); a second dielectric layer adjacent the waveguide layer (Fig. 13, second dielectric layer comprising IL3 and IL4); and a plurality of contact pads adjacent the second dielectric layer (Figs. 12 and 13, heat radiation plate RB), wherein, for individual contact pads of the plurality of contact pads, a plurality of plugs (Figs. 12-13, plugs PGs) extend from the corresponding contact pad and through the second dielectric layer (Fig. 13 shows this or one via for each contact pad of the plurality of contact pads; however, Fig. 12 shows that multiple vias extend from each contact pad).
Regarding claim 2: Iida disclosesThe PIC die of claim 1 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the plurality of plugs extending from the corresponding contact pad comprise a proximal end near the corresponding contact pad and a distal end opposite the proximal end, wherein, for individual contact pads of the plurality of contact pads, the distal ends of the plurality of plugs are not electrically coupled to any active component of the PIC die (see paragraph 0051 and claim 1).
Regarding claim 3: Iida disclosesThe PIC die of claim 1 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the plurality of plugs extend to an electrically isolated section of the waveguide layer (see Fig. 13, portion of IL1 not in direct contact with heater MH1 and including waveguide CR1 is electrically isolated by insulating material), wherein the electrically isolated section is electrically isolated from a remainder of the waveguide layer (the remainder of the waveguide layer is considered to be the portion of the layer of IL1 in direct contact with the heater as well as the whole of IL2), wherein the electrically isolated section comprises silicon (see paragraph 0046, CR1, included in the electrically isolated section, comprises silicon).
Regarding claim 5, as best understood: Iida disclosesThe PIC die of claim 1 (as applied above), wherein, for individual contact pads of the plurality of contact pads (for each of the inner ring and the two portions of the outer ring in Fig. 17), the plurality of plugs (Fig. 17, plugs PG) are arranged in a plurality of concentric rings (the plurality of plugs of each of the inner ring and the two portions of the outer ring in Fig. 17 are each arranged in a plurality of concentric rings).
Regarding claim 6: Iida disclosesThe PIC die of claim 1 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the plurality of plugs have a thermal conductivity of at least 90 W/(mK) (see paragraph 0054, the thermal pads are made of tungsten, having a thermal conductivity of at least 90 W/(mK)).
Regarding claim 7: Iida disclosesThe PIC die of claim 1 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the plurality of plugs comprise tungsten (see paragraph 0054).
Regarding claim 8: Iida disclosesThe PIC die of claim 1 (as applied above), wherein the substrate layer comprises silicon (see paragraph 0062), wherein the first dielectric layer comprises silicon and oxygen (see paragraph 0062), wherein the second dielectric layer comprises silicon and oxygen (see paragraphs 0069 and 0071).
Regarding claim 17: Iida disclosesA photonic integrated circuit (PIC) die (Figs. 12-13) comprising: a substrate layer (Fig. 13, substrate SB); a first dielectric layer adjacent the substrate layer (Fig. 13, BOX layer); a waveguide layer adjacent the first dielectric layer (Fig. 13, layer comprising IL1 and IL2), wherein one or more waveguides are defined in the waveguide layer (Fig. 13, waveguides CR1 are defined in the waveguide layer as defined above); a second dielectric layer adjacent the waveguide layer (Fig. 13, layer comprising IL3 and IL4); and a plurality of contact pads adjacent the second dielectric layer (Figs. 12 and 13, heat radiation plates RB), means for conducting heat from the plurality of contact pads through the second dielectric layer (Fig. 13 shows this for one via for each contact pad of the plurality of contact pads; however, Fig. 12 shows that multiple vias extend from each contact pad), wherein the means for conducting heat is not electrically coupled to any power supply node or ground node or to any active component of the PIC die (see paragraph 0051 and claim 1).
Regarding claim 21: Iida disclosesThe PIC die of claim 1 (as applied above), wherein the plurality of plugs are not electrically coupled to a power supply node of the photonic integrated circuit die (see paragraph 0051 and claim 1), wherein the plurality of plugs are not electrically coupled to a ground node of the photonic integrated circuit die (see paragraph 0051 and claim 1).
Regarding claim 24: Iida disclosesThe photonic integrated circuit die of claim 1 (as applied above), wherein the waveguide layer comprises a silicon layer (Fig. 13, IL1 is considered to be a silicon layer since it comprises silicon), wherein one or more waveguides are defined in the silicon layer (Fig. 13, waveguides CR1 are defined in the silicon layer), wherein the waveguide layer comprises, for individual contact pads of the plurality of contact pads, an electrically isolated section (see annotated Fig. 13, which demonstrates three electrically isolated sections corresponding to three individual contact pads of the plurality of contact pads; they are disclosed to be electrically floating and not connected to configured with circuits, and are therefore considered to be electrically isolated), wherein, for individual contact pads of the plurality of contact pads, the photonic integrated circuit die further comprises a dielectric-filled region in the waveguide layer that laterally surrounds the electrically isolated section of the waveguide layer to electrically isolate the electrically isolated section from an adjacent portion of the waveguide layer (see annotated Fig. 13, the area surrounding the identified electrically isolated sections are laterally surrounded by dielectric material to electrically isolate the electrically isolated section from an adjacent portion of the waveguide layer, including the heaters MH1).
Annotated Fig. 13:
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Claim(s) 1, 3-4, 9, 24, and 27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seetharam et al. (US 2025/0060545; hereinafter Seetharam).
Regarding claim 1: Seetharam teachesA photonic integrated circuit (PIC) die (Fig. 2, Photonic IC) comprising: a substrate (Fig. 2, substrate 101) layer; a first dielectric layer (Fig. 2, BOX layer 110) adjacent the substrate layer (BOX layer 110 is near to substrate 101 and is therefore considered adjacent); a waveguide layer (Fig. 2, region between BOX layer and IMD) adjacent the first dielectric layer (region between BOX layer and IMD is near the BOX layer and is therefore considered adjacent), wherein one or more waveguides are defined in a waveguide layer (Fig. 2, modulator 130 has a waveguide; additionally see paragraph 0036); a second dielectric layer (Fig. 2, IMD) adjacent the waveguide layer (IMD is near to the region between the BOX layer and IMD and is therefore considered adjacent); and a plurality of contact pads (Fig. 2, conductive layer 410) adjacent the second dielectric layer (conductive layer 410 is near to the IMD and is therefore considered adjacent).
Regarding claim 3: Seetharam discloses
The PIC die of claim 1 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the plurality of plugs extend to an electrically isolated section of the waveguide layer (the transmitting section, labeled Tx in Fig. 1, corresponding to the left half of the device shown in Fig. 1), wherein the electrically isolated section is electrically isolated from a remainder of the waveguide layer (the transmitting section is electrically isolated from the receiving section, and vice versa, per paragraph 0026, including a remainder of the waveguide layer, defined above as the layer between BOX layer and IMD), wherein the electrically isolated section comprises silicon (see paragraph 0030; silicon photonics platform is understood to include silicon in device layer/waveguide layer).
Regarding claim 4: Seetharam disclosesThe PIC die of claim 1 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the plurality of plugs extend to the substrate layer (see Seetharam Fig. 2), wherein the substrate layer has a resistivity more than 10 Ohm-centimeter (see paragraph 0031).
Regarding claim 9: Seetharam disclosesAn integrated circuit component comprising the PIC die of claim 1 (as applied above), further comprising: an electronic integrated circuit (EIC) die (Fig. 2, electric IC) mated with the PIC die; a plurality of solder balls (Fig. 2, solders 160) positioned between the EIC die and the PIC die, wherein individual solder balls of the plurality of solder balls are adjacent individual contact pads of the plurality of contact pads of the PIC die (Fig. 2 shows this); a circuit board (Fig. 2, printed circuit board 300) mated to the EIC die; and an integrated heat spreader (Fig. 2, both metal layers 421 and 422 are considered integrated heat spreaders thermally coupled to the PIC die; see Abstract) thermally coupled to the PIC die.
Regarding claim 24: Seetharam discloses the photonic integrated circuit of claim 1, as applied above, wherein the waveguide layer comprises a silicon layer (see paragraph 0032), wherein one or more waveguides are defined in the silicon layer (see paragraph 0032 and Fig. 1, modulator 130 is a waveguide), wherein the waveguide layer comprises, for individual contact pads of the plurality of contact pads, an electrically isolated section (the transmitting section is electrically isolated from the receiving section, and vice versa, per paragraph 0026, including a remainder of the waveguide layer, defined above as the layer between BOX layer and IMD; however, the electrically isolated sections can also be considered to be defined as smaller subsections of the transmitting and receiving sections, e.g. only extending the width of the modulator in the transmitting section and the photodiode in the receiving section, i.e. not including the surrounding dielectric), wherein, for individual contact pads of the plurality of contact pads, the photonic integrated circuit die further comprises a dielectric-filled region in the waveguide layer that laterally surrounds the electrically isolated section of the waveguide layer to electrically isolate the electrically isolated section from an adjacent portion of the waveguide layer (see Fig. 1, a dielectric-filled region in the waveguide layer laterally surrounds the electrically isolated sections of the waveguide layer for individual contact pads of the plurality of contact pads, as described above; the dielectric material inherently provides electrical isolation).
Regarding claim 27: Seetharam disclosesThe photonic integrated circuit die of claim 1 (as applied above), wherein the first dielectric layer includes a buried oxide (BOX) layer (Seetharam Fig. 2, buried oxide layer 110), wherein the plurality of plugs extend from the corresponding contact pad through the second dielectric layer and through the buried oxide layer into the substrate layer (Seetharam Fig. 2 shows this).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11, 14, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Doerr et al. (US 2013/0308898; hereinafter Doerr) in view of Iida et al. (US 2019/0004342; hereinafter Iida).
Regarding claim 10: Doerr disclosesAn integrated circuit component comprising: a photonic integrated circuit (PIC) die (Fig. 9(A), PIC); an electronic integrated circuit (EIC) die mated with the PIC die (Fig. 9(A), ASIC); and a plurality of solder balls between the PIC die and the EIC die (Fig. 9(A) shows a plurality of solder balls between the PIC die and the EIC die; additionally, see paragraphs 0086 and 0104).
Doerr fails to disclose “a plurality of contact pads are adjacent individual solder balls of the plurality of solder balls, wherein, for individual contact pads of the plurality of contact pads, a plurality of vias extend from the corresponding contact pad away from a surface of the PIC die, wherein, for individual contact pads of the plurality of contact pads, the plurality of vias extending from the corresponding contact pad comprise a proximal end near the corresponding contact pad and a distal end opposite the proximal end, wherein, for individual contact pads of the plurality of contact pads, the distal ends of the plurality of vias are not electrically coupled to any active component of the PIC die”. However, Doerr further discloses that the PIC can include thermo-optic phase shifters (see paragraph 0068). Iida teaches a thermo-optic phase shifter (Figs. 1, 12-13, and 17) which includes a plurality of contact pads (Figs. 12-13, metal films RB; see paragraph 0056), wherein, for individual contact pads of the plurality of contact pads, a plurality of vias (Figs. 12-13, vias PG) extend from the corresponding contact pad away from a surface of the PIC die (Fig. 13, top surface), wherein, for individual contact pads of the plurality of contact pads, the plurality of vias extending from the corresponding contact pad comprise a proximal end near the corresponding contact pad and a distal end opposite the proximal end (this arrangement is shown in Fig. 13), wherein, for individual contact pads of the plurality of contact pads, the distal ends of the plurality of vias are not electrically coupled to any active component of the PIC die (see paragraph 0051). Iida teaches that providing such a heat dissipation structure to the PIC improves the performance by improving thermal conduction control accuracy and increased heat dissipation efficiency (see paragraphs 0011-0015). In order to provide a PIC die having these beneficial properties, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the Doerr package with a PIC having a thermo-optic phase shifter with the heat dissipation structure taught by Iida. In providing the PIC die with such a structure, individual contact pads of the plurality of contact pads would necessarily be adjacent individual solder balls of the plurality of solder balls, since they are all located in the PIC and the subcomponents of each of the Doerr package components are all considered to be adjacent to each other.
Regarding claim 11: Modified Doerr teaches The integrated circuit component of claim 10 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the plurality of vias extend to an electrically isolated section of the waveguide layer (see Iida Fig. 13, portion of IL1 not in direct contact with heater MH1 and including waveguide CR1 is electrically isolated by insulating material), wherein the electrically isolated section is electrically isolated from a remainder of the waveguide layer (the remainder of the waveguide layer is considered to be the portion of the layer of IL1 in direct contact with the heater as well as the whole of IL2), wherein the electrically isolated section comprises silicon (see Iida paragraph 0046, CR1, included in the electrically isolated section, comprises silicon).
Regarding claim 14, as best understood: Modified Doerr teachesThe integrated circuit component of claim 10 (as applied above), wherein, for individual contact pads of the plurality of contact pads (for each of the inner ring and the two portions of the outer ring in Iida Fig. 17), the plurality of vias (Iida Fig. 17, vias PG) are arranged in a plurality of concentric rings (the plurality of vias of each of the inner ring and the two portions of the outer ring in Fig. 17 are each arranged in a plurality of concentric rings).
Regarding claim 23: Modified Doerr teaches The integrated circuit component of claim 10 (as applied above), wherein, for individual contact pads of the plurality of contact pads, the distal ends of the plurality of vias are not electrically coupled to any power supply node or ground node (see Iida paragraph 0051 and claim 1).
Claims 4 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Iida et al. (US 2019/0004342; hereinafter Iida) in view of Stuber et al. (US Patent No. 8,466,054; hereinafter Stuber).
Regarding claim 4: Iida discloses the PIC die of claim 1, as applied above. Iida further discloses that the substrate layer is made of silicon (see paragraph 0046), which has a resistivity more than 10 Ohm-centimeter. Iida fails to disclose that, for individual contact pads of the plurality of contact pads, the plurality of plugs extend to the substrate layer. Stuber, also related to heat dissipation in semiconductor-on-insulator devices (see title, abstract, and col. 1, lines 14-19), teaches that providing thermal conduction paths extending to the substrate layer (see Fig. 3, first and second thermal paths 312 and 313) allows for improved heat dissipation in SOI devices, since silicon is much more thermally conductive than silicon dioxide (see col. 1, line 62-col. 2, line 21 and col. 5, lines 1-9). In order to improve heat dissipation in the Iida device, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the Iida device by extending the plurality of plugs to the substrate layer, as taught by Stuber.
Regarding claim 22: Iida discloses the PIC die of claim 1, as applied above. Iida fails to disclose that, for individual contact pads of the plurality of contact pads, a plurality of plugs extend from the corresponding contact pad to the substrate layer and do not extend through the substrate layer. Stuber, also related to heat dissipation in semiconductor-on-insulator devices (see title, abstract, and col. 1, lines 14-19), teaches that providing thermal conduction paths extending to the substrate layer (see Fig. 3, first and second thermal paths 312 and 313) allows for improved heat dissipation in SOI devices, since silicon is much more thermally conductive than silicon dioxide (see col. 1, line 62-col. 2, line 21 and col. 5, lines 1-9). In order to improve heat dissipation in the Iida device, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the Iida device by extending the plurality of plugs to the substrate layer, such that they do not extend through the substrate layer, as taught by Stuber.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Seetharam et al. (US 2025/0060545; hereinafter Seetharam) in view of Miki (US 2023/0420468; hereinafter Miki), as evidenced by Wikipedia (Shallow trench isolation, captured on 04/21/2022 on Wayback Archive; copy attached to this Office Action; hereinafter Wikipedia).
Seetharam disclosesThe photonic integrated circuit die of claim 1 (as applied above), wherein the waveguide layer comprises a silicon layer (see paragraph 0032), wherein one or more waveguides are defined in the silicon layer (see paragraph 0032 and Fig. 1, modulator 130 is a waveguide), wherein the waveguide layer comprises, for individual contact pads of the plurality of contact pads, an electrically isolated section (the transmitting section is electrically isolated from the receiving section, and vice versa, per paragraph 0026, including a remainder of the waveguide layer, defined above as the layer between BOX layer and IMD; however, the electrically isolated sections can also be considered to be defined as smaller subsections of the transmitting and receiving sections, e.g. only extending the width of the modulator in the transmitting section and the photodiode in the receiving section, i.e. not including the surrounding dielectric).
Since Seetharam teaches that for individual contact pads of the plurality of contact pads, the electrically isolated section is electrically isolated by dielectric material laterally surrounding the electrically isolated regions, Seetharam fails to teach that the electrically isolated section is electrically isolated by at least one junction formed in the silicon layer around the electrically isolated section, the at least one junction including a p-type doped region and an n-type doped region. However, before the effective filing date of the claimed invention, Miki taught that adjacent electrically active regions of a semiconductor device can be electrically isolated from each other using an insulator structure such as STI or p-n junction isolation (see paragraphs 0059, 0070, and 0101). Using a pn-junction to provide electrical isolation to the electrically isolated regions of the waveguide layer would allow one of ordinary skill in the art to provide a high density of adjacent electrically isolated regions with simplified manufacturing, without the need of fully etching the waveguide layer and filling the etched regions with dielectric materials. Electrically isolating adjacent regions of the waveguide layer using pn-junctions would further allow a more uniform device layer with less thermal and mechanical stress induced by including two materials in the layer. For these reasons, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify the Seetharam device by electrically isolating the electrically isolated section, for individual contact pads of the plurality of contact pads, by at least one junction formed in the silicon layer around the electrically isolated section, the at least one junction including a p-type doped region and an n-type doped region, since it was suggested by Miki to be a suitable alternative to isolating adjacent regions of semiconductor material using STI, which conventionally uses dielectric materials for providing insulation, as evidenced by Wikipedia (see 2nd figure and 2nd paragraph).
Conclusion
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/KIRSTEN D. ENDRESEN/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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