DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on September 29, 2023 and May 9, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to because (a) Figures 3-4, 6-10, and 19 contain text on a shaded background, see 37 CFR § 1.84(p)(3); and (b) the periods should be deleted from the end of the text in reference characters 2606 and 2712. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 5, 12, and 19 are objected to because of the following informalities: “have a logical effect” should be “have a same logical effect”.
Claim 16 is objected to because of the following informalities: “noise generate” should be “noise generated”. Claims 17-20 are objected to for dependency on claim 16.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “circuit transpiler unit” in claims 1-2; “circuit twirling unit” in claims 1 and 4; “noise learning unit” in claim 1; and “dynamical decoupling pulse sequence insertion unit” in claims 6-7.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The claim limitations noted in the “Claim Interpretation” section above invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed functions and to clearly link the structure, material, or acts to the functions. Therefore, it is unclear whether Applicant had possession of the claimed invention as of the effective filing date. For further analysis, see rejections under 35 USC § 112(b) infra.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claim limitations noted in the “Claim Interpretation” section above invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed functions and to clearly link the structure, material, or acts to the functions.
Regarding the “circuit transpiler unit”, while paragraph 49 of the specification as originally filed provides examples of functions of the unit, no algorithm for “identif[ying] respective placement of one or more mid-circuit measurements and one or more classically controlled feed-forward operations on a quantum circuit to generate an optimized quantum circuit” and “adapt[ing] a plurality of quantum gates and one or more classically controlled instructions of the quantum circuit to a hardware that executes the plurality of quantum gates and the one or more classically controlled instructions” is provided.
Regarding the “circuit twirling unit”, paragraph 112 of the specification as originally filed recites examples of the functionality of the unit, but no full algorithm for performing the claimed function of “creat[ing] twirled layers of circuit instructions based on the optimized quantum circuit by twirling respective classical bits that control the one or more classically controlled feed-forward operations” is provided.
Regarding the “noise learning unit”, paragraph 54 of the specification as originally filed recites examples of the functionality of the unit, but no full algorithm for performing the claimed function of “learn[ing] a noise model of the twirled layers of circuit instructions based on a rank deficient Pauli transfer matrix to learn noise generated in the quantum circuit” is provided.
Regarding the “dynamical decoupling pulse sequence insertion unit”, paragraph 53 of the specification as originally filed recites examples of the functionality of the unit, but no full algorithm for performing the claimed functions of “insert[ing] a dynamical decoupling pulse sequence during an idle duration and a context-switching duration of the quantum circuit” and “insert[ing] the dynamical decoupling pulse sequence during the idle duration of the quantum circuit based on a sequence of dynamical decoupling gates” is provided.
Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. For purposes of examination, any computer software that performs the claimed functions will be deemed to read on the claims.
Applicant may:
(a) Amend the claims so that the claim limitations will no longer be interpreted as limitations under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed functions, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the functions recited in the claims, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the functions so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed functions, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed functions and clearly links or associates the structure, material, or acts to the claimed functions, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed functions. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
All claims dependent on a claim rejected hereunder are also rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 9-11, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Burgholzer et al., “Handling Non-Unitaries in Quantum Circuit Equivalence Checking,” in Proc. 59th ACM/IEEE Design Automation Conf. 529-34 (2022) (“Burgholzer”) in view of McDonough et al., “Automated Quantum Error Mitigation based on Probabilistic Error Reduction,” in IEEE/ACM Third Int’l Workshop on Quantum Computing Software 83-93 (2022) (“McDonough”) and further in view of Seif Tabrizi et al. (US 20230058207) (“Seif”).
Regarding claim 1, Burgholzer discloses “[a] system, comprising: …
a circuit transpiler unit that identifies respective placement of one or more mid-circuit measurements and one or more classically controlled feed-forward operations on a quantum circuit to generate an optimized quantum circuit (once qubit re-use is eliminated from a dynamic circuit, the only potentially non-unitary primitives remaining are mid-circuit measurements and classically-controlled operations conditioned on their result [i.e., feed-forward operations]; any mid-circuit measurement can be delayed until the very end of the quantum circuit [i.e., the system, including a circuit transpiler unit, decides to place the mid-circuit measurements at the end of the circuit] – Burgholzer, p. 4, paragraph between Examples 4 and 5; see also sec. 1, third paragraph (disclosing that alternative realizations of quantum circuit building blocks may be optimized)); [and]
a circuit … unit that creates … layers of circuit instructions based on the optimized quantum circuit by [manipulating] respective classical bits that control the one or more classically controlled feed-forward operations (any mid-circuit measurement can be delayed until the very end of the quantum circuit – replacing [and thereby controlling] any classically-controlled operations [i.e., operations controlled by classical bits] by proper quantum operations controlled by the respective qubit; by combining substitution of reset operations with “fresh” qubits and applying the deferred measurement principle, any dynamic quantum circuit can be transformed to a representation composed of unitary descriptions [layers of circuit instructions] only – Burgholzer, sec. 4, paragraphs immediately preceding and following Example 5; see also Fig. 3 (showing layers of circuit instructions)) ….”
Burgholzer appears not to disclose explicitly the further limitations of the claim. However, McDonough discloses “a circuit twirling unit that creates twirled layers of circuit instructions … by twirling respective [entities] that control the one or more … operations (Pauli noise tomography involves applying a Pauli twirl surrounding the Clifford entangling gates [entities that control entangling operations] contained in layers of a circuit [thereby creating twirled layers of circuit instructions] – McDonough, sec. III, first paragraph); and
a noise learning unit that learns a noise model of the twirled layers of circuit instructions based on a … Pauli transfer matrix to learn noise generated in the quantum circuit (PNT involves applying a Pauli twirl surrounding Clifford entangling gates contained in layers of the circuit; this converts an arbitrary noise channel into a Pauli channel; the resulting Pauli fidelities characterize the twirled noise – McDonough, sec. III, first paragraph; see also sec. III(A), second paragraph (disclosing that these Pauli fidelities are the diagonal elements of a Pauli transfer matrix)).”
McDonough and the instant application both relate to quantum computing using twirling operations and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Burgholzer to learn a noise model of twirled circuit instructions using a Pauli transfer matrix, as disclosed by McDonough, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow for robust characterization of hardware noise in large devices by keeping the number of measurements constant in the number of qubits. See McDonough, sec. I, penultimate paragraph.
Neither Burgholzer nor McDonough appears to disclose explicitly the further limitations of the claim. However, Seif discloses a [a] system, comprising:
a memory that stores computer-executable components (system for detecting a two-qubit correlated dephasing error includes a memory including instructions stored thereon – Seif, paragraph 21); and
a processor that executes the computer-executable components stored in the memory (system for detecting a two-qubit correlated dephasing error includes a processor that executes the instructions stored in the memory – Seif, paragraph 21), wherein the computer-executable components comprise: …
[a] rank deficient … matrix (for compressed sensing of “low-rank” objects (e.g., low-rank [rank deficient] density matrices, there are a few natural choices for measurements – Seif, paragraph 48) ….”
Seif and the instant application both relate to quantum computing and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Burgholzer and McDonough to use a rank-deficient matrix, as disclosed by Seif, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would facilitate measurement operations using the matrix and reduce calculations that a full-rank matrix would require. See Seif, paragraph 48.
Claim 9 is a method claim corresponding to system claim 1 and is rejected for the same reasons as given in the rejection of that claim. Similarly, claim 16 is a computer program product claim corresponding to method claim 1 and is rejected for the same reasons as given in the rejection of that claim.
Regarding claim 2, Burgholzer, as modified by McDonough and Seif, discloses that “the circuit transpiler unit adapts a plurality of quantum gates and one or more classically controlled instructions of the quantum circuit to a hardware that executes the plurality of quantum gates and the one or more classically controlled instructions (evaluations are conducted on a machine equipped with a CPU and 54 GiB RAM [hardware; note that any algorithm that runs on this hardware is thereby adapted for the hardware] – Burgholzer, sec. 6, second paragraph; once qubit re-use is eliminated from a dynamic circuit, the only potentially non-unitary primitives remaining are mid-circuit measurements and classically-controlled operations conditioned on their result; any mid-circuit measurement can be delayed until the very end of the quantum circuit [i.e., the system includes a circuit transpiler unit] – id. at p. 4, paragraph between Examples 4 and 5; see also Fig. 3(b) (showing that the circuit applying this principle includes quantum Hadamard gates)).”
Claim 10 is a method claim corresponding to system claim 2 and is rejected for the same reasons as given in the rejection of that claim. Similarly, claim 17 is a computer program product claim corresponding to method claim 2 and is rejected for the same reasons as given in the rejection of that claim.
Regarding claim 4, the rejection of claim 1 is incorporated. Burgholzer further discloses that “the … layers of circuit instructions comprise a plurality of mid-circuit measurements, a plurality of quantum gates and a plurality of feed-forward gates (Burgholzer Fig. 3(a) shows that the circuit includes mid-circuit measurements, Hadamard gates [quantum gates], and other Hadamard gates that feed forward to the Hadamard gates), and … the circuit … unit uses a set of … rules to [manipulate] the respective classical bits that control the one or more classically controlled feed-forward operations (any mid-circuit measurement can be delayed until the very end of the quantum circuit – replacing any classically-controlled operations [i.e., operations controlled by the manipulation of classical bits] by proper quantum operations controlled by the respective qubit [procedure for transforming the classically-controlled operations to quantum operations = rule]; by combining substitution of reset operations with “fresh” qubits and applying the deferred measurement principle, any dynamic quantum circuit can be transformed to a representation composed of unitary descriptions only – Burgholzer, sec. 4, paragraphs immediately preceding and following Example 5).”
Burgholzer/Seif appear not to disclose explicitly the further limitations of the claim. However, McDonough discloses “twirled layers of circuit instructions (Pauli noise tomography involves applying a Pauli twirl surrounding the Clifford entangling gates contained in layers of a circuit [thereby creating twirled layers of circuit instructions] – McDonough, sec. III, first paragraph) …, and … [a] circuit twirling unit uses a set of twirling rules to twirl the respective [entities] (Pauli noise tomography involves applying a Pauli twirl surrounding the Clifford entangling gates [Pauli twirl = rule] contained in layers of a circuit [thereby creating twirled layers of circuit instructions] – McDonough, sec. III, first paragraph) ….” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Burgholzer and Seif with to apply twirling rules to perform twirling, as disclosed by McDonough, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow for robust characterization of hardware noise in large devices by keeping the number of measurements constant in the number of qubits. See McDonough, sec. I, penultimate paragraph.
Claim 11 is a method claim corresponding to system claim 4 and is rejected for the same reasons as given in the rejection of that claim. Similarly, claim 18 is a computer program product claim corresponding to method claim 4 and is rejected for the same reasons as given in the rejection of that claim.
Claims 6-7, 13-14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Burgholzer in view of McDonough and Seif and further in view of Niu et al., “Analyzing Strategies for Dynamical Decoupling Insertion on IBM Quantum Computer,” in arXiv preprint arXiv:2204.14251 (2022) (“Niu”) and Te Raa et al. (WO 2023080786) (“Te Raa”).
Regarding claim 6, neither Burgholzer, Seif, nor McDonough appears to disclose explicitly the further limitations of the claim. However, Niu discloses “a dynamical decoupling pulse sequence insertion unit that inserts a dynamical decoupling pulse sequence during an idle duration … of the quantum circuit (to characterize the impact of a dynamical decoupling (DD) sequence on idle-idle qubit and crosstalk-idle qubit, the main qubit may be under a DD-inserted evolution during the idle time, wherein two Hadamard gates are inserted at the beginning and the end of the circuit, respectively – Niu, sec. II(C), second paragraph; see also sec. II(B), first paragraph (disclosing that DD continuously inserts pulses during the idle time)).”
Niu and the instant application both relate to quantum computing and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Burgholzer, McDonough, and Seif to insert a dynamical decoupling pulse during an idle duration of the quantum circuit, as disclosed by Niu, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would mitigate errors without extra circuit overhead. See Niu, sec. I, third paragraph.
Neither Burgholzer, McDonough, Seif, nor Niu appears to disclose explicitly the further limitations of the claim. However, Te Raa discloses “a context-switching duration of the quantum circuit (execution of quantum network applications is in contrast to the executing of quantum applications executed on a conventional quantum computer; for a conventional quantum computer, any context switching will cause decoherence to impact the qubit quality; however, in a quantum network application, idle time will leave spare capacity that can potentially be used to execute other operations – Te Raa, p. 35, l. 31-p. 36, l. 2).”
Te Raa and the instant application both relate to quantum computing and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Burgholzer, McDonough, Seif, and Niu to allow the circuit to perform context switching, as disclosed by Te Raa, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would allow the circuit to execute multiple applications. See Te Raa, p. 35, l. 31-p. 36, l. 2.
Claim 13 is a method claim corresponding to system claim 6 and is rejected for the same reasons as given in the rejection of that claim. Similarly, claim 20 is a computer program product claim corresponding to method claim 6 and is rejected for the same reasons as given in the rejection of that claim.
Regarding claim 7, Burgholzer, as modified by McDonough, Seif, Niu, and Te Raa, discloses that “the dynamical decoupling pulse sequence insertion unit inserts the dynamical decoupling pulse sequence during the idle duration of the quantum circuit based on a sequence of dynamical decoupling gates (to characterize the impact of a dynamical decoupling (DD) sequence on idle-idle qubit and crosstalk-idle qubit, the main qubit may be under a DD-inserted evolution during the idle time, wherein two [sequence of] Hadamard gates [dynamical decoupling gates] are inserted at the beginning and the end of the circuit, respectively – Niu, sec. II(C), second paragraph; see also sec. II(B), first paragraph (disclosing that DD continuously inserts pulses during the idle time)).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Burgholzer, McDonough, Te Raa, and Seif to insert a dynamical decoupling pulse during an idle duration of the quantum circuit, as disclosed by Niu, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would mitigate errors without extra circuit overhead. See Niu, sec. I, third paragraph.
Claim 14 is a method claim corresponding to system claim 7 and is rejected for the same reasons as given in the rejection of that claim.
Allowable Subject Matter
Claims 8, 12, 15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 3 and 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C VAUGHN whose telephone number is (571)272-4849. The examiner can normally be reached M-R 7:00a-5:00p ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar, can be reached at 571-272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN C VAUGHN/ Primary Examiner, Art Unit 2125
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