DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-9 have been amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant's arguments filed 07/17/2025 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments that Swarbrick in view of Georgiou does not teach “a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with the interconnection resource configurable for off-die communication” of claim 1, the Examiner respectfully disagrees.
Swarbrick discloses an SoC communication system (See Swarbrick: Fig. 2, SoC 102) wherein the SoC contains a network-on-chip (NoC) ([0025], “Each SoC 101, 102, 103 is an IC comprising a processing system 104, a network-on-chip (NoC) 106, a configuration interconnect 108, and one or more programmable logic regions 110”). Swarbrick further discloses that the NoC contain routing circuitry/logic (Fig. 3, NoC 106 contains routing 208 and NPI 210) that performs packet switching ([0028], “FIG. 3 is a block diagram depicting the NoC 106 of a SoC… network 214 includes NoC packet switches 206 and routing 208 between the NoC packet switches 206. Each NoC packet switch 206 performs switching of NoC packets”) wherein the routing circuitry/logic includes a protocol block (Fig. 7, NPI 210 includes protocol block 410). Swarbrick does not teach translating from a first protocol associated with the NOC to a second protocol associated with an off-die interconnection resource, thus the secondary reference Georgiou was incorporated to disclose an SoC (See Georgiou: Figures 8 and 9, SoC) that contains a protocol converter (Figs. 8 and 9, Protocol converter 550) that translates from a first SOC protocol to a secondary off-chip protocol such as Ethernet or Fiber Channel ([0081], “FIG. 9 illustrates a process flow for protocol conversion of a single packet within the embedded SoC to external protocol interfaces”).
While Applicant argues that Swarbrick already discloses a protocol converter (See Swarbrick: Figure 7, NPI 210 with protocol block 410) and thus it would not have been reasonable to have Swarbrick’s SoC incorporate the single-chip protocol converter of Georgiou (See Georgiou: Figures 8 and 9, Protocol converter 550), the protocol block of Swarbrick is only used for translating between the NoC switch nodes and components using SoC protocols such as AMBA and APB3 (See Swarbrick: [0035], “protocol blocks 410 can also translate the transaction request from the protocol implemented on the NPI 210 to a protocol implemented by the register blocks 212 of the NoC packet switches 206. In some examples, the protocol blocks 410 can translate between NPI Protocol and the Advanced Microcontroller Bus Architecture (AMBA) 3 Advanced Peripheral Bus (APB3) protocol”), whereas Georgiou discloses that the protocol converter is used for off-chip protocols such as for Ethernet or Fibernet (See Georgiou: [0086], “a Fibre Channel protocol packet is sent (originated) from the host system bus 223 and is sent to the SoC protocol converter macro 350 for conversion and transmission to the external Ethernet interface 1G EMAC interface 485”). Georgiou’s protocol converters are located on a single SoC but are used to sending protocols off-chip, which is what the claim 1 limitations require (See Georgiou: Figures 8 and 9 show external protocol interfaces 475 and 485 which are off-chip interconnection resources that use the first/second protocols; i.e. translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource configurable for off-die communication of claim 1). Thus, it would have been obvious that incorporating the off-chip protocol converter of Georgiou into Swarbrick’s protocol block would enable translating from a first protocol of the NoC (such as the AMBA/APB3 protocols of Swarbrick) into a second off-chip protocol such as Ethernet which would enable high-speed network communications with remote SoCs, servers, clients, etc. (See Georgiou: [0007], “existing SANs are often physically remote, sometimes at greater distances, and are often using multiple network architectures. To consolidate existing SANs and to utilize existing WAN and LAN infrastructure there is a need for network protocol conversion”).
Applicant’s arguments with respect to claim 1 limitation “transfer the communication packet to a first router” of newly amended claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
See below for detailed rejection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8, 10-15, and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 9-10, 16, 22, and 25 of U.S. Patent No. 11,789,883. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 5, 9-10, 16, 22, and 25 of U.S. Patent No. 11,789,883 discloses all of the features of claims 1-8, 10-15, and 17-20 of the Instant Application.
As per claims 1-20,
Instant Application
US Patent 11,789,883 (US Application No. 16/103,709)
Claim 1: An integrated circuit device, comprising: a first network on chip (NOC) circuit configurable to: receive a communication packet comprising a set of data; and transfer the communication packet to a first router of the first NOC circuit, wherein the first router comprises a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource configurable for off-die communication.
Claim 1: An integrated circuit device, comprising: a first network on chip (NOC) circuit configurable to: receive a set of data; and transfer the set of data to a first node of the first NOC circuit, wherein the first node is configured to directly transfer the set of data to a second node of a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device, and wherein the first node comprises a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource of a plurality of interconnection resources configurable for off-die communication; and the second NOC circuit configurable to: receive the set of data from the second node, wherein the second node is associated with the interconnection resource of the plurality of interconnection resources, and wherein the second node comprises a second protocol translator configurable to translate the second protocol associated with the interconnection resource into a third protocol associated with the second NOC circuit.
Claim 3: The integrated circuit device of claim 1, wherein the set of data is associated with a communication packet comprising a first location indicative of a first portion of the integrated circuit device and a second location indicative of a second portion of the additional integrated circuit device.
Claim 2: The integrated circuit device of claim 1, wherein the first node is configurable to directly transfer the communication packet to a second router of a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.
Claim 1: An integrated circuit device, comprising: a first network on chip (NOC) circuit configurable to: receive a set of data; and transfer the set of data to a first node of the first NOC circuit, wherein the first node is configured to directly transfer the set of data to a second node of a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device, and wherein the first node comprises a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource of a plurality of interconnection resources configurable for off-die communication; and the second NOC circuit configurable to: receive the set of data from the second node, wherein the second node is associated with the interconnection resource of the plurality of interconnection resources, and wherein the second node comprises a second protocol translator configurable to translate the second protocol associated with the interconnection resource into a third protocol associated with the second NOC circuit.
Claim 3: The integrated circuit device of claim 2, wherein the second router comprises a second protocol translator configurable to translate the second protocol associated with the interconnection resource into a third protocol associated with the second NOC circuit.
Claim 1: An integrated circuit device, comprising: a first network on chip (NOC) circuit configurable to: receive a set of data; and transfer the set of data to a first node of the first NOC circuit, wherein the first node is configured to directly transfer the set of data to a second node of a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device, and wherein the first node comprises a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource of a plurality of interconnection resources configurable for off-die communication; and the second NOC circuit configurable to: receive the set of data from the second node, wherein the second node is associated with the interconnection resource of the plurality of interconnection resources, and wherein the second node comprises a second protocol translator configurable to translate the second protocol associated with the interconnection resource into a third protocol associated with the second NOC circuit.
Claim 4: The integrated circuit device of claim 2, wherein the communication packet comprises data regarding a plurality of routers associated with the first NOC circuit and the second NOC circuit that the set of data is routed through.
Claim 5: The integrated circuit device of claim 3, wherein the communication packet comprises data regarding a plurality of nodes associated with the first NOC circuit and the second NOC circuit that the set of data is routed through.
Claim 5: The integrated circuit device of claim 4, wherein the communication packet comprises a string of virtual functions defining an order in which the set of data is to be processed, wherein the first router is configurable to directly transfer the communication packet to the second router based at least in part on the string of virtual functions.
Claim 9: A system for transferring data between programmable logic devices, comprising: a first programmable logic device, comprising: a first portion associated with a first portion of programmable logic circuitry configurable to process a set of data; and first network on chip (NOC) circuitry configurable to: receive a communication packet and the set of data, wherein the communication packet comprises a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first portion of programmable logic circuitry, a second virtual function identifier associated with a second portion of programmable logic circuitry, and one or more nodes between the first portion of programmable logic circuitry and the second portion of programmable logic circuitry; and transfer the set of data to a first node of the first NOC circuitry based at least in part on the communication packet; and a second programmable logic device comprising: second NOC circuitry configurable to: receive the communication packet and the set of data via a second node; and transfer the set of data from second node associated with a second portion of the second programmable logic device to a second portion of programmable logic circuitry based in part on the communication packet.
Claim 6: The integrated circuit device of claim 1, wherein the communication packet comprises a virtual function identifier corresponding to a portion of the integrated circuit device configured to process the set of data after the first router.
Claim 9: A system for transferring data between programmable logic devices, comprising: a first programmable logic device, comprising: a first portion associated with a first portion of programmable logic circuitry configurable to process a set of data; and first network on chip (NOC) circuitry configurable to: receive a communication packet and the set of data, wherein the communication packet comprises a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first portion of programmable logic circuitry, a second virtual function identifier associated with a second portion of programmable logic circuitry, and one or more nodes between the first portion of programmable logic circuitry and the second portion of programmable logic circuitry; and transfer the set of data to a first node of the first NOC circuitry based at least in part on the communication packet; and a second programmable logic device comprising: second NOC circuitry configurable to: receive the communication packet and the set of data via a second node; and transfer the set of data from second node associated with a second portion of the second programmable logic device to a second portion of programmable logic circuitry based in part on the communication packet.
Claim 7: The integrated circuit device of claim 1, wherein the first router is configurable to transfer the communication packet to a second router of a second NOC circuit of an additional integrated circuit device via a central router, wherein the central router is positioned between the integrated circuit device and the additional integrated circuit device.
Claim 10: The system of claim 9, comprising a central router configurable to transfer the set of data between the first programmable logic device, the second programmable logic device based at least in part on the communication packet, wherein the central router is separate from and located between the first programmable logic device and the second programmable logic device.
Claim 8: The integrated circuit device of claim 1, comprising a second NOC circuit, wherein the communication packet comprises data regarding a plurality of routers associated with the first NOC circuit and the second NOC circuit that the set of data is routed through.
Claim 5: The integrated circuit device of claim 3, wherein the communication packet comprises data regarding a plurality of nodes associated with the first NOC circuit and the second NOC circuit that the set of data is routed through.
Claim 9: The integrated circuit device of claim 1, wherein the first protocol translator is implemented as hard logic associated with the first router.
Claims 1 and 3 do not teach these limitations.
See Below for Obviousness Rejection.
Claim 10: A system, comprising: a first programmable logic device comprising: a first portion associated with a first function block configurable to process a set of data; and first network on chip (NOC) circuitry configurable to: receive a communication packet comprising the set of data and a string of virtual functions, wherein the string of virtual functions comprises a first virtual function identifier associated with the first function block and a second virtual function identifier associated with a second function block; and transfer the communication packet to a first node of the first NOC circuitry based at least in part on the string of virtual functions; and a second programmable logic device comprising: second NOC circuitry configurable to: receive the communication packet via the first node and a second node of the second NOC circuitry; and transfer the set of data to a second portion associated with the second function block to process the set of data.
Claim 9: A system for transferring data between programmable logic devices, comprising: a first programmable logic device, comprising: a first portion associated with a first portion of programmable logic circuitry configurable to process a set of data; and first network on chip (NOC) circuitry configurable to: receive a communication packet and the set of data, wherein the communication packet comprises a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first portion of programmable logic circuitry, a second virtual function identifier associated with a second portion of programmable logic circuitry, and one or more nodes between the first portion of programmable logic circuitry and the second portion of programmable logic circuitry; and transfer the set of data to a first node of the first NOC circuitry based at least in part on the communication packet; and a second programmable logic device comprising: second NOC circuitry configurable to: receive the communication packet and the set of data via a second node; and transfer the set of data from second node associated with a second portion of the second programmable logic device to a second portion of programmable logic circuitry based in part on the communication packet.
Claim 11: The system of claim 10, wherein the communication packet comprises at least one node between the first function block and the second function block.
Claim 9: A system for transferring data between programmable logic devices, comprising: a first programmable logic device, comprising: a first portion associated with a first portion of programmable logic circuitry configurable to process a set of data; and first network on chip (NOC) circuitry configurable to: receive a communication packet and the set of data, wherein the communication packet comprises a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first portion of programmable logic circuitry, a second virtual function identifier associated with a second portion of programmable logic circuitry, and one or more nodes between the first portion of programmable logic circuitry and the second portion of programmable logic circuitry; and transfer the set of data to a first node of the first NOC circuitry based at least in part on the communication packet; and a second programmable logic device comprising: second NOC circuitry configurable to: receive the communication packet and the set of data via a second node; and transfer the set of data from second node associated with a second portion of the second programmable logic device to a second portion of programmable logic circuitry based in part on the communication packet.
Claim 12: The system of claim 10, wherein the string of virtual functions defines an order in which the set of data is to be processed.
Claim 9: A system for transferring data between programmable logic devices, comprising: a first programmable logic device, comprising: a first portion associated with a first portion of programmable logic circuitry configurable to process a set of data; and first network on chip (NOC) circuitry configurable to: receive a communication packet and the set of data, wherein the communication packet comprises a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises a first virtual function identifier associated with the first portion of programmable logic circuitry, a second virtual function identifier associated with a second portion of programmable logic circuitry, and one or more nodes between the first portion of programmable logic circuitry and the second portion of programmable logic circuitry; and transfer the set of data to a first node of the first NOC circuitry based at least in part on the communication packet; and a second programmable logic device comprising: second NOC circuitry configurable to: receive the communication packet and the set of data via a second node; and transfer the set of data from second node associated with a second portion of the second programmable logic device to a second portion of programmable logic circuitry based in part on the communication packet.
Claim 13: The system of claim 10, comprising a central router positioned separate from and located between the first programmable logic device and the second programmable logic device, wherein the central router is configurable to transfer the set of data between the first programmable logic device, the second programmable logic device based at least in part on the string of virtual functions.
Claim 10: The system of claim 9, comprising a central router configurable to transfer the set of data between the first programmable logic device, the second programmable logic device based at least in part on the communication packet, wherein the central router is separate from and located between the first programmable logic device and the second programmable logic device.
Claim 14: The system of claim 13, wherein the central router is configurable to directly transfer the set of data from the first node to the second node without processing the set of data.
Claim 10: The system of claim 9, comprising a central router configurable to transfer the set of data between the first programmable logic device, the second programmable logic device based at least in part on the communication packet, wherein the central router is separate from and located between the first programmable logic device and the second programmable logic device.
Claim 15: The system of claim 10, comprising a central router configurable to receive the communication packet from the second node and directly transfer the communication packet to a third node of third NOC circuitry of a third programmable logic device.
Claim 10: The system of claim 9, comprising a central router configurable to transfer the set of data between the first programmable logic device, the second programmable logic device based at least in part on the communication packet, wherein the central router is separate from and located between the first programmable logic device and the second programmable logic device.
Claim 16: The system of claim 10, wherein the first function block and the second function block are configurable to implement a protocol translator via soft logic.
Claim 9 does not teach these limitations.
See Below for Obviousness Rejection.
Claim 17: A system, comprising: a plurality of programmable logic devices on different respective dies, wherein respective programmable logic devices of the plurality of programmable logic devices comprise: a first accelerator associated with a first virtual function identifier and configurable to process a set of data; and one or more nodes configurable to: receive a communication packet from the first accelerator comprising a string of virtual functions defining order in which the set of data is to be processed and the set of data; and transfer the set of data to a second accelerator of a different programmable logic device of the plurality of programmable logic devices based on the string of virtual functions.
Claim 16: A system for transferring data between programmable logic devices, comprising: a plurality of programmable logic devices on different respective dies, wherein respective programmable logic devices of the plurality of programmable logic devices comprise: at least one accelerator that is configurable to process a set of data, wherein the at least one accelerator is associated with a virtual function identifier and a unique identifier; one or more nodes configurable to: receive a communication packet comprising a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises one or more virtual function identifiers and one or more unique identifiers; and transmit the data to the at least one accelerator of a different one of the plurality of programmable logic devices based on the string of virtual functions; and a semaphore system comprising: a register configurable to be updated in response to the at least one accelerator processing the set of data.
Claim 18: The system of claim 17, comprising a semaphore system comprising a register configurable to be updated in response to the first accelerator processing the set of data.
Claim 16: A system for transferring data between programmable logic devices, comprising: a plurality of programmable logic devices on different respective dies, wherein respective programmable logic devices of the plurality of programmable logic devices comprise: at least one accelerator that is configurable to process a set of data, wherein the at least one accelerator is associated with a virtual function identifier and a unique identifier; one or more nodes configurable to: receive a communication packet comprising a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises one or more virtual function identifiers and one or more unique identifiers; and transmit the data to the at least one accelerator of a different one of the plurality of programmable logic devices based on the string of virtual functions; and a semaphore system comprising: a register configurable to be updated in response to the at least one accelerator processing the set of data.
Claim 19: The system of claim 17, wherein a first node of the one or more nodes comprises a first protocol translator, wherein the first node is configurable to receive the communication packet from the first accelerator, wherein the first protocol translator is configurable to translate the set of data of the communication packet from a first protocol associated with the first accelerator to a second protocol associated with an input/output port of the each respective programmable logic device.
Claim 16: A system for transferring data between programmable logic devices, comprising: a plurality of programmable logic devices on different respective dies, wherein respective programmable logic devices of the plurality of programmable logic devices comprise: at least one accelerator that is configurable to process a set of data, wherein the at least one accelerator is associated with a virtual function identifier and a unique identifier; one or more nodes configurable to: receive a communication packet comprising a string of virtual functions defining an order in which the set of data is to be processed, wherein the string of virtual functions comprises one or more virtual function identifiers and one or more unique identifiers; and transmit the data to the at least one accelerator of a different one of the plurality of programmable logic devices based on the string of virtual functions; and a semaphore system comprising: a register configurable to be updated in response to the at least one accelerator processing the set of data.
Claim 22: The integrated circuit device of claim 1, wherein the first protocol translator of the first node is configurable to translate the second protocol associated with the plurality of interconnection resources into a fourth protocol associated with a third NOC circuit.
Claim 20: The system of claim 17, wherein the string of virtual functions comprises the first virtual function identifier associated with the first accelerator and a second virtual function identifier associated with the second accelerator.
Claim 25: The system of claim 16, wherein the unique identifier is associated with a programmable logic device identifier, wherein the programmable logic device identifier defines on which of the plurality of programmable logic devices the at least one accelerator of the different one of the plurality of programmable logic devices is located, and wherein the virtual function identifier is associated a physical function performed by the at least one accelerator.
Regarding claim 1 of the Instant Application, the features in instant claim 1 are disclosed in claim 1 of US Patent 11,789,883. It is evident from the table that many limitations in instant claim 1 are linguistically comparable to the emphasized limitations in claim 1 of US Patent 11,789,883. For example, instant claim 1 requires a first NOC with a first node comprising a first protocol translator which claim 1 of US Patent 11,789,883 teaches as “a first network on chip (NOC) circuit configurable to: receive a set of data; and transfer the set of data to a first router of the first NOC circuit” and “the first router comprises a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource of a plurality of interconnection resources configurable for off-die communication”. While, claim 1 of US Patent 11,789,883 does not teach a communication packet, claim 3 of US Patent 11,789,883, which is dependent on claim 1 of US Patent 11,789,883, does disclose communication packets.
Regarding claims 5-7 of Instant Application, claims 1 and 3 of US Patent 11,789,883 do not teach the string of virtual functions in claim 5, the virtual function identifiers in claim 6, nor the central router in claim 7 of Instant Application. However, claim 9 of a different system claim branch of US Patent 11,789,883 does teach a string of virtual functions with virtual function identifiers while claim 10 of US Patent 11,789,883 of the system claim branch teaches the central router. It would have been obvious to include the virtual functions and the central router of the system claim branch of claims 9-10 of US Patent 11,789,883 to the integrated circuit device of claims 1 and 3 of US Patent 11,789,883 because the integrated circuit device and the system are part of the same embodiment and the integrated circuit device will necessarily have a system of components, and including the virtual function string and central router will enable the integrated circuit device to efficiently process complex operations.
Regarding claim 19 of the Instant Application, claim 16 of US Patent 11,789,883 does not teach the protocol translator of claim 19 of the Instant Application. However, dependent claim 22 of US Patent 11,789,883 of the integrated circuit device claim branch of independent claim 1 of US Patent 11,789,883 does teach protocol translators. It would have been obvious to include the protocol translators of claim 22 of US Patent 11,789,883 to claim 16 of US Patent 11,789,883 because the system of claim 16 of US Patent 11,789,883 already discloses integrated circuit devices which is part of the same embodiment as the integrated circuit device of claim 22 of US Patent 11,789,883, and including a protocol translator will enable the use of heterogeneous protocols thus providing greater support for different interface types.
Claims 9 and 16 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, and 9 of U.S. Patent No. 11,789,883 in view of Abdelfattah (US 2015/0109024).
Regarding claim 9 of Instant Application, claims 1 and 3 of US Patent 11,789,883 teaches the limitations of claim 1 of Instant Application, which claim 9 of Instant Application depends on. Claims 1 and 3 of US Patent 11,789,883 do not teach “wherein the first protocol translator is implemented as hard logic associated with the first router” of claim 9 of the Instant Application. However, Abdelfattah teaches using hard logic in the logic circuits (Paragraph 0071, protocol translators may either be implemented in soft logic or hard logic within the fabric port). It would have been obvious to modify the integrated circuit device of the Instant Application to incorporate the teachings of Abdelfattah and include hard logic to implement the protocol translator, in order to increase performance and efficiency via the use of fixed hardware (See Abdelfattah: Paragraph 0026).
Regarding claim 16 of Instant Application, claim 9 of US Patent 11,789,883 teaches the limitations of claim 10 of Instant Application, which claim 16 of Instant Application depends on. Claim 9 of US Patent 11,789,883 does not teach “wherein the first function block and the second function block are configurable to implement a protocol translator via soft logic” of claim 16 of the Instant Application. However, Abdelfattah teaches using either hard logic or soft logic in the logic circuits (Paragraph 0071, protocol translators may either be implemented in soft logic or hard logic within the fabric port). It would have been obvious to modify the integrated circuit device of the Instant Application to incorporate the teachings of Abdelfattah and include soft logic to implement the protocol translator, in order to create reconfigurable logic circuitry that is able to be easily adapted to new logical circuit requirements (See Abdelfattah: Paragraph 0026).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick (US 2019/0363717) in view of Georgiou (US 2012/0082171) and further in view of Kumar (US 2016/0156572).
Regarding claim 1, Swarbrick teaches an integrated circuit device (Fig. 2, SoC 102), comprising: a first network on chip (NOC) circuit (Fig. 2, NoC 106; Paragraph 0025, Each SoC 101, 102, 103 is an IC comprising a processing system 104, a network-on-chip (NoC) 106) configured to: receive a communication packet comprising a set of data (Figs. 3 and 4, NoC 106 receives packets from endpoints 302; Paragraph 0028, NoC 106 includes NoC master units (NMUs) 202, NoC slave units (NSUs) 204, a network 214… network 214 includes NoC packet switches 206); and transfer the communication packet to a first node of the first NOC circuit (Fig. 8, Switch nodes 206c-d (i.e. a first node) of NoC 106 (i.e. first NOC circuit) receive communication packets entering NoC 106; Paragraph 0038, NoC 106 includes routing 208 and NoC packet switches 206 (boxes labeled with an “x”) at various intersections… NoC packet switches 206 are capable of being configured to connect and direct communications), wherein the first node is associated with an interconnection resource configurable for off-die communication (Fig. 8, Switch node 206c-d transfers packets to external SoCs 101 & 103 which contains other NoCs (i.e. the external NoCs are an interconnection resource); Paragraph 0050, permit communication… via the interconnected NoCs of the SoCs 101, 102, 103 for communications between SoCs 101, 102, 103).
Swarbrick does not teach the integrated circuit device, comprising: wherein the first node comprises a first protocol translator configurable to translate a first protocol associated with the first NOC circuit into a second protocol associated with an interconnection resource configurable for off-die communication.
Georgiou teaches the integrated circuit device (Fig. 9, System-on-chip SoC 400; Paragraph 0053, protocol converter on a single chip), comprising: wherein the first node (Figs. 8 & 9, Processing cluster 200) comprises a first protocol translator (Figs. 8 & 9, Processing cluster 200 contains processor proc. 0 which receives external packets and converts them to a different protocol; Paragraph 0082, protocol conversion code is performed on the processing elements… processes is mapped to one of the macro's processing elements labeled Proc. 0, Proc. 1, Proc. 2) configurable to translate a first protocol (Fig. 9, Protocol #1) associated with the first NOC circuit (Fig. 9, Circuit 550 contains crossbar switch 64 provides switching for packets in protocol #1 and thus is an NOC circuit) into a second protocol (Fig. 9, Protocol #2; Paragraph 0081, A to B packet conversion is shown with a packet according to a first protocol, e.g., where 1G Ethernet packets are received at the SoC external protocol chip, macro or EMAC (external Ethernet I/O) interface 485 and are forwarded to the converter) associated with an interconnection resource configurable for off-die communication (Fig. 9, Converted packets to protocol #2 are output externally off-chip to external networks; Paragraph 0084, After protocol conversion of packet "A" to "B", the packet is transferred… transfers the converted packet through the cross bar switch, Fibre Channel Interface, and finally external I/O interface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick’s integrated circuit device to incorporate the teachings of Georgiou and include nodes with protocol translators to the NoC of Swarbrick for translation of SoC protocols into external protocols.
One of ordinary skill in the art would be motivated to make the modifications in order to provide integration of the SoC within a wide range of network architectures while being able to accommodate different and evolving protocols in an efficient manner (See Georgiou: Paragraphs 0006 and 0007).
Neither Swarbrick nor Georgiou teaches the integrated circuit device with a first router of the first NOC circuit, wherein the first router comprises the first protocol translator.
Kumar teaches the integrated circuit device with a first router (Fig. 5(b) Bridge 503 is a multiplexer switch that routes data between NoC agent 502 and NoC layers 500-1 and 500-2) of the first NOC circuit (Fig. 5(b), Bridges are part of the NoC 500; See Paragraph 0047), wherein the first router comprises the first protocol translator (Fig. 5(b), Bridge 503 performs protocol translation; Paragraph 0051, Bridge 503 can be used to translate messages from the protocol associated with function F.sub.1 of the NoC agent 502 to protocol(s) of regular NoC agents such as 501-a, 501-b, and 501-c, and visa-versa).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou’s integrated circuit device to incorporate the teachings of Kumar and include bridge routers that perform the protocol translation of the processor of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to implement NoC networks that are spatially efficient (See Kumar: Paragraph 0027) by incorporating protocol translation bridges/routers into the NoC (See Kumar: Paragraphs 0022-0023).
Regarding claim 2, the combination of Swarbrick/Georgiou/Kumar teaches the integrated circuit device of claim 1. Swarbrick teaches the integrated circuit device comprising wherein the first node is configurable to directly transfer the communication packet to a second node of a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device (Fig. 8, Switch nodes 206c-d (i.e. the first node) can transfer packets to separate nodes 206b (i.e. second node) of a second NoC (i.e. second NOC circuit) on second SoC 101 (i.e. additional integrated circuit device); Paragraph 0050, permit communication… via the interconnected NoCs of the SoCs 101, 102, 103 for communications between SoCs 101, 102, 103).
Kumar teaches the integrated circuit device including a first router (Fig. 5(b) Bridge 503 is a multiplexer switch that routes data between NoC agent 502 and NoC layers 500-1 and 500-2) and a second router (Fig. 7, Multiple bridges 714 and 715).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou’s integrated circuit device to incorporate the teachings of Kumar and include bridge routers that perform the protocol translation of the processor of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to implement NoC networks that are spatially efficient (See Kumar: Paragraph 0027) by incorporating protocol translation bridges/routers into the NoC (See Kumar: Paragraphs 0022-0023).
Regarding claim 4, the combination of Swarbrick/Georgiou/Kumar teaches the integrated circuit device of claim 2. Swarbrick further teaches the integrated circuit device comprising wherein the communication packet comprises data regarding a plurality of nodes (Paragraph 0043, chip identification can be appended to addresses of the memory-mapped packets, and the NoC packet switch 206b can direct packets based on the chip identification) associated with the first NOC circuit and the second NOC circuit that the first set of data is routed through (Paragraph 0043, PMC 402 of the SoC 101 can determine addresses of register blocks 212 of the NoC packet switch 206a, 206b for programming routing tables of the NoC packet switch 206a, 206b… routing tables of the NoC packet switch 206b can direct memory-mapped packets through different sides of the NoC packet switch 206b based on an address in the respective memory-mapped packet).
Kumar teaches the integrated circuit device including routers (Fig. 7, Bridges 714 and 715).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou’s integrated circuit device to incorporate the teachings of Kumar and include bridge routers that perform the protocol translation of the processor of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to implement NoC networks that are spatially efficient (See Kumar: Paragraph 0027) by incorporating protocol translation bridges/routers into the NoC (See Kumar: Paragraphs 0022-0023).
Regarding claim 8, the combination of Swarbrick/Georgiou/Kumar teaches the integrated circuit device of claim 1. Swarbrick further teaches the integrated circuit device comprising a second NOC circuit (Fig. 8, Second NOC on SoC 101), wherein the communication packet comprises data regarding a plurality of nodes (Paragraph 0043, chip identification can be appended to addresses of the memory-mapped packets, and the NoC packet switch 206b can direct packets based on the chip identification) associated with the first NOC circuit and the second NOC circuit that the first set of data is routed through (Paragraph 0043, PMC 402 of the SoC 101 can determine addresses of register blocks 212 of the NoC packet switch 206a, 206b for programming routing tables of the NoC packet switch 206a, 206b… routing tables of the NoC packet switch 206b can direct memory-mapped packets through different sides of the NoC packet switch 206b based on an address in the respective memory-mapped packet).
Kumar teaches the integrated circuit device including routers (Fig. 7, Bridges 714 and 715).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou’s integrated circuit device to incorporate the teachings of Kumar and include bridge routers that perform the protocol translation of the processor of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to implement NoC networks that are spatially efficient (See Kumar: Paragraph 0027) by incorporating protocol translation bridges/routers into the NoC (See Kumar: Paragraphs 0022-0023).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick (US 2019/0363717) in view of Georgiou (US 2012/0082171) in view of Kumar (US 2016/0156572) and further in view of Srinivasan (US 2011/0134915).
Regarding claim 6, the combination of Swarbrick/Georgiou/Kumar teaches the integrated circuit device of claim 1.
Kumar teaches the integrated circuit device including routers (Fig. 7, Bridges 714 and 715).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou’s integrated circuit device to incorporate the teachings of Kumar and include bridge routers that perform the protocol translation of the processor of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to implement NoC networks that are spatially efficient (See Kumar: Paragraph 0027) by incorporating protocol translation bridges/routers into the NoC (See Kumar: Paragraphs 0022-0023).
The combination of Swarbrick/Georgiou/Kumar does not teach the integrated circuit device comprising wherein the communication packet comprises a virtual function identifier corresponding to a portion of the integrated circuit device configured to process the set of data after the first node.
Srinivasan teaches the integrated circuit device (Fig. 1, Chip with virtual function routing; Paragraph 0025, network interface device includes one or more high-bandwidth communication ports shared among multiple physical and/or virtual functions, an may be embodied within a single chip) comprising wherein the communication packet comprises a virtual function identifier corresponding to a portion of the integrated circuit device configured to process the set of data after the first node (Fig. 3, Packets include virtual function identifier of destination to be processed at; Paragraph 0069, identify a destination function (physical or virtual) for the packet and/or one or more DMA engines that may be used to transfer the packet to that function).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou/Kumar’s integrated circuit device to incorporate the teachings of Srinivasan and include virtualization of the SoC of Swarbrick where packets can be routed based on virtual function identifiers to virtualized peripherals.
One of ordinary skill in the art would be motivated to make the modifications in order to increase the number of I/O devices available to be used (See Srinivasan: Paragraphs 0002 and 0003).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick (US 2019/0363717) in view of Georgiou (US 2012/0082171) in view of Kumar (US 2016/0156572) and further in view of Lee (US 2012/0147567).
Regarding claim 7, the combination of Swarbrick/Georgiou/Kumar teaches the integrated circuit device of claim 1. Swarbrick teaches the integrated circuit device comprising wherein the first node is configurable to transfer the communication packet to a second node of a second NOC circuit of an additional integrated circuit device (Fig. 8, Switch nodes 206c-d can transfer packets to separate nodes 206b of a second NoC on second SoC 101; Paragraph 0050, permit communication… via the interconnected NoCs of the SoCs 101, 102, 103 for communications between SoCs 101, 102, 103).
Kumar teaches the integrated circuit device including routers (Fig. 7, Bridges 714 and 715).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou’s integrated circuit device to incorporate the teachings of Kumar and include bridge routers that perform the protocol translation of the processor of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to implement NoC networks that are spatially efficient (See Kumar: Paragraph 0027) by incorporating protocol translation bridges/routers into the NoC (See Kumar: Paragraphs 0022-0023).
The combination of Swarbrick/Georgiou/Kumar does not teach the integrated circuit device comprising wherein the integrated circuit device is configurable to transfer the communication packet to an additional integrated circuit device via a central router, wherein the central router is positioned between the integrated circuit device and the additional integrated circuit device.
Lee teaches the integrated circuit device comprising wherein the integrated circuit device is configurable to transfer the communication packet to an additional integrated circuit device via a central router (Fig. 2, Central router 24 routes packets from processor die 1 to processor die 2; Paragraph 0017, interactions between networking die 24 and functional elements 26 are also illustrated. Networking die 24 includes a plurality of switches/routers 32, which are configured to receive data packets 36 from each other), wherein the central router is positioned between the integrated circuit device and the additional integrated circuit device (Fig. 2, Central router 24 is between processor dies).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou/Kumar’s integrated circuit device to incorporate the teachings of Lee and include a central router between the SoC’s of Swarbrick.
One of ordinary skill in the art would be motivated to make the modifications in order to support different circuits dies using a wide range of heterogeneous interface and protocol types (See Lee: Paragraph 0017).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Swarbrick (US 2019/0363717) in view of Georgiou (US 2012/0082171) in view of Kumar (US 2016/0156572) and further in view of Abdelfattah (US 2015/0109024).
Regarding claim 9, the combination of Swarbrick/Georgiou/Kumar teaches the integrated circuit device of claim 1.
Kumar teaches the integrated circuit device including routers (Fig. 7, Bridges 714 and 715).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou’s integrated circuit device to incorporate the teachings of Kumar and include bridge routers that perform the protocol translation of the processor of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to implement NoC networks that are spatially efficient (See Kumar: Paragraph 0027) by incorporating protocol translation bridges/routers into the NoC (See Kumar: Paragraphs 0022-0023).
The combination of Swarbrick/Georgiou/Kumar does not teach the integrated circuit device comprising wherein the first protocol translator is implemented as hard logic associated with the first node.
Abdelfattah teaches the integrated circuit device comprising wherein the circuitry is implemented as hard logic associated with the first node (Paragraph 0071, protocol translators may either be implemented in soft logic or hard logic within the fabric port).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Swarbrick/Georgiou/Kumar’s integrated circuit device to incorporate the teachings of Abdelfattah and include hard logic to implement the protocol translator of Georgiou.
One of ordinary skill in the art would be motivated to make the modifications in order to improve performance and efficiency via the use of fixed hardware (See Abdelfattah: Paragraph 0026).
Allowable Subject Matter
Claims 3 and 5 would be allowable if rewritten to overcome the rejection(s) Double Patenting, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 10-20 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting, set forth in this Office action.
Regarding claim 10, none of the cited references either alone or in combination teach a system, comprising: a first programmable logic device comprising: a first portion associated with a first function block configurable to process a set of data; and first network on chip (NOC) circuitry configurable to: receive a communication packet comprising the set of data and a string of virtual functions, wherein the string of virtual functions comprises a first virtual function identifier associated with the first function block and a second virtual function identifier associated with a second function block; and transfer the communication packet to a first node of the first NOC circuitry based at least in part on the string of virtual functions; and a second programmable logic device comprising: second NOC circuitry configurable to: receive the communication packet via the first node and a second node of the second NOC circuitry; and transfer the set of data to a second portion associated with the second function block to process the set of data.
Regarding claim 17, none of the cited references either alone or in combination teach a system, comprising: a plurality of programmable logic devices on different respective dies, wherein respective programmable logic devices of the plurality of programmable logic devices comprise: a first accelerator associated with a first virtual function identifier and configurable to process a set of data; and one or more nodes configurable to: receive a communication packet from the first accelerator comprising a string of virtual functions defining order in which the set of data is to be processed and the set of data; and transfer the set of data to a second accelerator of a different programmable logic device of the plurality of programmable logic devices based on the string of virtual functions.
Claims 11-16 and 18-20 are considered allowable subject matter because they are dependent on claims 10 and 17.
US PGPUB 2016/0321094 to Rabi discloses a plurality of virtual function hardware accelerators that process data sequentially. No mention of a hardware accelerate of a different programmable logic device is present.
US PGPUB 2008/0244126 to Hundley discloses hardware accelerators performing processing on data. No mention of a hardware accelerator of a different programmable logic device nor a communication packet containing a string of virtual function identifiers is present.
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2015/0256356 discloses that bridges and routers are the same (See Paragraph 0035, The switch device can also be referred to as a bridge or router device).
US PGPUB 2018/0011811 discloses that bridges provide routing (See Paragraph 0030, The routing function 800 can include a PCIe switch 820 (also referred to as a bridge) to provide routing).
US PGPUB 2016/0210261 to Oprea discloses that bridges routes data and therefore are routers (See Paragraph 0003: A network switch is also commonly referred to as a multi-port network bridge that processes and routes data).
US PGPUB 2009/0245257 discloses a router agent block node with a network interface controller capable of performing protocol translation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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