Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-24 of Group I in the reply filed on December 11, 2025 is acknowledged.
Claims 3, 5-8, 11, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 11, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-16, 21, 22, and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by XU (US 2022/0255548 A1, hereinafter referred to as XU).
Regarding claim 12, XU discloses an apparatus (Figs. 1, 2), comprising:
a full unit interval (UI) transmit driver (20, 30, Fig. 1; it is noted that “the PTO applies to the verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art,” In re Morris, 44 USPQ2d 1023, 1027 (Fed. Cir. 1997).) including an input coupled to a signal input (Data_In_Pos); and
a mid-sub-UI boost driver (41, Fig. 1; Fig. 2; it is noted that “the PTO applies to the verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art,” In re Morris, 44 USPQ2d 1023, 1027 (Fed. Cir. 1997).) including an input coupled to the signal input (Data_In_Pos) and an output coupled to an output (DQ) of the full UI transmit driver.
Regarding claim 13, XU discloses the apparatus of claim 12, wherein the mid-sub-UI boost driver (41, Fig. 1; Fig. 2) comprises: a boost rising edge initiating circuit (S22, Fig. 2) including an input (Data_In_Pos) coupled to the signal input; and/or a boost falling edge initiating circuit (S11, S12, Fig. 2) including an input (Data_In_Pos) coupled to the signal input; and a transmit boost driver (S3) including an input coupled to outputs of the boost rising edge initiating circuit and the boost falling edge initiating circuit, respectively (see Fig. 2).
Regarding claim 14, XU discloses the apparatus of claim 13, wherein the boost rising edge initiating circuit (S22, Fig. 2) comprises a delay circuit (para 0043).
Regarding claim 15, XU discloses the apparatus of claim 13, wherein the boost falling edge initiating circuit (S11, S12, Fig. 2) comprises a delay circuit (S12, para 0043) cascaded with an inverting circuit (S11).
Regarding claim 16, XU discloses the apparatus of claim 12, wherein the mid-sub-UI boost driver (41, Fig. 1; Fig. 2) comprises: a boost pulse initiating circuit (S11, S12, S22) including an input (Data_In_Pos) coupled to the signal input; and a transmit boost driver (S3) including an input coupled to an output of the boost pulse initiating circuit (see Fig. 2).
Regarding claim 21, XU discloses an apparatus, comprising:
a full-UI transmit driver (20, 30, Fig. 1; it is noted that “the PTO applies to the verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art,” In re Morris, 44 USPQ2d 1023, 1027 (Fed. Cir. 1997).) configured to generate a first portion of an output transmit signal (DQ) based on an input transmit signal (Data_In_Pos, Fig. 1; para 0033), wherein the first portion of the output transmit signal (DQ) includes a first set of pulses each spanning a unit interval (UI) (see para 0050, Fig. 3); and
a mid-sub-UI boost driver (41, Fig. 1; Fig. 2; it is noted that “the PTO applies to the verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art,” In re Morris, 44 USPQ2d 1023, 1027 (Fed. Cir. 1997).) configured to generate a second portion of the output transmit signal (DQ) based on the input transmit signal (Data_In_Pos), wherein the second portion of the output transmit signal (DQ) includes a second set of pulses each spanning a middle sub-interval of the UI (see paragraphs 0045, 0046, 0050; Figs. 1, 3).
Regarding claim 22, XU discloses the apparatus of claim 21, wherein the mid-sub-UI boost driver (41, Fig. 1; Fig. 2) comprises: a first delay circuit (S22, Fig. 2) configured to generate a rising edge at a first delay (para 0043) after a rising edge of the input transmit signal per each of the second set of pulses (Fig. 3); a second delay circuit (S11, S12, Fig. 2) configured to generate a falling edge at a second delay (para 0043) after the rising edge of the input transmit signal per each of the second set of pulses (Fig. 3); and a boost driver (S3) configured to generate each of the second set of pulses based on the rising and falling edges generated by the first and second delay circuits, respectively (Fig. 3; paragraphs 0045, 0046, 0050).
Regarding claim 24, XU discloses the apparatus of claim 22, wherein the boost driver (S3) includes an output (PU_Boost) coupled to an output (DQ) of the full-UI transmit driver.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 9, 10, 17, 18, 20, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over XU (US 2022/0255548 A1, hereinafter referred to as XU).
Regarding claim 1, XU discloses an apparatus (Figs. 1, 2), comprising:
a first transmit driver (20, 30) including an input (10) coupled to a signal input (Data_In_Pos, Fig. 1; para 0032));
a first delay circuit (S22) including an input coupled to the signal input (Data_In_Pos, Fig. 2; paragraphs 0041-0042);
a second delay circuit (S12) including an input coupled to the signal input (Data_In_Pos) or an output of the first delay circuit;
an inverting circuit (S11)
a logic gate (S3) including inputs coupled to outputs of the first delay circuit (S22)
a second transmit driver (51, 52) including an input (PU_Boost) coupled to an output of the logic gate (S3), and an output coupled to an output (DQ) of the first transmit driver.
XU does not explicitly disclose that the inverting circuit (S11) including an input coupled to an output of the second delay circuit; and the logic gate (S3) including input coupled to output of the inverting circuit (S11).
However, it is well kwon in the art that placing the inverting circuit before or after the delay circuit has the same logical effect.
Therefore, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to place the inverting circuit (S11) of XU between the output of the delay (S12) and the input of the logic gate (S3) since the inverting circuit's position, before or after the delay circuit, does not change the outcome. Such modification would have been a mere an obvious engineering variation well within the ordinary skill in the art.
Regarding claim 2, the modified XU discloses the apparatus of claim 1, wherein the logic gate comprises an AND function (“AND circuit S3”, para 0041), an AND gate, or an exclusive-NOR (XNOR) gate.
Regarding claim 4, the modified XU discloses the apparatus of claim 1, wherein the input of the second delay circuit (S12) is coupled to the input of the first delay circuit (S22).
Regarding claim 9, the modified XU discloses the apparatus of claim 1, further comprising: an upper supply voltage rail (see supply voltage coupled to 20 and 51, Fig. 1) coupled to the first and second transmit drivers; and a lower supply voltage rail (See ground coupled to 30, 52, Fig. 1) coupled to the first and second transmit drivers.
Regarding claim 10, the modified XU discloses the apparatus of claim 1, further comprising: a first upper supply voltage rail (see supply voltage coupled to 20, Fig. 1) coupled to the first transmit driver (20, 30, Fig. 1); a second upper supply voltage rail (see supply voltage coupled to 51, Fig. 1) coupled to the second transmit driver (51, 52, Fig. 1); and a lower supply voltage rail (See ground coupled to 30, 52, Fig. 1) coupled to the first and second transmit drivers.
Claim 17 is essentially the same as claim 1 and is similarly rejected as claim 1 as discussed above.
Regarding claim 18, the modified XU discloses the apparatus of claim 17, wherein the logic gate comprises an AND function (“AND circuit S3”, para 0041), an AND gate, or an exclusive-NOR (XNOR) gate.
Regarding claim 20, the modified XU discloses the apparatus of claim 17, wherein the input of the second delay circuit (S12) is coupled to the input of the first delay circuit (S22, Fig. 2).
Claim 23 is essentially the same as claim 1 and is similarly rejected as claim 1 as discussed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. GU (US 2022/0045675 A1) discloses driving circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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/DANIEL D CHANG/Primary Examiner, Art Unit 2844