DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/29/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakajima et al. (US 7,126,442 B2).
Regarding claim 1, Nakajima et al. disclose a phase shifter circuit (figure 5) comprising: a first cell (unit element a) comprising a first inductor (L51a), a first capacitor (C51a), a second inductor (L52a), and a second capacitor (C52a); a second cell (unit element b) coupled to the first cell, the second cell comprising a third inductor (L51b), a third capacitor (C51b), a fourth inductor (L52b), and a fourth capacitor (C52b) (column 12, lines 9-48).
Regarding claim 7, Nakajima et al. disclose the phase shifter circuit of claim 1, wherein an output terminal of the first cell (output from L52a of cell a) is coupled to an input terminal of the second cell (input of C51b of cell b) (see figure 5).
Regarding claim 8, Nakajima et al. disclose the phase shifter circuit of claim 1, comprising a third cell (unit element n) coupled to the second cell, the third cell comprising a fifth inductor (L51n), a fifth capacitor (C51n), a sixth inductor (L52n), and a sixth capacitor (C52n) (column 12, lines 9-48).
Claim(s) 1, 3, 4 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saiki et al. (WO 2023135663 A1 – See English Text).
Regarding claim 1, Saiki et al. (figure 11) disclose a phase shifter circuit comprising: a first cell (section A) comprising a first inductor (3A), a first capacitor (1A), a second inductor (7A), and a second capacitor (4A); a second cell (section B) coupled to the first cell, the second cell comprising a third inductor (3B), a third capacitor (1B), a fourth inductor (7B), and a fourth capacitor (4B) (see Embodiment 7, page 12, paragraph 7 – page 13, paragraph 7).
Regarding claim 3, Saiki et al. disclose the phase shifter circuit of claim 1, wherein the first inductor (3A), the first capacitor (1A), or both are coupled to an input terminal (IO1A) and an output terminal (IO2A) of the first cell, the second inductor (7A), the second capacitor (4A), or both are coupled to the output terminal (IO2A) and a ground terminal (G) (see figure 11).
Regarding claim 4, Saiki et al. disclose the phase shifter circuit of claim 1, wherein the third inductor (3B), the third capacitor (1B), or both are coupled to an input terminal (IO1B) and an output terminal (IO2B) of the second cell, the fourth inductor (7B), the fourth capacitor (4B), or both are coupled to the output terminal (IO2B) and a ground terminal (G) (see figure 11).
Regarding claim 7, Saiki et al. disclose the phase shifter circuit of claim 1, wherein an output terminal of the first cell (output from IO2A) is coupled to an input terminal of the second cell (input of IO1B) (see figure 11).
Claim(s) 1, 2 and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wallace et al. (US 6,137,377 A).
Regarding claim 1, Wallace et al. (figure 11) disclose a phase shifter circuit comprising: a first cell (section 1804) comprising a first inductor (L6), a first capacitor (C4), a second inductor (L7), and a second capacitor (C9); a second cell (section 1806) coupled to the first cell, the second cell comprising a third inductor (L9), a third capacitor (C11), a fourth inductor (L14), and a fourth capacitor (C13) (column 8, line 12 – column 10, line 15).
Regarding claim 2, Wallace et al. (figure 11) disclose the phase shifter circuit of claim 1, comprising a first switch (transistor T5) coupled to the first inductor (L6), a second switch (T4) coupled to the first capacitor (C4), a third switch (T6) coupled to the second inductor (L7), and a fourth switch (T7) coupled to the second capacitor (C9) (column 8, line 23 – column 9, line 58, the transistors T4-T7 act as switches depending on control line 532b).
Regarding claim 5, Wallace et al. disclose the phase shifter circuit of claim 1, wherein the first cell is configured to shift a phase of a signal by a first fractional phase shift value (180o) and the second cell is configured to shift the phase of the signal by a second fractional phase shift value (90o) (column 8, lines 12-22).
Regarding claim 6, Wallace et al. disclose the phase shifter circuit of claim 5, wherein the phase shifter circuit is configured to output the signal with a phase shift value based on the first fractional phase shift value (180o) and the second fractional phase shift value (90o) (column 8, lines 12-22).
Regarding claim 7, Wallace et al. disclose the phase shifter circuit of claim 1, wherein an output terminal of the first cell (output from 1804) is coupled to an input terminal of the second cell (input of 1806) (see figure 11).
Regarding claim 8, Wallace et al. disclose the phase shifter circuit of claim 1, comprising a third cell (section 1808) coupled to the second cell (1806), the third cell comprising a fifth inductor (upper L11), a fifth capacitor (C14), a sixth inductor (lower L11), and a sixth capacitor (C16) (see figure 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nakajima et al. in view of Liu et al. (US 2024/0113406 A1).
Regarding claim 9, Nakajima et al. disclose the phase shifter circuit of claim 1. Nakajima et al. do not explicitly disclose the phase shifter circuit above comprising an inverter block configured to invert a signal. However, Liu et al. disclose a phase shifter circuit comprising an inverter block (inverter) (paragraphs [0007], [0071]-[0075]). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claim invention to adapt the inverter block of Liu et al. to the phase shifter circuit of Nakajima et al. for performing in-phase or inverting phase shifting as suggested by Liu et al. (paragraphs [0072] and [0078]).
Claim(s) 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Brown, JR. et al. (US 2023/0048770 A1) in view of Wallace et al.
Regarding claim 10, Brown, JR. et al. (figure 2) disclose an electronic device (200) comprising: a first antenna (first top antenna of antenna array 248); a second antenna (second top antenna of antenna array 248); a first phase shifter circuit (first top phase shifter 283) coupled to the first antenna (through top phased array element 287); and a second phase shifter circuit (second top phase shifter 283) coupled to the second antenna (through second top phased array element 287) (paragraph [0032]-[0039]). Brown, JR. et al. do not explicitly disclose the first phase shifter circuit comprising a first cell and a second cell, the first phase shifter circuit configured to output a first signal with a first phase shift value based on a first fractional phase shift value of the first cell and a second fractional phase shift value of the second cell; and the second phase shifter circuit comprising a third cell and a fourth cell, the second phase shifter circuit configured to output a second signal with a second phase shift value based on a third fractional phase shift value of the third cell and a fourth fractional phase shift value of the fourth cell. However, Wallace et al. disclose a phase shifter circuit (figure 11) comprising a first cell (section 1802) and a second cell (section 1804) the phase shifter circuit configured to output a first signal with a first phase shift value based on a first fractional phase shift value (22.5o) of the first cell and a second fractional phase shift value of the second cell (180o) or a third cell (section 1806) and a fourth cell (section 1808), the phase shifter circuit configured to output a second signal with a second phase shift value based on a third fractional phase shift value of the third cell (90o) and a fourth fractional phase shift value of the fourth cell (45o) (column 8, lines 12-28). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claim invention to adapt the phase shifter of Wallace et al. to the first and second phase shifters of the electronic device of Brown, JR. et al. as a system design preference for adjusting the phase of the signal as desired.
Regarding claim 11, Brown, JR. et al. and Wallace et al. disclose the electronic device of claim 10 above. In addition, Brown, JR. et al. disclose wherein the first phase shifter circuit is configured to receive the first signal in-phase with the second phase shifter circuit receiving the second signal (since both phase shifters receive the same signal from Mixer 276, see figure 2).
Regarding claim 12, Brown, JR. et al. and Wallace et al. disclose the electronic device of claim 10 above. In addition, Brown, JR. et al. disclose wherein the first antenna and the second antenna are configured to form a desired beam by outputting the first signal and the second signal (through top and second top antennas of antenna array 248, see figure 2).
Regarding claim 13, Brown, JR. et al. and Wallace et al. disclose the electronic device of claim 10 above. In addition, Brown, JR. et al. disclose wherein the first phase shifter circuit is configured to receive the first signal via the first antenna and the second phase shifter circuit is configured to receive the second signal via the second antenna (in receive direction, signals from top and second top antennas to top and second top phase shifters, see figure 2).
Regarding claim 14, Brown, JR. et al. and Wallace et al. disclose the electronic device of claim 13 above. In addition, Brown, JR. et al. disclose wherein the first phase shifter circuit is inherently configured to receive the first signal in-phase or out-of-phase compared to the second phase shifter circuit receiving the second signal, and output the first signal in-phase with the second phase shifter circuit outputting the second signal in order to properly process the receiving signals (from antenna array 248, see figure 2).
Regarding claim 15, Brown, JR. et al. (figure 2) disclose a transceiver (200) comprising: a first phase shifter circuit (top phase shifter 283); and a second phase shifter circuit (second top phase shifter 283) (paragraphs [0032]-[0037]). Brown, JR. et al. do not explicitly disclose the first phase shifter circuit comprising a first cell being coupled to a second cell, the first cell being configured to shift a phase of a signal by a first phase shift value and a second phase shift value, the second cell being configured to shift the phase of the signal by the first phase shift value and the second phase shift value; and the second phase shifter circuit comprising a third cell being coupled to a fourth cell, the third cell being configured to shift the phase of the signal by the first phase shift value and the second phase shift value, and the fourth cell being configured to shift the phase of the signal by the first phase shift value and the second phase shift value. However, Wallace et al. disclose a phase shifter circuit (figure 11) comprising a first cell (section 1802) being coupled to a second cell (section 1804), the first cell being configured to shift a phase of a signal by a first phase shift value and a second phase shift value (base on the control line 532a), the second cell being configured to shift the phase of the signal by the first phase shift value and the second phase shift value (based on the control line 532b); or the phase shifter circuit comprising a third cell (section 1806) being coupled to a fourth cell (1808), the third cell being configured to shift the phase of the signal by the first phase shift value and the second phase shift value (based on the control line 532c), and the fourth cell being configured to shift the phase of the signal by the first phase shift value and the second phase shift value (based on the control line 532d)(column 8, line 12 – column 9, line 67). Therefore, it would have been obvious for one having ordinary skill in the art before the effective filing date of the claim invention to adapt the phase shifter of Wallace et al. to the first and second phase shifters of the transceiver of Brown, JR. et al. as a system design preference for adjusting the phase of the signal as desired.
Allowable Subject Matter
Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 16 and 17, Brown, JR. et al. and Wallace et al. disclose the transceiver of claim 15. However, Brown, JR. et al. and Wallace et al. fail to further disclose the transceiver above wherein the first phase shift value corresponds to a positive fractional phase shift value and the second phase shift value corresponds to a negative fractional phase shift value.
Regarding claims 18-20, Brown, JR. et al. and Wallace et al. disclose the transceiver of claim 15. However, Brown, JR. et al. and Wallace et al. fail to further disclose the transceiver above wherein the first cell, the second cell, the third cell, and the fourth cell each include circuitry to form an inductor-capacitor circuit to shift the phase of the signal by the first phase shift value based on receiving a first control signal and form a capacitor-inductor circuit to shift the phase of the signal by the second phase shift value based on receiving a second control signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Reiha (US 9,450,557 B2) disclose methods and apparatus include a transmission line comprising a plurality of sections; and a plurality of switches coupled to the plurality of sections, wherein the plurality of switches activate one or more of the plurality of sections to vary a phase shift provided by the transmission line, and wherein the plurality of switches configure a type of coupling between one or more of the sections to vary an impedance provided by the transmission line.
Shrivastava et al. (US 2018/021259 A1) teach a phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing; one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOCHIEN B VUONG whose telephone number is (571)272-7902. The examiner can normally be reached 10:00-06:00PM M-F.
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/QUOCHIEN B VUONG/Primary Examiner, Art Unit 2645