DETAILED ACTION
This office action is in response to amendment/arguments filed on 8/25/2026.
Claim 15 is amended.
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 7 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nalluri (US 20140300614, prior art part of IDS dated 10/4/2024, hereinafter Nalluri).
As per claim 1, Nalluri discloses: A graphics processor comprising: a memory;
a graphics engine coupled with the memory and configured to perform graphics operations according to commands received via a graphics engine command queue; (Nalluri [0011]: “a mechanism in GPU hardware, such as a command streamer to evaluate the conditions of predicate registers, such as command buffers, and skip the subsequent depended command buffers without software intervention.”)
and a copy engine to perform copy operations according to commands received via a copy engine command queue, the copy engine configured to execute a command from the copy engine command queue to update a predication value in the memory, wherein the graphics engine, based on the predication value, is configured to bypass execution of a first plurality of commands in the graphics engine command queue and execute a second plurality of commands in the graphics engine command queue. (Nalluri [0012]: “a "Predication Enable" control field is provided in a command executed before the start of the execution of a command sequence, such as a sequence loaded into a batch buffer. In the described example, this is referred to as a "MI_BATCH_BUFFER_START" command, where MI refers to memory interface. The control field, such as a flag, when parsed by a command streamer, indicates that the MI_BATCH.sub.-- BUFFER_START command should be skipped based on a value in a predicate register. In the described example, this is referred to as a "PR_RESULT.sub.--1" register. In the described embodiment, there is also a "PR_RESULT.sub.--0" register that is used to predicate a 3DPRIMITIVE command. This command is used to trigger rendering in a 3D engine 216 of the GPU 201 shown in FIG. 4.”; [0013]: “Command buffers, such as a particular MI_BATCH_BUFFER_START command can be skipped conditionally depending upon a predicate register value, such as the PR_RESULT.sub.--1 value. A predication control field, such as a PREDICATION ENABLE field in the MI_BATCH_BUFFER_START command indicates whether the hardware is to use predication to determine whether to skip the command. When predication is enabled, then the hardware is to either skip or not skip the batch buffer depending on the PR_RESULT.sub.--1 value. When predication is not enabled, then the command is executed without reference to the predication register.”; Figure 1 and [0030]: if prediction value is not set, skip and loop back to new received batch buffer execution command.)
As per claim 2, Nalluri further discloses:
The graphics processor of claim 1, wherein the graphics engine includes predication circuitry to enable predication for a region of a command buffer. (Nalluri [0011])
As per claim 3, Nalluri further discloses:
The graphics processor of claim 2, wherein the predication circuitry is configured to: load a first command buffer including the first plurality of commands; detect a first predicated command region in the first command buffer, the first predicated command region including the first plurality of commands; perform a first read of the predication value from the memory; and bypass the execution of the first plurality of commands based on the predication value returned by the first read. (Nalluri [0012] – [0013])
As per claim 4, Nalluri further discloses:
The graphics processor of claim 3, wherein the command from the copy engine command queue is submitted to the copy engine command queue after submission of the first plurality of commands in the graphics engine command queue and the copy engine is to execute the command from the copy engine command queue before the first read of the predication value by the predication circuitry. (Nalluri [0012] – [0013] and [0042])
As per claim 5, Nalluri further discloses:
The graphics processor of claim 4, wherein the predication circuitry is configured to: load a second command buffer including the second plurality of commands; detect a second predicated command region in the second command buffer, the second predicated command region including the second plurality of commands; perform a second read of the predication value from the memory; and execute the second plurality of commands based on the predication value returned by the second read, the predication value having been updated via the copy engine after the first plurality of commands was bypassed and before the second read of the predication value. (Nalluri [0012] – [0013])
As per claim 6, Nalluri further discloses:
The graphics processor of claim 4, wherein the predication circuitry is configured to: load a second command buffer including the second plurality of commands; detect a second predicated command region in the second command buffer, the second predicated command region including a third plurality of commands; read the predication value from the memory; bypass execution of the third plurality of commands based on the predication value; and execute the second plurality of commands, wherein the second plurality of commands is outside of the second predicated command region of the second command buffer. (Nalluri [0012] – [0013])
As per claim 8, Nalluri further discloses:
The graphics processor of claim 1, wherein the memory is an on-die memory that is coupled with the graphics engine and the copy engine. (Nalluri figure 5.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nalluri, in view of Cheng et al (US 20200250787, hereinafter Chen), and further in view of Koo et al (US 20220092722, hereinafter Koo).
As per claim 9, Nalluri discloses: A method comprising:
receiving first programming interface commands to render first data; (Nalluri Figure 1 and [0030]: step 10.)
receive second programming interface commands to render second data; (Nalluri Figure 1 and [0030]: step 10.)
submitting a command to a copy engine command queue to cause a copy engine to update a predication value in a memory associated with the graphics engine; bypassing execution of one or more workloads of the first command list at the graphics engine based on the predication value; and executing the second command list in place of the one or more workloads bypassed based on the predication value. (Nalluri [0012]: “a "Predication Enable" control field is provided in a command executed before the start of the execution of a command sequence, such as a sequence loaded into a batch buffer. In the described example, this is referred to as a "MI_BATCH_BUFFER_START" command, where MI refers to memory interface. The control field, such as a flag, when parsed by a command streamer, indicates that the MI_BATCH.sub.-- BUFFER_START command should be skipped based on a value in a predicate register. In the described example, this is referred to as a "PR_RESULT.sub.--1" register. In the described embodiment, there is also a "PR_RESULT.sub.--0" register that is used to predicate a 3DPRIMITIVE command. This command is used to trigger rendering in a 3D engine 216 of the GPU 201 shown in FIG. 4.”; [0013]: “Command buffers, such as a particular MI_BATCH_BUFFER_START command can be skipped conditionally depending upon a predicate register value, such as the PR_RESULT.sub.--1 value. A predication control field, such as a PREDICATION ENABLE field in the MI_BATCH_BUFFER_START command indicates whether the hardware is to use predication to determine whether to skip the command. When predication is enabled, then the hardware is to either skip or not skip the batch buffer depending on the PR_RESULT.sub.--1 value. When predication is not enabled, then the command is executed without reference to the predication register.”; Figure 1 and [0030]: if prediction value is not set, skip and loop back to new received batch buffer execution command.)
Nalluri did not explicitly disclose:
Wherein the first and second programming interface commands to render first and second data are for a gaming application;
where the second programming interface commands indicate that the second data is associated with a control input;
submitting a first command list to a render queue of a graphics engine to cause the graphics engine to render the first data;
submitting a second command list to a render queue of a graphics engine to cause the graphics engine to render the second data;
However, Cheng teaches:
Wherein the first and second programming interface commands to render first and second data are for a gaming application; (Cheng figure 3 and [0024]: “application jobs being queued and executed by a processing unit is shown. In one implementation, frame-based real-time applications are executed on a processing unit (e.g., GPU, FPGA, ASIC, DSP). The frame-based real-time applications include any type of gaming applications as well as any type of rendering applications that submit multiple jobs per frame and repeat this process at a constant or variable frame rate.”)
submitting a first command list to a render queue of a graphics engine to cause the graphics engine to render the first data; submitting a second command list to a render queue of a graphics engine to cause the graphics engine to render the second data; (Cheng [0023].)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Cheng into that of Nalluri in order to have the first and second programming interface commands to render first and second data are for a gaming application, submitting a first command list to a render queue of a graphics engine to cause the graphics engine to render the first data; submitting a second command list to a render queue of a graphics engine to cause the graphics engine to render the second data. Although not explicitly teaching gaming application, Nalluri [0012] does teaches command sequence which implied a queuing order for commands. Nevertheless, Cheng figure 3 and [0023] – [0024] has shown the claimed limitations are merely commonly known and used applications for modern computing, applicants have merely claimed the combination of known parts in the field to achieve predictable results of having gaming application submit GPU requests to be queued and is therefore rejected under 35 UCS 103.
Koo teaches:
where the second programming interface commands indicate that the second data is associated with a control input; (Koo [0013])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Koo into that of Nalluri and Cheng in order to have the second programming interface commands indicate that the second data is associated with a control input. It is merely a design choice to have which data associated with specific input and is therefore rejected under 35 UCS 103.
As per claim 15, it is the non-transitory machine readable medium variant of claim 9 and is therefore rejected under the same rationale. (Nalluri [0054].)
Allowable Subject Matter
Claims 4 – 7, 10 – 14 and 16 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 8/25/2026 have been fully considered but they are not persuasive.
Claim 1:
Applicant argued on pages 9 – 10 that Nalluri reference failed to anticipate the claimed limitations of claim 1. More specifically, applicant argued that the cited portion of Nalluri “may describe conditional skipping by a graphics command streamer, but they do not identify a copy engine, a copy engine command queue, or a copy-engine command that updates a prediction value in the memory”.
The examiner disagrees. Referring to cited portion of Nalluri [0012] – [0013], more specifically Nalluri [0012] teaches “a "Predication Enable" control field is provided in a command executed before the start of the execution of a command sequence, such as a sequence loaded into a batch buffer”, examiner notes that such sequencing of the commands would infer that there is a queue for the received commands, and the command containing “Prediction Enable” control field is mapped to the claimed copy-engine command, and the command streamer is mapped to the claimed “copy engine”, thus Nalluri anticipated the claimed limitations of claim 1 in full.
Claims 2 and 3:
Applicant argued on page 11, first paragraph that Nalluri failed to anticipate the “claimed detection of predicated command region coupled with claimed read from memory.”
The examiner disagrees as referring to the cited portion of Nalluri, the predicate register such as command buffers are mapped to the claimed “command region” and claimed “read from memory”.
Claim 8:
Applicant argued on page 11, second to last paragraph that Nalluri failed to anticipate the “copy engine”.
The examiner disagrees and referring to counter arguments raised for claim 1, the claimed “copy engine” is mapped to the command streamer of Nalluri, which is part of GPU (Nalluri [0045] – [0046]).
Claims 9 and 15:
Applicant argued on pages 12 – 13 that the combination of Nalluri, Cheng and Koo does not teach the claimed limitations of claim 9. More specifically, applicant argued that Nalluri did not teach the claimed “a copy engine, a copy engine command queue, or a copy-engine command that updates a prediction value in the memory”.
The examiner disagrees, see the counter arguments for claim 1 above.
Applicant argued on page 13 that this is no rationale to combine the cited references.
The examiner disagrees. Referring to Nalluri figure 1 and [0030], it teaches receiving a new batch buffer execution command for GPU but failed to teach that first and second programming interface to render first and second data for a gaming application. Cheng and Koo are introduced to cure that deficiency by teaching having games issue rendering jobs is a commonly known and used application of modern GPU based scheduling and execution, and therefore would be obvious for one of ordinary skill in the art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 5712701014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196
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