Prosecution Insights
Last updated: April 19, 2026
Application No. 18/478,431

RESISTOR DRIFT CALIBRATION

Non-Final OA §103
Filed
Sep 29, 2023
Examiner
RETEBO, METASEBIA T
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
571 granted / 639 resolved
+21.4% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
31 currently pending
Career history
670
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
46.0%
+6.0% vs TC avg
§102
32.6%
-7.4% vs TC avg
§112
13.3%
-26.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 639 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election with traverse of species I corresponding to figure 12 and directed to claims 1-20 in the reply filed on 10/03/2025 is acknowledged. The traversal is on the grounds that there is no patentably distinct species present in the claims 1-20. The examiner acknowledge the claims 1-20 read on the elected species illustrated in figure 12 and examine these claims on the merits. However, the examiner maintains that the species illustrated in figures 1-2, 4, 8 and 12 are patentably distinct for the following reasons. Each figure represents a structural and/or functionally distinct configuration of the drift sense circuit and/or driver calibration controller, For example: Figures 1-2 depict a configuration where the drift sense circuit includes a different arrangement or type of reference component (e.g., switch controller, test circuit, driver circuit and load). Figure 4 illustrate a current sensing circuit is integral (130B) to the drift sense and a feedback loop or calibration path not present in Figure 12. Figure 8 include additional circuitry and a current sensing circuit (130C) that are absent in the elected species. Figure 12 as elected appears to implement a specific calibration resistor arrangement that’s not present in the other figures. These differences are not mere design choices but reflect distinct technical implementations that would not be obvious variation to one of ordinary skill in the art. Therefore, the species are not considered obvious variants of each other and are patentably distinct under MPEP §806.04(f). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Larson et al. (US 2020/0393529 and Larson hereinafter) in view of Cesaretti (US 10107873). Regarding claim 1, Larson discloses a system [fig. 4] comprising: a drift sense circuit [HALL sensor 210] having an input terminal [internal input 210], an output terminal [terminal 228/224], and a ground terminal [internal ground in 210]; and a drift calibration controller [460] coupled to the output terminal of the drift sense circuit, the drift calibration controller configured to: obtain a sense signal [224/228] responsive to an input voltage [voltage input to 210] applied to the input terminal; determine a drift result [using 470] of the resistor responsive to the sense signal [par. 0030-0035]; and update a control operation [using 440] responsive to the drift result [par. 0040-0046]. Larson does not explicitly disclose the drift sense circuit including: a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the input terminal; and a reference component having a first terminal and a second terminal, the second terminal of the reference component coupled to the ground terminal. However, Cesaretti disclose a drift sense circuit [Hall sensor/100, fig. 1] including: a resistor [104] having a first terminal and a second terminal, the first terminal of the resistor coupled to an input terminal [102]; and a reference component [106] having a first terminal and a second terminal, the second terminal of the reference component coupled to the ground terminal [112]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Larson by resistor in the sensor as taught in Cesaretti in order to use well known drift Hall sensor. Regarding claim 2, Larson in view of Cesaretti [fig. 1] discloses wherein the second terminal of the resistor is coupled to the output terminal [114, fig. 1] and to the first terminal of the reference component. Regarding claim 3, Larson in view of Cesaretti discloses wherein the reference component is a metal resistor [resistor formed in a metal layer [col. 10, ln. 1, ref. Cesaretti]. Regarding claim 8, Larson in view of Cesaretti discloses [fig. 4] wherein the output terminal is a first output terminal [output terminal to signal 228], and the drift sense circuit includes a ratiometric measurement circuit [Hall sensors 210] having the input terminal, the first output terminal, a second output terminal, and the ground terminal, the ratiometric measurement circuit including a first sense path [path through signal 228] and a second sense path [path through 224], the resistor and the reference component being part of the first sense path. Regarding claim 10, Larson in view of Cesaretti discloses [fig. 1] wherein the resistor is a first resistor [104], and the second sense path includes: a second resistor [108] having a first terminal and a second terminal, the first terminal of the second resistor coupled to the input terminal [102]; and a third resistor [110] having a first terminal and a second terminal, the first terminal of the third resistor coupled to the second terminal of the second resistor, and the second terminal of the third resistor coupled to the ground terminal [112]. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Perrott et al. (US 2022/0224348 and Perrott hereinafter) in view of Chen et al. (US 8421556 and Chen hereinafter). Regarding claim 15, Perrott discloses a circuit (fig. 7A) comprising: a first switch [switch between right and left R2/2’s] having a first terminal [terminal connected to left R2/2], a second terminal [terminal connected to right R2/2], and a control terminal [terminal connected to MID(t)]; a capacitor [C2] having a first terminal [terminal connected to right R2/2] and a second terminal [terminal connected to ground], the first terminal of the capacitor coupled to the second terminal of the first switch; a second switch [switch between right and left R3/2’s] having a first terminal [terminal connected to left R3/2], a second terminal [terminal connected to right R3/2], and a control terminal [terminal connected to LAST(t)], the first terminal of the second switch coupled to the second terminal of the first switch and to the first terminal of the metal capacitor; a first resistor [right R3/2] having a first terminal [terminal connected to the switch] and a second terminal [terminal connected to C3], the first terminal of the first resistor coupled to the second terminal of the second switch; a second resistor [R1] having a first terminal and a second terminal, the first terminal of the second resistor coupled to the first terminal of the first switch; and a third resistor [left R2/2] having a first terminal [terminal connected to R1] and a second terminal [terminal connected to switch between R2/2’s], the first terminal of the third resistor coupled to the second terminal of the second resistor. Perrott does not explicitly disclose metal capacitor. In the same field of endeavor, Chen discloses metal capacitor used interchangeably. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Perrott by metal capacitor as taught in Chen in order to use well known metal capacitor. Allowable Subject Matter Claims 19 and 20 are allowed. Claims 4-7, 9, 11-14 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /METASEBIA T RETEBO/Primary Examiner, Art Unit 2842
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Prosecution Timeline

Sep 29, 2023
Application Filed
Oct 03, 2025
Response Filed
Jan 14, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603647
DRIVER CIRCUIT OF SWITCHING TRANSISTOR, LASER DRIVER CIRCUIT, AND CONTROLLER CIRCUIT OF CONVERTER
2y 5m to grant Granted Apr 14, 2026
Patent 12603646
TRACK AND HOLD CIRCUIT
2y 5m to grant Granted Apr 14, 2026
Patent 12597915
CAPACITANCE CIRCUIT
2y 5m to grant Granted Apr 07, 2026
Patent 12592690
CONTROL CIRCUIT
2y 5m to grant Granted Mar 31, 2026
Patent 12592692
POWER DEVICE
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+5.2%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 639 resolved cases by this examiner. Grant probability derived from career allow rate.

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