DETAILED ACTION
This Office action is in response to the amendment filed on 31 October 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Arguments
Applicant's arguments filed 31 October 2025 have been fully considered but they are not persuasive.
With respect to independent claims 1, 8 and 13, Applicant argues that the applied prior art in Meyer (see citation below in this Office action) fails to disclose or suggest the recited limitation of shunting excess charge to ground because Meyer instead requires that the excess load current is transferred back to the input of the converter.
Examiner respectfully disagrees, however, because in the actual circuit implementation of Meyer’s CCSC, shown in Fig. 1b on p. 816 and in Fig. 4 on p. 817, it can be seen that the CCSC includes a MOSFET Qaux that is connected between the output node (via inductor Laux) and ground. When turned on, Qaux conducts current (see p. 816, left column, last full paragraph: “the auxiliary current can be sensed using the R(ds)on of the auxiliary MOSFET Qaux”) and thus shunts at least some of the excess charge at the output node to ground. Meyer further provides a formula (see p. 818, left column, eq. (6)) for calculating the RMS current flowing through Qaux. It is basic knowledge in the art that electric charge and electric current are proportional quantities according to the formula
Q
=
I
∙
t
, where Q is charge, I is current, and t is time.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-10, 12-17, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by “Controlled current source circuit (CCSC) for reduction of output voltage overshoot in buck converters” by Meyer et al. (hereinafter “Meyer”).
In re claims 1-3, 5-10, 12-17, 19 and 20, Meyer on its face clearly discloses the claimed invention in the form of a voltage regulator circuit, device and system (buck converter circuit Figs. 1b and 4) comprising a capacitor bank (output capacitor Co) and active shunt circuit (CCSC comprising Qaux, Daux, and related control circuitry including voltage comparators) that is in parallel and integrated with the capacitor bank (Fig. 4).
In the Abstract and throughout the disclosure, Meyer teaches the basic functional purpose of Applicant’s invention, both as claimed and as disclosed in the specification: to reduce the amount of output capacitance needed to control transient load events based on the observation that voltage overshoots from load step-down events are much larger than voltage undershoots from step-up events.
Thus, the output capacitor bank (Co) selection can be made much smaller based on the latter, because it is configured for a first voltage step corresponding to the smaller voltage undershoot events, while the active shunt circuit (CCSC in Meyer as cited above) is configured to handle a second, larger voltage step by shunting excess charge to ground (through Qaux, when turned ON: p. 816, left column, last full paragraph; see p. 818, eq. (6); and see auxiliary current waveforms in Figs. 3 and 5-6) and away from the load and the output capacitors. See the disclosure of Meyer as a whole, and in particular the Abstract, sec. I. Introduction, sec. VI. Conclusion, and the load transient waveforms shown in Figs. 3, 5, and 6.
Further, all of the structural elements recited in the dependent claims under this rejection are illustrated in the circuit of Fig. 4 in Meyer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer (cited above) in view of Chang et al. (US 2019/0058351; hereinafter “Chang”).
In re claims 4, 11, and 18, Mayer discloses the claimed invention as explained above, except for the shunt circuit comprising a Zener diode.
Whereas Chang discloses a voltage regulating circuit and system (Figs. 1-2) in which a Zener diode (D1) is included in a shunt circuit (see Fig. 2) for the purpose of regulating and limiting voltage overshoots to protect the loads and other circuitry from excessive voltages (see [0036]-[0037]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit, device, and system of Meyer by including a Zener diode in the shunt circuit for protective purposes as taught by Chang.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838