Prosecution Insights
Last updated: October 01, 2026
Application No. 18/478,485

VOLTAGE REGULATOR WITH ACTIVE SHUNT

Non-Final OA §102§103
Filed
Sep 29, 2023
Priority
Jan 06, 2023 — provisional 63/478,906
Examiner
FINCH III, FRED E
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Amd
OA Round
3 (Non-Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
741 granted / 924 resolved
+12.2% vs TC avg
Strong +17% interview lift
Without
With
+17.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
27 currently pending
Career history
952
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
47.0%
+7.0% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 924 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office action is in response to the amendment filed on 23 April 2026. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 23 April 2026 has been entered. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Response to Arguments Applicant's arguments filed 23 April 2026 have been fully considered but they are not persuasive. Applicant argues (Remarks at p. 6: section I. A.) that the examiner misinterprets the operations of the circuit in Meyer (“Controlled current source circuit (CCSC) for reduction of output voltage overshoot in buck converters”) in a manner that contradicts the actual teachings in Meyer. Specifically, examiner’s understanding of the operation described in Meyer is that when the switch Qaux is turned on, it conducts current to ground and thus shunts at least some of excess charge at the output node of the buck converter to ground. Applicant contends that this is contradicted by statements in Meyer that excess current is transferred from the output of the buck converter back to its input, and therefore is not shunted to ground as claimed (id., citing Meyer at Abstract, p. 816). Examiner respectfully disagrees, however, because Meyer explicitly teaches that Qaux conducts current, and since Qaux, together with inductor Laux, is connected between the output terminal and the ground terminal, such conduction must shunt some of the excess charge to ground. That is, Meyer teaches that Qaux is operated (i.e., turned ON and OFF periodically) at high frequency (p. 816, left-column, paragraph immediately before section II; see also graphs of auxiliary current in Figs. 2, 3, 5). The person of ordinary skill in the art will understand that when Qaux is turned ON, it conducts current from the higher voltage at the output terminal to ground (zero volts); this is explicitly evidenced in Meyer at p. 818, section III: Loss Analysis, A. Conduction Loss. Specifically eq. (6) calculates the effective or RMS current through switch Qaux and eqs. (9) and (10) calculate the conduction loss of the switch Qaux. In order for there to be conduction loss in Qaux, Qaux must be conducting current. Thus, when the CCSC is activated during a voltage overshoot caused by a load step-down transient, Qaux begins operating, or turning ON and OFF periodically, and, during the times when it is turned ON, shunts at least a portion of excess charge to ground. More broadly, Examiner notes that the claim recitation, “shunting excess charge to ground”, is understood based on Applicant’s specification and the knowledge of the ordinary artisan to mean that excess charge is dissipated on a shunt circuit pathway to the ground terminal, or in other words, to the return terminal of the electrical source (in Meyer, Figs. 1(b) and 4 the ground terminal is the negative terminal of the source Vin). For instance, Applicant discloses in the specification at [0031] that the pathway to ground upon which the excess charge is shunted may include, in examples, a resistor or a Zener diode. Thus, in light of the specification, “shunting excess charge to ground” must be understood to mean the dissipation of excess charge via components in the shunt pathway to ground. In the case of Meyer’s disclosure, at least a portion of such excess charge is shunted through inductor Laux and switch Qaux when Qaux is turned ON. The amount of such shunted charge could be calculated based on the equations provided in Meyer, as cited above. While not all of the excess charge is shunted through this specific pathway, nonetheless the claims do not specify such a limitation; the broadest reasonable interpretation of “shunting excess charge” is that at least a portion of such excess charge is shunted. Finally, even assuming arguendo that the claims as presented must be interpreted as shunting all excess charge to ground, it is respectfully asserted that this still occurs in Meyer, just through additional pathways, since any charge which is shunted back to the input of the circuit will then still be converted through the main Buck converter to supply the load, thus eventually returning to the power source via the ground terminal. See Figs. 1(b) and 4 of Meyer. Applicant’s disclosure does not show any specific circuit schematic of the shunt circuit beyond the vague box diagram in Fig. 3, and thus it is not seen how the phrase, “shunting excess charge to ground” could be interpreted in a narrower way that would not read onto Mayer’s disclosure. Applicant also argues (Remarks at p. 7) that Meyer fails to teach shunting of excess charge to ground during a voltage overshoot, according to the amended claim 1. However, Examiner respectfully disagrees, because Meyer teaches at least in the title, abstract, and graphically in Figs. 3 and 5 that auxiliary CCSC circuit is operating specifically during load step-down transients when a voltage overshoot occurs at the output of the buck converter. Further, regarding Applicant’s contention that “any interpretation of Meyer suggesting "shunting excess charge to a ground during a voltage overshoot" would amount to impermissible hindsight” (id., near end of first full paragraph on p. 7) it is respectfully submitted that as Meyer is shown to anticipate the invention of claim 1 and is rejected under 35 U.S.C. 102, the question of hindsight does not a relevant factor. Only the express or inherent teachings of Meyer, as it would have been understood to a person of ordinary skill in the art, are used to demonstrate anticipation of the broadest reasonable interpretation of claim language. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 5-10, 12-17, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by “Controlled current source circuit (CCSC) for reduction of output voltage overshoot in buck converters” by Meyer et al. (hereinafter “Meyer”). In re claims 1-3, 5-10, 12-17, 19 and 20, Meyer on its face clearly discloses the claimed invention in the form of a voltage regulator circuit, device and system (buck converter circuit Figs. 1b and 4) comprising a capacitor bank (output capacitor Co) and active shunt circuit (CCSC comprising Qaux, Daux, and related control circuitry including voltage comparators) that is in parallel and integrated with the capacitor bank (Fig. 4). In the Abstract and throughout the disclosure, Meyer teaches the basic functional purpose of Applicant’s invention, both as claimed and as disclosed in the specification: to reduce the amount of output capacitance needed to control transient load events based on the observation that voltage overshoots from load step-down events are much larger than voltage undershoots from step-up events. Thus, the output capacitor bank (Co) selection can be made much smaller based on the latter, because it is configured for a first voltage step corresponding to the smaller voltage undershoot events, while the active shunt circuit (CCSC in Meyer as cited above) is configured to handle a second, larger voltage step by shunting excess charge to ground (through Qaux, when turned ON: p. 816, left column, last full paragraph; see p. 818, eq. (6); and see auxiliary current waveforms in Figs. 3 and 5-6) and away from the load and the output capacitors during the voltage overshoot (the CCSC and Qaux are activated during voltage overshoots as shown in Figs. 3, 5, 6 and described in the abstract and title). See the disclosure of Meyer as a whole, and in particular the Abstract, sec. I. Introduction, sec. VI. Conclusion, and the load transient waveforms shown in Figs. 3, 5, and 6. Further, all of the structural elements recited in the dependent claims under this rejection are illustrated in the circuit of Fig. 4 in Meyer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer (cited above) in view of Chang et al. (US 2019/0058351; hereinafter “Chang”). In re claims 4, 11, and 18, Mayer discloses the claimed invention as explained above, except for the shunt circuit comprising a Zener diode. Whereas Chang discloses a voltage regulating circuit and system (Figs. 1-2) in which a Zener diode (D1) is included in a shunt circuit (see Fig. 2) for the purpose of regulating and limiting voltage overshoots to protect the loads and other circuitry from excessive voltages (see [0036]-[0037]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit, device, and system of Meyer by including a Zener diode in the shunt circuit for protective purposes as taught by Chang. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRED E FINCH III/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Sep 29, 2023
Application Filed
Aug 12, 2025
Non-Final Rejection mailed — §102, §103
Oct 31, 2025
Response Filed
Feb 05, 2026
Final Rejection mailed — §102, §103
Apr 23, 2026
Request for Continued Examination
Apr 28, 2026
Response after Non-Final Action
Jul 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12738847
BUCK CONVERTER, METHOD OF OPERATING THE SAME AND ELECTRONIC DEVICE INCLUDING THE SAME
1y 11m to grant Granted Sep 15, 2026
Patent 12730470
CURRENT MIRROR PRE-BIAS FOR INCREASED TRANSITION SPEED
2y 7m to grant Granted Sep 08, 2026
Patent 12732098
RESONANT POWER CONVERSION CIRCUIT AND CONTROL METHOD THEREOF FOR BALANCING DUTY CYCLES OF HIGH-SIDE TRANSISTOR AND LOW-SIDE TRANSISTOR
1y 9m to grant Granted Sep 08, 2026
Patent 12726022
POWER SUPPLY
2y 5m to grant Granted Sep 01, 2026
Patent 12719352
POWER SUPPLY DEVICE INCLUDING VOLTAGE BOOSTING CIRCUIT
3y 7m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
97%
With Interview (+17.2%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 924 resolved cases by this examiner. Grant probability derived from career allowance rate.

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