Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7, 11, 17, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication 2021/0256756 A1 (hereinafter Yang).
Regarding claim 1, the limitations “A method of preparing and storing primitive lists for use in a tile-based graphics processing system, in which a render output to be generated is divided into a plurality of tiles for rendering purposes, with each tile of the render output being rendered separately, the method comprising: preparing and storing primitive lists for plural sets of regions of the render output, each primitive list indicating graphics primitives to be processed when rendering a region of the render output” are taught by Yang (Yang, e.g. abstract, paragraphs 3-15, 70-163, describes a graphics processing system which renders geometry data received from an application using a tile-based rendering process, wherein the geometry comprises a set of primitives, e.g. paragraphs 3-10, 70-75, 126 . Yang, e.g. paragraphs 6-9, 70-125, teaches that after being transformed into screen space, primitives are stored in one or more primitive section(s) corresponding to the one or more region(s) of the screen space overlapped by the primitive, e.g. paragraphs 9, 125, where the one or more primitive section(s) for each region are stored in one or more primitive block(s) for the corresponding region, i.e. for the plurality of different regions, primitive sections/blocks/lists are prepared and stored, as claimed, where each region is rendered by processing the corresponding sections/blocks/lists, e.g. Yang, paragraphs 10-14, 132-147, figures 1, 17. As discussed further below, both of Yang’s primitive section and primitive block elements can correspond to the claimed primitive lists, i.e. the primitive section has a list of primitives, e.g. paragraphs 75, 86, 87, 92, figure 5, element 410, and the primitive block is a combined listing of primitive sections having lists of primitives, e.g. paragraphs 80, 83. It is additionally noted with respect to corresponding independent claims 11 and 20, Yang, e.g. paragraphs 147-155, teaches that the system may be implemented using a variety of structural embodiments, including as a processor, which may be programmed using a stored program, and/or fixed function circuitry.)
The limitations “storing in a plurality of primitive list pointer arrays, one or more pointers, each pointer indicating a location in storage of one or more of the primitive lists; … and storing in a further pointer array, one or more further pointers, each further pointer indicating a location in storage of one or more of the primitive list pointer arrays” are taught by Yang (As noted above, both of Yang’s primitive section and primitive block elements can correspond to the claimed primitive lists, i.e. the primitive section has a list of primitives, e.g. paragraphs 75, 86, 87, 92, figure 5, element 410, and the primitive block is a combined listing of primitive sections having lists of primitives, e.g. paragraphs 80, 83. Yang teaches that the tiling engine generates per-tile display lists comprising pointers to one or more primitive blocks, e.g. paragraphs 10, 70, 126, figure 2, and that the primitive block headers may include offset addresses, i.e. pointers, indicating the location of each primitive section within the primitive block, e.g. paragraphs 83, 84, 94, such that in a first mapping of Yang’s data structures, the primitive sections correspond to the claimed primitive lists, the primitive blocks comprising headers including pointers to the primitive sections of the block correspond to the claimed primitive list pointer arrays, and the tile display lists including pointers to one or more of the primitive blocks comprising primitives required for rendering the tile correspond to the claimed further pointer arrays storing pointers to one or more primitive pointer lists. Further, Yang, e.g. figure 1, paragraphs 11, 12, teaches that the rasterization logic operates by fetching the display lists from memory, such that one of ordinary skill in the art would have found it implicit that Yang’s system would include the claimed further pointer array, i.e. a listing of display list addresses in memory used by the rasterizer rendering a tile to retrieve the corresponding display list, such that in a second mapping of Yang’s data structures, the implied listing of display list addresses used by the rasterizer corresponds to the claimed further pointer array having memory addresses, i.e. pointers, of the display lists, wherein the display lists comprise a set of pointers indicating the location of one or more primitive blocks, such that the display lists correspond to the claimed primitive list pointer arrays, and as discussed above the primitive blocks correspond to the claimed primitive lists. It is noted that the first mapping, wherein Yang’s primitive sections correspond to primitive lists, Yang’s primitive blocks correspond to primitive list pointer arrays, and Yang’s display lists correspond to further pointer arrays anticipates the claimed invention as in the independent claims and is used for the rejections of claims 1, 4, 5, 7, 11, 14, 15, 17, and 20 . The second mapping, wherein Yang’s primitive blocks correspond to primitive lists, Yang’s display lists correspond to primitive list pointer arrays, and Yang’s implied listing of display list addresses corresponds to the further pointer array corresponds to an obvious modification of Yang’s system, is applied as part of the 103 rejections in view of Baldwin, Jesus, and/or Livesly to claims 4-6, 8, 9, 14-16, 18, and 19.)
The limitation “wherein the primitive list pointer arrays respectively store pointers indicating locations in memory of primitive lists prepared for a respective one of the sets of regions of the render output” is taught by Yang (Yang, e.g. paragraphs 9, 125, indicates that primitive blocks/sections are generated for each of the regions of screen space, i.e. each region corresponds to a region of the render output, such that with respect to the first mapping of Yang’s data structures as discussed above, where the primitive list pointer arrays correspond to Yang’s primitive blocks, each primitive list pointer array, i.e. primitive block, stores primitive list locations for only one region, i.e. the claimed respective one of the sets of regions. Further, Yang, e.g. paragraphs 9, 125, indicate that the regions may or may not be the same size as the rendering tiles, such that with respect to the second mapping of Yang’s data structures as discussed above, where the primitive list pointer array corresponds to Yang’s per-tile display lists, when the regions are the same size as the render tiles, then each display list would correspond to one region, i.e. the claimed respective one of the sets of regions.)
Regarding claim 7, the limitation “only allocating and initialising memory space for a primitive list pointer array when it is determined that the primitive list pointer array is required to store a location of a primitive list” is taught by Yang (Yang, e.g. paragraphs 97, 103-106, 110-118, teaches that primitive blocks and sections are allocated/initialised on an as needed basis, i.e. if a primitive cannot be added to the current primitive section, a new section may be required, or if a state change requires starting a new primitive block, then the new primitive block is allocated/initialized, e.g. paragraphs 106, 117, 118. With respect to the first mapping of Yang’s data structures as discussed in claim 1, where the primitive list pointer arrays correspond to Yang’s primitive blocks and the primitive lists correspond to Yang’s primitive sections, Yang’s allocation/initialization of a new primitive block in response to the state change for a received primitive corresponds to the claimed allocation/initialization of the primitive list pointer array when it is determined that the primitive list pointer array is required to store a location of a primitive list, i.e. the primitive having the changed state requires a new primitive block to be initialized for the new primitive section which will include the primitive having the changed state.)
Regarding claims 11 and 20, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 1 above.
Regarding claim 12, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 2 above.
Regarding claim 13, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 3 above.
Regarding claim 17, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 7 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2021/0256756 A1 (hereinafter Yang) as applied to claims 1 and 11 above, and further in view of U.S. Patent 7,505,036 B1 (hereinafter Baldwin).
Regarding claim 4, the limitation “preparing primitive lists for each of multiple render layers, wherein a respective primitive list pointer array indicates the location in memory of primitive lists for a respective render layer” is not explicitly taught by Yang (As discussed in the claim 1 rejection above, Yang, e.g. paragraphs 6-9, 70-125, teaches that after being transformed into screen space, primitives are stored in one or more primitive section(s) corresponding to the one or more region(s) of the screen space overlapped by the primitive. While Yang’s primitive sections, primitive blocks, and display lists correspond to different regions of screen space, Yang does not address multiple render layers.) However, this limitation is taught by Baldwin (Baldwin, e.g. abstract, cols 3-7, figure 4, describes a tile based rendering system which supports efficient transparency rendering by separating primitives for each tile/bin into opaque and transparent layers, such that for each tile/bin/region of screen space, primitive lists are separately generated for each layer as shown in figure 4. As in figure 4, for each tile a bin record is generated having a linked list of entries including a list of primitives for the bin from either the opaque or transparent layer. As discussed in Baldwin, e.g. col 3, col 4, line 63 – col 5, line 14, col 6, lines 37 – col 7, line 17, separating the primitives into opaque and transparent layers allows for more efficiently processing transparent primitives than conventional approaches.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s tile based rendering system to include Baldwin’s efficient transparency rendering by separating primitives into opaque and transparent layers. Baldwin, e.g. figure 4, shows that for each tile a display list for each layer is generated, e.g. for tile 405, an opaque bin record 405OB and transparent bin record 405TB are generated, where the display list for each layer identifies a bin record in the form of a linked list comprising a header portion Bin Record B pointing to a primitive list Bin Record P, and further Baldwin, e.g. col 6, lines 36-65, teaches that primitives are sent to the respective bins based on a change in transparency state, analogous to Yang, e.g. paragraphs 106, 117, 118, teaching that a new primitive block is generated for a region in response to a state change. In Yang’s modified system separating primitives into opaque layers and transparent layers, separate display lists would be generated for each layer for each tile, and separate primitive blocks would be generated for each layer for each region, analogous to Yang, paragraphs 106, 117, 118, such that Yang’s modified system generates multiple display lists/primitive blocks for multiple render layers for each tile/region. Finally it is noted that both mappings of Yang’s system as in the claim 1 rejection read on the claim 4 limitation, i.e. with respect to the first mapping of Yang’s data structures, where the primitive list pointer array corresponds to Yang’s primitive blocks and the primitive lists correspond to Yang’s primitive sections, separate primitive list pointer arrays, i.e. primitive blocks, pointing to separate primitive lists, i.e. primitive sections, are generated for each layer, and with respect to the second mapping of Yang’s data structures where the primitive list pointer array corresponds to Yang’s per-tile display lists, Yang’s separate display lists generated for each layer for each tile would correspond to separate primitive list pointer arrays for each layer.
Regarding claim 14, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 4 above.
Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2021/0256756 A1 (hereinafter Yang) as applied to claims 1 and 11 above, and further in view of U.S. Patent 7,505,036 B1 (hereinafter Baldwin) in view of U.S. Patent Application Publication 2023/0215095 A1 (hereinafter Jesus).
Regarding claim 5, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 4 above, except for the hierarchical limitations “preparing a hierarchical set of primitive lists for each of multiple render layers, wherein a respective primitive list pointer array indicates the location in memory of primitive lists for a respective hierarchical level of a respective render layer” which are not explicitly taught by Yang as modified in view of Baldwin in the claim 4 rejection. However, these limitations are taught by Jesus (Jesus, e.g. abstract, paragraphs 81-241, describes a tile based rendering system which divides the screen space into a multi-level hierarchy of tile groups, e.g. paragraphs, and, analogous to Yang’s tile-based rendering system, places input primitives into primitive blocks for each tile/region at each level of the hierarchy, e.g. paragraphs 90-116, and generates for each tile of each level of the hierarchy a display list identifying corresponding primitive blocks, e.g. paragraphs 122-135. It is additionally noted that Jesus, e.g. paragraphs 129-135, describes a data structure shown in figure 17 storing pointers 1702 to the display lists for different tiles, corresponding to Yang’s implied listing of display list addresses used by the rasterizer as discussed in the second mapping of Yang’s data structures in the claim 1 rejection, wherein the further pointer array corresponds to the implied listing.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s tile based rendering system, including Baldwin’s separating rendering layers for efficient transparent rendering, to include Jesus’ multi-level hierarchy tiling technique in order to improve memory storage and bandwidth usage, e.g. Jesus, paragraphs 90, 91. As discussed in the claim 4 rejection, in Yang’s modified system separating primitives into opaque layers and transparent layers, separate display lists would be generated for each layer for each tile, and separate primitive blocks would be generated for each layer for each region. In Yang’s modified system further including Jesus’ multi-level hierarchy tiling, the separate display lists would be generated for each layer for each tile of each level of the hierarchy, and would comprise pointers to the separate primitive blocks/sections for the respective layer for each tile/region of each level of the hierarchy. With respect to the first mapping of Yang’s data structures, where the primitive list pointer array corresponds to Yang’s primitive blocks and the primitive lists correspond to Yang’s primitive sections, each primitive block would be associated with one or more tiles/regions at one or more levels of the hierarchy associated with either the opaque or transparent layer, such that each primitive list pointer array indicates the location of primitive lists for said one or more levels of the hierarchy associated with said opaque or transparent layer. Further, as noted above, Jesus, e.g. paragraphs 129-135, describes a data structure shown in figure 17 storing pointers 1702 to the display lists for different tiles, corresponding to Yang’s implied listing of display list addresses used by the rasterizer as discussed in the second mapping of Yang’s data structures in the claim 1 rejection, wherein the further pointer array corresponds to the implied listing, such that as discussed further in the claim 8 rejection below, Yang’s modified tile-based rendering system could include Jesus’ data structure of figure 17, corresponding to Yang’s implied listing of display list addresses. In the second mapping of Yang’s modified tile-based rendering system including Jesus’ data structure of figure 17, the pointers 1702 would correspond to the further pointer array pointing to the display lists for each tile/region of each level of the hierarchy for both the opaque and transparent layers, and Yang’s display lists for each tile/region of each level of the hierarchy for both the opaque and transparent layers would correspond to the claimed primitive list pointer arrays indicating the location in memory of primitive lists, i.e. Yang’s primitive blocks as in the second mapping, for a respective hierarchical level of a respective render layer.
Regarding claim 15, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 5 above.
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2021/0256756 A1 (hereinafter Yang) as applied to claims 1 and 11 above, and further in view of U.S. Patent Application 2023/0334749 A1 (hereinafter Livesly)
Regarding claim 6, the limitation “allocating and initialising memory space for the further pointer array prior to preparing and storing primitive lists” is not explicitly taught by Yang (As discussed in the claim 1 rejection above, in the second mapping, the further pointer array is mapped to Yang’s implied listing of display list addresses used by the rasterizer. While one of ordinary skill in the art would have found it implicit that Yang’s implied listing of display list addresses could be allocated and initialized prior to processing primitives into primitive blocks/sections, i.e. the data structure inherently must be allocated and initialized some memory space prior to use, and one of ordinary skill in the art would know that it is common to allocate/initialize memory for data structures which will be used by a rendering algorithm as part of a setup process prior to rendering processing, in the interest of compact prosecution Livesly is cited for explicitly teaching this step.) However, this limitation is taught by Livesly (Livesly, e.g. abstract, paragraphs 2-10, 189-285, describes a tile-based rendering system generating per-tile lists of primitives for rendering each tile, e.g. paragraphs 189-191, 197. Livesly, e.g. paragraphs 203, 204, teaches that a set of head pointers pointing to the start of a corresponding tile control list comprising pointers to primitive blocks can be stored in statically allocated memory, i.e. memory that is allocated/initialized prior to performing rendering processing. Livesly’s head pointers correspond to Yang’s implied listing of display list addresses, i.e. the head pointers point the location of the control list for each tile, and are allocated/initialized prior to processing primitives for rendering, i.e. are statically allocated.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s tile based rendering system to use Livesly’s statically allocated head pointers to implement Yang’s implied listing of display list addresses, because one of ordinary skill in the art would recognize that Yang’s implied listing would need to be allocated/initialized before use, and know, as taught by Livesly, that the listing of display list addresses could be statically allocated prior to performing rendering processing on the primitives, i.e. prior to preparing and storing the primitive lists. As noted above, and discussed in the claim 1 rejection, in the second mapping of Yang’s data structures, the further pointer array is mapped to Yang’s implied listing of display list addresses used by the rasterizer, i.e. as claimed the further pointer array would be allocated/initialized prior to preparing and storing the primitive lists in Yang’s modified system.
Regarding claim 9, the limitations “when a location in storage for a primitive list is allocated, writing a pointer indicating a location in storage of the primitive list to a cache; and when a primitive list pointer array for storing the pointer has been initialized, writing the pointer from the cache to the primitive list pointer array” are partially taught by Yang (As discussed in the claim 7 rejection above, Yang, e.g. paragraphs 97, 103-106, 110-118, teaches that primitive blocks and sections are allocated/initialised on an as needed basis, i.e. if a primitive cannot be added to the current primitive section, a new section may be required, or if a state change requires starting a new primitive block, then the new primitive block is allocated/initialized, e.g. paragraphs 106, 117, 118. With respect to the second mapping of Yang’s data structures as discussed in claim 1, where the primitive list pointer array corresponds to Yang’s display lists and the primitive lists correspond to Yang’s primitive blocks, Yang’s allocation/initialization of a new primitive block in response to the state change for a received primitive corresponds to the claimed allocation/initialization of the primitive list, wherein the tile display list(s) are generated to include pointer(s) to one or more primitive blocks. While Yang, e.g. figure 1, paragraph 126, teaches that the primitive blocks are generated prior to the display lists, which implicitly, if not inherently, teaches the claimed writing of the pointer to a cache, i.e. if the primitive blocks are allocated prior to generating display lists, the location of each primitive block would need to be stored in memory for access by the tiling engine, i.e. written to a cache and then written to the display list(s) from the cache. In the interest of compact prosecution Livesly is cited for explicitly teaching maintaining a listing of primitive block addresses used by a tiling engine generating a tile display list.) However, this limitation is taught by Livesly (Livesly, e.g. abstract, paragraphs 2-10, 189-285, describes a tile-based rendering system generating per-tile lists of primitives for rendering each tile, e.g. paragraphs 189-191, 197. Livesly, e.g. paragraphs 189, 191, 197, 242, 247-250, teaches that the primitives are grouped into primitive blocks, and tile display lists are generated comprising a set of the primitive blocks, wherein the memory allocation manager maintains an index of data in memory, including addresses and the type of data, e.g. paragraphs 210-212, 227-234, i.e. each primitive block is allocated a location in memory tracked by the allocation manager, such that the display lists generated by the geometry processing cores include pointers to the corresponding allocated location by referring to the respective primitive block. That is, Livesly teaches that the location/pointer for each primitive block/list is stored to a cache maintained by the allocation manager, and when the display lists/primitive list pointer arrays are generated, the location/pointer is then written to the display list/primitive list pointer array, as claimed. Finally, as discussed in the claim 6 rejection above, Livesly, e.g. paragraphs 203, 204, teaches that a set of head pointers pointing to the start of a corresponding tile control list comprising pointers to primitive blocks can be stored in statically allocated memory, i.e. memory that is allocated/initialized prior to performing rendering processing. Livesly’s head pointers correspond to Yang’s implied listing of display list addresses, i.e. the head pointers point the location of the control list for each tile, and are allocated/initialized prior to processing primitives for rendering, i.e. are statically allocated.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s tile based rendering system to use Livesly’s statically allocated head pointers to implement Yang’s implied listing of display list addresses, and to use Livesly’s allocation manager for tracking primitive blocks and tile display lists allocated in memory because Yang does not teach details of memory allocation and Livesly does teach details of memory allocation for an analogous tile based rendering system. As noted above, and discussed in the claim 1 rejection, in the second mapping of Yang’s data structures, the further pointer array is mapped to Yang’s implied listing of display list addresses used by the rasterizer, i.e. the second mapping is an obvious modification of Yang’s system, which is explicitly taught by Livesly’s statically allocated head pointers. Further, as discussed above, with respect to the second mapping of Yang’s data structures as discussed in claim 1, where the primitive list pointer array corresponds to Yang’s display lists and the primitive lists correspond to Yang’s primitive blocks, Yang’s allocation/initialization of a new primitive block in response to the state change for a received primitive corresponds to the claimed allocation/initialization of the primitive list, wherein the tile display list(s) are generated to include pointer(s) to one or more primitive blocks, and Yang’s modified system using Livesly’s allocation manager for tracking primitive blocks and tile display lists would store the primitive block pointers in the cache maintained by the allocation manager which would later be written to the tile display lists by the tiling engine, corresponding to the limitations of claim 9.
Regarding claim 16, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 6 above.
Regarding claim 19, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 9 above.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 2021/0256756 A1 (hereinafter Yang) as applied to claims 1 and 11 above, and further in view of U.S. Patent Application Publication 2023/0215095 A1 (hereinafter Jesus).
Regarding claim 8, the limitations “wherein preparing and storing the primitive lists comprises: for a primitive for the render output: determining a set of regions of the render output the primitive is to be listed for; determining whether the further pointer array comprises a further pointer indicating a location in storage of a primitive list pointer array for the set of regions; and when it is determined that the further pointer array does not comprise a further pointer indicating a location in storage of a primitive list pointer array for the set of regions of the render output: allocating and initialising a primitive list pointer array for the set of regions of the render output; and writing a further pointer indicating a location in storage of the primitive list pointer array in the further pointer array” are partially taught by Yang (As discussed in the claim 1 rejection above, in the second mapping, the further pointer array is mapped to Yang’s implied listing of display list addresses used by the rasterizer, the primitive list pointer arrays are mapped to Yang’s per-tile display lists, and the primitive lists are mapped to Yang’s primitive blocks. Also discussed in the claim 1 rejection above, Yang, e.g. paragraphs 6-9, 70-125, teaches that after being transformed into screen space, primitives are stored in one or more primitive section(s) corresponding to the one or more region(s) of the screen space overlapped by the primitive, e.g. paragraphs 9, 125, where the one or more primitive section(s) for each region are stored in one or more primitive block(s) for the corresponding region, and further Yang, e.g. paragraphs 126-144, teaches that each tile display list is generated by adding primitive blocks overlapping each tile to the corresponding display list. That is, in the second mapping of Yang, for all of the primitives in a primitive block, the corresponding regions/display lists are identified, corresponding to the claimed determining of the set of regions of render output the primitive(s) is(are) to be listed for, and the tile display list(s)/primitive list pointer array(s) are updated to include a pointer to said primitive block/primitive list. As Yang’s listing of display list addresses is implicitly required, rather than explicitly described, Yang does not actually address the claimed conditional, i.e. it is a given in Yang’s description that the address for storing the tile display list(s)/primitive list pointer array(s) is known, such that Yang does not address determining whether the implied listing of display list addresses comprises a pointer to the overlapped tile’s display list address, or by extension, in response to determining that the implied listing of display list addresses/further pointer array does not comprise a pointer to the overlapped tile display list(s)/primitive list pointer array(s) for the primitive block, allocating/initializing a display list(s)/primitive list pointer array(s) for the overlapped tile(s) and writing the storage location(s) in the implied listing of display list addresses/further pointer array.) However, these limitations are taught by Jesus (Jesus, e.g. abstract, paragraphs 81-241, describes a tile based rendering system which divides the screen space into a multi-level hierarchy of tile groups, e.g. paragraphs, and, analogous to Yang’s tile-based rendering system, places input primitives into primitive blocks for each tile/region at each level of the hierarchy, e.g. paragraphs 90-116, and generates for each tile of each level of the hierarchy a display list identifying corresponding primitive blocks, e.g. paragraphs 122-135. Jesus, e.g. paragraphs 129-135, further describes a data structure shown in figure 17 storing pointers 1702 to the display lists for different tiles, corresponding to Yang’s implied listing of display list addresses used by the rasterizer as discussed in the second mapping of Yang’s data structures in the claim 1 rejection, wherein the further pointer array corresponds to the implied listing. Finally, Jesus, paragraphs 129-135, teaches that the headers may comprise, in addition to a display list address, a valid flag indicating whether the address is valid or not, wherein when adding primitive blocks to the display list for a tile, the validity of the header is used to determine whether memory for the tile display list must first be dynamically allocated before the primitive block is added to the display list. That is, Jesus teaches the above two missing elements not explicitly taught by Yang, i.e. determining whether the listing of display list addresses comprises a (valid) pointer to a display list corresponding to the tile overlapped by a primitive block, and in response to determining the pointer is not valid, allocating/initializing a display list to add the primitive block to, and storing the address of the allocated/initialized display list to the header in the figure 17 data structure.)
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s tile based rendering system, to include Jesus’ data structure of figure 17, corresponding to Yang’s implied listing of display list addresses, because, as noted above, Yang does not explicitly disclose details of maintaining the implied listing of display list addresses, and Jesus describes details of maintaining an analogous data structure for listing display list addresses using the headers and footers of the figure 17 data structure, including tracking validity of display list pointers and allocating new display list data structures. In the second mapping of Yang’s data structures the further pointer array corresponds to the implied listing of display list addresses and the primitive list pointer arrays correspond to the display lists for each tile, such that in Yang’s modified tile-based rendering system including Jesus’ data structure of figure 17, the pointers 1702 would correspond to the further pointer array pointing to the display lists for each tile/region. Further, as discussed above, in the second mapping of Yang, for all of the primitives in a primitive block, the corresponding regions/display lists are identified, corresponding to the claimed determining of the set of regions of render output the primitive(s) is(are) to be listed for, and the tile display list(s)/primitive list pointer array(s) are updated to include a pointer to said primitive block/primitive list, and although Yang does not discuss the details of allocating/initializing display lists or adding the display list address to the implied listing of display list addresses, Jesus teaches determining whether the listing of display list addresses comprises a (valid) pointer to a display list corresponding to the tile overlapped by a primitive block, and in response to determining the pointer is not valid, allocating/initializing a display list to add the primitive block to, and storing the address of the allocated/initialized display list to the header in the figure 17 data structure, such that in Yang’s modified system, as claimed, when it is determined that the further pointer array does not comprise the further pointer, i.e. a valid address for the tile, a primitive list pointer array(s) is (are) allocated/initialized and then written to the further pointer array, i.e. the tile header is updated to store the valid address of the new display list.
Regarding claim 18, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 8 above.
Response to Arguments
Applicant's arguments filed 3/11/26 have been fully considered but they are not persuasive.
Applicant asserts, exclusively on the basis of Yang’s paragraph 18, that Yang’s primitive sections have no association with regions of the render output. As noted in the rejections, Yang, e.g. paragraphs 9, 125, clearly anticipates that primitive blocks are associated with one of the plural regions of screen space which may or may not be larger than a tile. Instead of addressing the portion of Yang cited for this feature, Applicant’s suggests that the primitive sections merely store a number of primitives based on paragraph 18, which does not contradict Yang’s paragraphs 9 and 125. Applicant further suggests that paragraph 9 discloses that the primitive blocks may be prepared for “a (single) set of regions” but not “plural sets of regions”. Applicant’s suggestion is not an actual distinction with respect to the claim language, i.e. i.e. a single set of tiles can be both “a single set of regions”, i.e. 4 tiles make a single set of 4, and also plural sets of regions, i.e. 4 tiles can be two sets of 2, or four sets of 1. Furthermore, Applicant’s suggestion is contradicted, again, by Yang’s disclosure of paragraph 9, indicating the use of macro regions in addition to tiles, making up plural sets of regions, i.e. the macro regions and the tiles. Therefore, this argument is still contradicted by Yang’s disclosure.
Applicant suggests that the primitive sections and primitive blocks are “not used to indicate which primitive is to be processed when rendering”, on the basis of paragraph 10 of Yang. Applicant’s remarks are again contradicted by the disclosure of Yang, i.e. as in paragraph 9, the display lists comprise the primitive sections/blocks/lists and are used for rendering each tile, e.g. paragraphs 132-146 describes the generation of display lists comprising the primitive sections/blocks/lists for a corresponding tile. Therefore Applicant’s argument cannot be considered persuasive because it is clear that Yang’s display lists comprise the claimed primitive sections/blocks/lists.
Applicant’s argument further cannot be considered persuasive because it is incomplete, i.e. despite the context of Yang’s system being an accelerated graphics rendering system for rasterizing images for display from primitives, Applicant suggests that Yang is making lists of primitives for some purpose other than rendering, and fails to identify what that supposed other purpose, i.e. if Applicant’s position were reasonable, Applicant would be able to indicate the purpose of Yang’s generation of primitive sections/blocks/lists for a purpose entirely unrelated to rendering the primitives therein. Therefore this argument cannot be considered persuasive.
Applicant asserts that “there is no disclosure of Yang of preparing any primitive list pointer arrays indicating a location in storage of the display lists, let alone plural such primitive list pointer arrays”. Applicant’s assertion is irrelevant as there is no mapping on that basis, nor does Applicant’s claim recite such a limitation. Applicant further asserts on this basis that there is no suggestion to provide the claimed further pointer array, but fails to actually address either mapping for this feature, and therefore this assertion cannot be considered persuasive.
Applicant makes additional assertions regarding Yang failing to disclose storing pointers indicating the locations of primitive lists for respective regions, or a further pointer array storing locations for primitive list pointer arrays, but again fails to actually address the mappings of the rejection, or otherwise show that the cited portions of Yang do not anticipate the claim limitations. Instead Applicant’s argument is a conclusory statement lacking supporting rationale, which cannot be considered persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERT BADER/Primary Examiner, Art Unit 2611